[deliverable/linux.git] / arch / mips / mm / uasm.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * A small micro-assembler. It is intentionally kept simple, does only
 * support a subset of instructions, and does not try to hide pipeline
 * effects like branch delay slots.
 *
 * Copyright (C) 2004, 2005, 2006, 2008	 Thiemo Seufer
 * Copyright (C) 2005, 2007  Maciej W. Rozycki
 * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
 * Copyright (C) 2012, 2013  MIPS Technologies, Inc.  All rights reserved.
 */

enum fields {
	RS = 0x001,
	RT = 0x002,
	RD = 0x004,
	RE = 0x008,
	SIMM = 0x010,
	UIMM = 0x020,
	BIMM = 0x040,
	JIMM = 0x080,
	FUNC = 0x100,
	SET = 0x200,
	SCIMM = 0x400,
	SIMM9 = 0x800,
};

#define OP_MASK		0x3f
#define OP_SH		26
#define RD_MASK		0x1f
#define RD_SH		11
#define RE_MASK		0x1f
#define RE_SH		6
#define IMM_MASK	0xffff
#define IMM_SH		0
#define JIMM_MASK	0x3ffffff
#define JIMM_SH		0
#define FUNC_MASK	0x3f
#define FUNC_SH		0
#define SET_MASK	0x7
#define SET_SH		0
#define SIMM9_SH	7
#define SIMM9_MASK	0x1ff

enum opcode {
	insn_invalid,
	insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
	insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
	insn_bne, insn_cache, insn_cfc1, insn_cfcmsa, insn_ctc1, insn_ctcmsa,
	insn_daddiu, insn_daddu, insn_dins, insn_dinsm, insn_divu, insn_dmfc0,
	insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll, insn_dsll32, insn_dsra,
	insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret, insn_ext, insn_ins,
	insn_j, insn_jal, insn_jalr, insn_jr, insn_lb, insn_ld, insn_ldx,
	insn_lh, insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, insn_mfc0,
	insn_mfhc0, insn_mfhi, insn_mflo, insn_mtc0, insn_mthc0, insn_mul,
	insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd,
	insn_sd, insn_sll, insn_sllv, insn_slt, insn_sltiu, insn_sltu, insn_sra,
	insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall,
	insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh,
	insn_xor, insn_xori, insn_yield, insn_lddir, insn_ldpte,
};

struct insn {
	enum opcode opcode;
	u32 match;
	enum fields fields;
};

static inline u32 build_rs(u32 arg)
{
	WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & RS_MASK) << RS_SH;
}

static inline u32 build_rt(u32 arg)
{
	WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & RT_MASK) << RT_SH;
}

static inline u32 build_rd(u32 arg)
{
	WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & RD_MASK) << RD_SH;
}

static inline u32 build_re(u32 arg)
{
	WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & RE_MASK) << RE_SH;
}

static inline u32 build_simm(s32 arg)
{
	WARN(arg > 0x7fff || arg < -0x8000,
	     KERN_WARNING "Micro-assembler field overflow\n");

	return arg & 0xffff;
}

static inline u32 build_uimm(u32 arg)
{
	WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return arg & IMM_MASK;
}

static inline u32 build_scimm(u32 arg)
{
	WARN(arg & ~SCIMM_MASK,
	     KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & SCIMM_MASK) << SCIMM_SH;
}

static inline u32 build_scimm9(s32 arg)
{
	WARN((arg > 0xff || arg < -0x100),
	       KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & SIMM9_MASK) << SIMM9_SH;
}

static inline u32 build_func(u32 arg)
{
	WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return arg & FUNC_MASK;
}

static inline u32 build_set(u32 arg)
{
	WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return arg & SET_MASK;
}

static void build_insn(u32 **buf, enum opcode opc, ...);

#define I_u1u2u3(op)					\
Ip_u1u2u3(op)						\
{							\
	build_insn(buf, insn##op, a, b, c);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_s3s1s2(op)					\
Ip_s3s1s2(op)						\
{							\
	build_insn(buf, insn##op, b, c, a);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2u1u3(op)					\
Ip_u2u1u3(op)						\
{							\
	build_insn(buf, insn##op, b, a, c);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u3u2u1(op)					\
Ip_u3u2u1(op)						\
{							\
	build_insn(buf, insn##op, c, b, a);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u3u1u2(op)					\
Ip_u3u1u2(op)						\
{							\
	build_insn(buf, insn##op, b, c, a);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u1u2s3(op)					\
Ip_u1u2s3(op)						\
{							\
	build_insn(buf, insn##op, a, b, c);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2s3u1(op)					\
Ip_u2s3u1(op)						\
{							\
	build_insn(buf, insn##op, c, a, b);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2u1s3(op)					\
Ip_u2u1s3(op)						\
{							\
	build_insn(buf, insn##op, b, a, c);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2u1msbu3(op)					\
Ip_u2u1msbu3(op)					\
{							\
	build_insn(buf, insn##op, b, a, c+d-1, c);	\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2u1msb32u3(op)				\
Ip_u2u1msbu3(op)					\
{							\
	build_insn(buf, insn##op, b, a, c+d-33, c);	\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2u1msbdu3(op)				\
Ip_u2u1msbu3(op)					\
{							\
	build_insn(buf, insn##op, b, a, d-1, c);	\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u1u2(op)					\
Ip_u1u2(op)						\
{							\
	build_insn(buf, insn##op, a, b);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2u1(op)					\
Ip_u1u2(op)						\
{							\
	build_insn(buf, insn##op, b, a);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u1s2(op)					\
Ip_u1s2(op)						\
{							\
	build_insn(buf, insn##op, a, b);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u1(op)					\
Ip_u1(op)						\
{							\
	build_insn(buf, insn##op, a);			\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_0(op)						\
Ip_0(op)						\
{							\
	build_insn(buf, insn##op);			\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

I_u2u1s3(_addiu)
I_u3u1u2(_addu)
I_u2u1u3(_andi)
I_u3u1u2(_and)
I_u1u2s3(_beq)
I_u1u2s3(_beql)
I_u1s2(_bgez)
I_u1s2(_bgezl)
I_u1s2(_bltz)
I_u1s2(_bltzl)
I_u1u2s3(_bne)
I_u2s3u1(_cache)
I_u1u2(_cfc1)
I_u2u1(_cfcmsa)
I_u1u2(_ctc1)
I_u2u1(_ctcmsa)
I_u1u2u3(_dmfc0)
I_u1u2u3(_dmtc0)
I_u2u1s3(_daddiu)
I_u3u1u2(_daddu)
I_u1u2(_divu)
I_u2u1u3(_dsll)
I_u2u1u3(_dsll32)
I_u2u1u3(_dsra)
I_u2u1u3(_dsrl)
I_u2u1u3(_dsrl32)
I_u2u1u3(_drotr)
I_u2u1u3(_drotr32)
I_u3u1u2(_dsubu)
I_0(_eret)
I_u2u1msbdu3(_ext)
I_u2u1msbu3(_ins)
I_u1(_j)
I_u1(_jal)
I_u2u1(_jalr)
I_u1(_jr)
I_u2s3u1(_lb)
I_u2s3u1(_ld)
I_u2s3u1(_lh)
I_u2s3u1(_ll)
I_u2s3u1(_lld)
I_u1s2(_lui)
I_u2s3u1(_lw)
I_u1u2u3(_mfc0)
I_u1u2u3(_mfhc0)
I_u1(_mfhi)
I_u1(_mflo)
I_u1u2u3(_mtc0)
I_u1u2u3(_mthc0)
I_u3u1u2(_mul)
I_u2u1u3(_ori)
I_u3u1u2(_or)
I_0(_rfe)
I_u2s3u1(_sc)
I_u2s3u1(_scd)
I_u2s3u1(_sd)
I_u2u1u3(_sll)
I_u3u2u1(_sllv)
I_s3s1s2(_slt)
I_u2u1s3(_sltiu)
I_u3u1u2(_sltu)
I_u2u1u3(_sra)
I_u2u1u3(_srl)
I_u3u2u1(_srlv)
I_u2u1u3(_rotr)
I_u3u1u2(_subu)
I_u2s3u1(_sw)
I_u1(_sync)
I_0(_tlbp)
I_0(_tlbr)
I_0(_tlbwi)
I_0(_tlbwr)
I_u1(_wait);
I_u2u1(_wsbh)
I_u3u1u2(_xor)
I_u2u1u3(_xori)
I_u2u1(_yield)
I_u2u1msbu3(_dins);
I_u2u1msb32u3(_dinsm);
I_u1(_syscall);
I_u1u2s3(_bbit0);
I_u1u2s3(_bbit1);
I_u3u1u2(_lwx)
I_u3u1u2(_ldx)
I_u1u2(_ldpte)
I_u2u1u3(_lddir)

#ifdef CONFIG_CPU_CAVIUM_OCTEON
#include <asm/octeon/octeon.h>
void ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b,
			    unsigned int c)
{
	if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR && a <= 24 && a != 5)
		/*
		 * As per erratum Core-14449, replace prefetches 0-4,
		 * 6-24 with 'pref 28'.
		 */
		build_insn(buf, insn_pref, c, 28, b);
	else
		build_insn(buf, insn_pref, c, a, b);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_i_pref));
#else
I_u2s3u1(_pref)
#endif

/* Handle labels. */
void ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr, int lid)
{
	(*lab)->addr = addr;
	(*lab)->lab = lid;
	(*lab)++;
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_build_label));

int ISAFUNC(uasm_in_compat_space_p)(long addr)
{
	/* Is this address in 32bit compat space? */
#ifdef CONFIG_64BIT
	return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
#else
	return 1;
#endif
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_in_compat_space_p));

static int uasm_rel_highest(long val)
{
#ifdef CONFIG_64BIT
	return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
#else
	return 0;
#endif
}

static int uasm_rel_higher(long val)
{
#ifdef CONFIG_64BIT
	return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
#else
	return 0;
#endif
}

int ISAFUNC(uasm_rel_hi)(long val)
{
	return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_hi));

int ISAFUNC(uasm_rel_lo)(long val)
{
	return ((val & 0xffff) ^ 0x8000) - 0x8000;
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_lo));

void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr)
{
	if (!ISAFUNC(uasm_in_compat_space_p)(addr)) {
		ISAFUNC(uasm_i_lui)(buf, rs, uasm_rel_highest(addr));
		if (uasm_rel_higher(addr))
			ISAFUNC(uasm_i_daddiu)(buf, rs, rs, uasm_rel_higher(addr));
		if (ISAFUNC(uasm_rel_hi(addr))) {
			ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
			ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
					ISAFUNC(uasm_rel_hi)(addr));
			ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
		} else
			ISAFUNC(uasm_i_dsll32)(buf, rs, rs, 0);
	} else
		ISAFUNC(uasm_i_lui)(buf, rs, ISAFUNC(uasm_rel_hi(addr)));
}
UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA_mostly));

void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr)
{
	ISAFUNC(UASM_i_LA_mostly)(buf, rs, addr);
	if (ISAFUNC(uasm_rel_lo(addr))) {
		if (!ISAFUNC(uasm_in_compat_space_p)(addr))
			ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
					ISAFUNC(uasm_rel_lo(addr)));
		else
			ISAFUNC(uasm_i_addiu)(buf, rs, rs,
					ISAFUNC(uasm_rel_lo(addr)));
	}
}
UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA));

/* Handle relocations. */
void ISAFUNC(uasm_r_mips_pc16)(struct uasm_reloc **rel, u32 *addr, int lid)
{
	(*rel)->addr = addr;
	(*rel)->type = R_MIPS_PC16;
	(*rel)->lab = lid;
	(*rel)++;
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_r_mips_pc16));

static inline void __resolve_relocs(struct uasm_reloc *rel,
				    struct uasm_label *lab);

void ISAFUNC(uasm_resolve_relocs)(struct uasm_reloc *rel,
				  struct uasm_label *lab)
{
	struct uasm_label *l;

	for (; rel->lab != UASM_LABEL_INVALID; rel++)
		for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
			if (rel->lab == l->lab)
				__resolve_relocs(rel, l);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_resolve_relocs));

void ISAFUNC(uasm_move_relocs)(struct uasm_reloc *rel, u32 *first, u32 *end,
			       long off)
{
	for (; rel->lab != UASM_LABEL_INVALID; rel++)
		if (rel->addr >= first && rel->addr < end)
			rel->addr += off;
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_relocs));

void ISAFUNC(uasm_move_labels)(struct uasm_label *lab, u32 *first, u32 *end,
			       long off)
{
	for (; lab->lab != UASM_LABEL_INVALID; lab++)
		if (lab->addr >= first && lab->addr < end)
			lab->addr += off;
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_labels));

void ISAFUNC(uasm_copy_handler)(struct uasm_reloc *rel, struct uasm_label *lab,
				u32 *first, u32 *end, u32 *target)
{
	long off = (long)(target - first);

	memcpy(target, first, (end - first) * sizeof(u32));

	ISAFUNC(uasm_move_relocs(rel, first, end, off));
	ISAFUNC(uasm_move_labels(lab, first, end, off));
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_copy_handler));

int ISAFUNC(uasm_insn_has_bdelay)(struct uasm_reloc *rel, u32 *addr)
{
	for (; rel->lab != UASM_LABEL_INVALID; rel++) {
		if (rel->addr == addr
		    && (rel->type == R_MIPS_PC16
			|| rel->type == R_MIPS_26))
			return 1;
	}

	return 0;
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_insn_has_bdelay));

/* Convenience functions for labeled branches. */
void ISAFUNC(uasm_il_bltz)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			   int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_bltz)(p, reg, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bltz));

void ISAFUNC(uasm_il_b)(u32 **p, struct uasm_reloc **r, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_b)(p, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_b));

void ISAFUNC(uasm_il_beq)(u32 **p, struct uasm_reloc **r, unsigned int r1,
			  unsigned int r2, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_beq)(p, r1, r2, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beq));

void ISAFUNC(uasm_il_beqz)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			   int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_beqz)(p, reg, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqz));

void ISAFUNC(uasm_il_beqzl)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			    int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_beqzl)(p, reg, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqzl));

void ISAFUNC(uasm_il_bne)(u32 **p, struct uasm_reloc **r, unsigned int reg1,
			  unsigned int reg2, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_bne)(p, reg1, reg2, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bne));

void ISAFUNC(uasm_il_bnez)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			   int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_bnez)(p, reg, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bnez));

void ISAFUNC(uasm_il_bgezl)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			    int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_bgezl)(p, reg, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgezl));

void ISAFUNC(uasm_il_bgez)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			   int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_bgez)(p, reg, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgez));

void ISAFUNC(uasm_il_bbit0)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			    unsigned int bit, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_bbit0)(p, reg, bit, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit0));

void ISAFUNC(uasm_il_bbit1)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			    unsigned int bit, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_bbit1)(p, reg, bit, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit1));
Commit	Line	Data
e30ec452 TS	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* A small micro-assembler. It is intentionally kept simple, does only
	7	* support a subset of instructions, and does not try to hide pipeline
	8	* effects like branch delay slots.
	9	*
70342287	10	* Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
e30ec452 TS	11	* Copyright (C) 2005, 2007 Maciej W. Rozycki
e30ec452 TS	12	* Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
abc597fe	13	* Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved.
e30ec452 TS	14	*/
e30ec452 TS	15
e30ec452 TS	16	enum fields {
	17	RS = 0x001,
	18	RT = 0x002,
	19	RD = 0x004,
	20	RE = 0x008,
	21	SIMM = 0x010,
	22	UIMM = 0x020,
	23	BIMM = 0x040,
	24	JIMM = 0x080,
	25	FUNC = 0x100,
58b9e223	26	SET = 0x200,
51eec48e LY	27	SCIMM = 0x400,
51eec48e LY	28	SIMM9 = 0x800,
e30ec452 TS	29	};
	30
	31	#define OP_MASK 0x3f
	32	#define OP_SH 26
e30ec452 TS	33	#define RD_MASK 0x1f
	34	#define RD_SH 11
	35	#define RE_MASK 0x1f
	36	#define RE_SH 6
	37	#define IMM_MASK 0xffff
	38	#define IMM_SH 0
	39	#define JIMM_MASK 0x3ffffff
	40	#define JIMM_SH 0
	41	#define FUNC_MASK 0x3f
	42	#define FUNC_SH 0
	43	#define SET_MASK 0x7
	44	#define SET_SH 0
51eec48e LY	45	#define SIMM9_SH 7
51eec48e LY	46	#define SIMM9_MASK 0x1ff
e30ec452 TS	47
	48	enum opcode {
	49	insn_invalid,
71a1c776 SH	50	insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
71a1c776 SH	51	insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
59e3559f JH	52	insn_bne, insn_cache, insn_cfc1, insn_cfcmsa, insn_ctc1, insn_ctcmsa,
	53	insn_daddiu, insn_daddu, insn_dins, insn_dinsm, insn_divu, insn_dmfc0,
	54	insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll, insn_dsll32, insn_dsra,
	55	insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret, insn_ext, insn_ins,
	56	insn_j, insn_jal, insn_jalr, insn_jr, insn_lb, insn_ld, insn_ldx,
	57	insn_lh, insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, insn_mfc0,
	58	insn_mfhc0, insn_mfhi, insn_mflo, insn_mtc0, insn_mthc0, insn_mul,
	59	insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd,
	60	insn_sd, insn_sll, insn_sllv, insn_slt, insn_sltiu, insn_sltu, insn_sra,
	61	insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall,
	62	insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh,
	63	insn_xor, insn_xori, insn_yield, insn_lddir, insn_ldpte,
e30ec452 TS	64	};
	65
	66	struct insn {
	67	enum opcode opcode;
	68	u32 match;
	69	enum fields fields;
	70	};
	71
078a55fc	72	static inline u32 build_rs(u32 arg)
e30ec452	73	{
8d662c8d	74	WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	75
	76	return (arg & RS_MASK) << RS_SH;
	77	}
	78
078a55fc	79	static inline u32 build_rt(u32 arg)
e30ec452	80	{
8d662c8d	81	WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	82
	83	return (arg & RT_MASK) << RT_SH;
	84	}
	85
078a55fc	86	static inline u32 build_rd(u32 arg)
e30ec452	87	{
8d662c8d	88	WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	89
	90	return (arg & RD_MASK) << RD_SH;
	91	}
	92
078a55fc	93	static inline u32 build_re(u32 arg)
e30ec452	94	{
8d662c8d	95	WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	96
	97	return (arg & RE_MASK) << RE_SH;
	98	}
	99
078a55fc	100	static inline u32 build_simm(s32 arg)
e30ec452	101	{
8d662c8d DD	102	WARN(arg > 0x7fff \|\| arg < -0x8000,
8d662c8d DD	103	KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	104
	105	return arg & 0xffff;
	106	}
	107
078a55fc	108	static inline u32 build_uimm(u32 arg)
e30ec452	109	{
8d662c8d	110	WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	111
	112	return arg & IMM_MASK;
	113	}
	114
078a55fc	115	static inline u32 build_scimm(u32 arg)
58b9e223	116	{
8d662c8d DD	117	WARN(arg & ~SCIMM_MASK,
8d662c8d DD	118	KERN_WARNING "Micro-assembler field overflow\n");
58b9e223 DD	119
	120	return (arg & SCIMM_MASK) << SCIMM_SH;
	121	}
	122
51eec48e LY	123	static inline u32 build_scimm9(s32 arg)
	124	{
	125	WARN((arg > 0xff \|\| arg < -0x100),
	126	KERN_WARNING "Micro-assembler field overflow\n");
	127
	128	return (arg & SIMM9_MASK) << SIMM9_SH;
	129	}
	130
078a55fc	131	static inline u32 build_func(u32 arg)
e30ec452	132	{
8d662c8d	133	WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	134
	135	return arg & FUNC_MASK;
	136	}
	137
078a55fc	138	static inline u32 build_set(u32 arg)
e30ec452	139	{
8d662c8d	140	WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	141
	142	return arg & SET_MASK;
	143	}
	144
078a55fc	145	static void build_insn(u32 **buf, enum opcode opc, ...);
e30ec452 TS	146
	147	#define I_u1u2u3(op) \
	148	Ip_u1u2u3(op) \
	149	{ \
	150	build_insn(buf, insn##op, a, b, c); \
22b0763a DD	151	} \
22b0763a DD	152	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452	153
9d987369 MC	154	#define I_s3s1s2(op) \
	155	Ip_s3s1s2(op) \
	156	{ \
	157	build_insn(buf, insn##op, b, c, a); \
	158	} \
	159	UASM_EXPORT_SYMBOL(uasm_i##op);
	160
e30ec452 TS	161	#define I_u2u1u3(op) \
	162	Ip_u2u1u3(op) \
	163	{ \
	164	build_insn(buf, insn##op, b, a, c); \
22b0763a DD	165	} \
22b0763a DD	166	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452	167
beef8e02 MC	168	#define I_u3u2u1(op) \
	169	Ip_u3u2u1(op) \
	170	{ \
	171	build_insn(buf, insn##op, c, b, a); \
	172	} \
	173	UASM_EXPORT_SYMBOL(uasm_i##op);
	174
e30ec452 TS	175	#define I_u3u1u2(op) \
	176	Ip_u3u1u2(op) \
	177	{ \
	178	build_insn(buf, insn##op, b, c, a); \
22b0763a DD	179	} \
22b0763a DD	180	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452 TS	181
	182	#define I_u1u2s3(op) \
	183	Ip_u1u2s3(op) \
	184	{ \
	185	build_insn(buf, insn##op, a, b, c); \
22b0763a DD	186	} \
22b0763a DD	187	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452 TS	188
	189	#define I_u2s3u1(op) \
	190	Ip_u2s3u1(op) \
	191	{ \
	192	build_insn(buf, insn##op, c, a, b); \
22b0763a DD	193	} \
22b0763a DD	194	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452 TS	195
	196	#define I_u2u1s3(op) \
	197	Ip_u2u1s3(op) \
	198	{ \
	199	build_insn(buf, insn##op, b, a, c); \
22b0763a DD	200	} \
22b0763a DD	201	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452	202
92078e06 DD	203	#define I_u2u1msbu3(op) \
	204	Ip_u2u1msbu3(op) \
	205	{ \
	206	build_insn(buf, insn##op, b, a, c+d-1, c); \
22b0763a DD	207	} \
22b0763a DD	208	UASM_EXPORT_SYMBOL(uasm_i##op);
92078e06	209
c42aef09 DD	210	#define I_u2u1msb32u3(op) \
	211	Ip_u2u1msbu3(op) \
	212	{ \
	213	build_insn(buf, insn##op, b, a, c+d-33, c); \
	214	} \
	215	UASM_EXPORT_SYMBOL(uasm_i##op);
	216
70342287	217	#define I_u2u1msbdu3(op) \
e6de1a09 SH	218	Ip_u2u1msbu3(op) \
	219	{ \
	220	build_insn(buf, insn##op, b, a, d-1, c); \
	221	} \
	222	UASM_EXPORT_SYMBOL(uasm_i##op);
	223
e30ec452 TS	224	#define I_u1u2(op) \
	225	Ip_u1u2(op) \
	226	{ \
	227	build_insn(buf, insn##op, a, b); \
22b0763a DD	228	} \
22b0763a DD	229	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452	230
d674dd14 PB	231	#define I_u2u1(op) \
	232	Ip_u1u2(op) \
	233	{ \
	234	build_insn(buf, insn##op, b, a); \
	235	} \
	236	UASM_EXPORT_SYMBOL(uasm_i##op);
	237
e30ec452 TS	238	#define I_u1s2(op) \
	239	Ip_u1s2(op) \
	240	{ \
	241	build_insn(buf, insn##op, a, b); \
22b0763a DD	242	} \
22b0763a DD	243	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452 TS	244
	245	#define I_u1(op) \
	246	Ip_u1(op) \
	247	{ \
	248	build_insn(buf, insn##op, a); \
22b0763a DD	249	} \
22b0763a DD	250	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452 TS	251
	252	#define I_0(op) \
	253	Ip_0(op) \
	254	{ \
	255	build_insn(buf, insn##op); \
22b0763a DD	256	} \
22b0763a DD	257	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452 TS	258
	259	I_u2u1s3(_addiu)
	260	I_u3u1u2(_addu)
	261	I_u2u1u3(_andi)
	262	I_u3u1u2(_and)
	263	I_u1u2s3(_beq)
	264	I_u1u2s3(_beql)
	265	I_u1s2(_bgez)
	266	I_u1s2(_bgezl)
	267	I_u1s2(_bltz)
	268	I_u1s2(_bltzl)
	269	I_u1u2s3(_bne)
fb2a27e7	270	I_u2s3u1(_cache)
c29732a1	271	I_u1u2(_cfc1)
59e3559f	272	I_u2u1(_cfcmsa)
c29732a1	273	I_u1u2(_ctc1)
59e3559f	274	I_u2u1(_ctcmsa)
e30ec452 TS	275	I_u1u2u3(_dmfc0)
	276	I_u1u2u3(_dmtc0)
	277	I_u2u1s3(_daddiu)
	278	I_u3u1u2(_daddu)
4c12a854	279	I_u1u2(_divu)
e30ec452 TS	280	I_u2u1u3(_dsll)
	281	I_u2u1u3(_dsll32)
	282	I_u2u1u3(_dsra)
	283	I_u2u1u3(_dsrl)
	284	I_u2u1u3(_dsrl32)
92078e06	285	I_u2u1u3(_drotr)
de6d5b55	286	I_u2u1u3(_drotr32)
e30ec452 TS	287	I_u3u1u2(_dsubu)
e30ec452 TS	288	I_0(_eret)
e6de1a09 SH	289	I_u2u1msbdu3(_ext)
e6de1a09 SH	290	I_u2u1msbu3(_ins)
e30ec452 TS	291	I_u1(_j)
e30ec452 TS	292	I_u1(_jal)
49e9529b	293	I_u2u1(_jalr)
e30ec452	294	I_u1(_jr)
82488818	295	I_u2s3u1(_lb)
e30ec452	296	I_u2s3u1(_ld)
d6b3314b	297	I_u2s3u1(_lh)
e30ec452 TS	298	I_u2s3u1(_ll)
	299	I_u2s3u1(_lld)
	300	I_u1s2(_lui)
	301	I_u2s3u1(_lw)
	302	I_u1u2u3(_mfc0)
e2965cd0	303	I_u1u2u3(_mfhc0)
f3ec7a23	304	I_u1(_mfhi)
16d21a81	305	I_u1(_mflo)
e30ec452	306	I_u1u2u3(_mtc0)
e2965cd0	307	I_u1u2u3(_mthc0)
a8e897ad	308	I_u3u1u2(_mul)
e30ec452	309	I_u2u1u3(_ori)
5808184f	310	I_u3u1u2(_or)
e30ec452 TS	311	I_0(_rfe)
	312	I_u2s3u1(_sc)
	313	I_u2s3u1(_scd)
	314	I_u2s3u1(_sd)
	315	I_u2u1u3(_sll)
bef581ba	316	I_u3u2u1(_sllv)
7682f9e8	317	I_s3s1s2(_slt)
390363ed	318	I_u2u1s3(_sltiu)
e8ef868b	319	I_u3u1u2(_sltu)
e30ec452 TS	320	I_u2u1u3(_sra)
e30ec452 TS	321	I_u2u1u3(_srl)
f31318fd	322	I_u3u2u1(_srlv)
32546f38	323	I_u2u1u3(_rotr)
e30ec452 TS	324	I_u3u1u2(_subu)
e30ec452 TS	325	I_u2s3u1(_sw)
729ff561	326	I_u1(_sync)
e30ec452	327	I_0(_tlbp)
32546f38	328	I_0(_tlbr)
e30ec452 TS	329	I_0(_tlbwi)
e30ec452 TS	330	I_0(_tlbwr)
53ed1389	331	I_u1(_wait);
ab9e4fa0	332	I_u2u1(_wsbh)
e30ec452 TS	333	I_u3u1u2(_xor)
e30ec452 TS	334	I_u2u1u3(_xori)
d674dd14	335	I_u2u1(_yield)
92078e06	336	I_u2u1msbu3(_dins);
c42aef09	337	I_u2u1msb32u3(_dinsm);
58b9e223	338	I_u1(_syscall);
5b97c3f7 DD	339	I_u1u2s3(_bbit0);
5b97c3f7 DD	340	I_u1u2s3(_bbit1);
bb3d68c3 DD	341	I_u3u1u2(_lwx)
bb3d68c3 DD	342	I_u3u1u2(_ldx)
380cd582 HC	343	I_u1u2(_ldpte)
380cd582 HC	344	I_u2u1u3(_lddir)
e30ec452	345
c9941158 DD	346	#ifdef CONFIG_CPU_CAVIUM_OCTEON
c9941158 DD	347	#include <asm/octeon/octeon.h>
078a55fc	348	void ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b,
c9941158 DD	349	unsigned int c)
c9941158 DD	350	{
e3d0ead5	351	if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR && a <= 24 && a != 5)
c9941158 DD	352	/*
	353	* As per erratum Core-14449, replace prefetches 0-4,
	354	* 6-24 with 'pref 28'.
	355	*/
	356	build_insn(buf, insn_pref, c, 28, b);
	357	else
	358	build_insn(buf, insn_pref, c, a, b);
	359	}
abc597fe	360	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_i_pref));
c9941158 DD	361	#else
	362	I_u2s3u1(_pref)
	363	#endif
	364
e30ec452	365	/* Handle labels. */
078a55fc	366	void ISAFUNC(uasm_build_label)(struct uasm_label *lab, u32 addr, int lid)
e30ec452 TS	367	{
	368	(*lab)->addr = addr;
	369	(*lab)->lab = lid;
	370	(*lab)++;
	371	}
abc597fe	372	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_build_label));
e30ec452	373
078a55fc	374	int ISAFUNC(uasm_in_compat_space_p)(long addr)
e30ec452 TS	375	{
	376	/* Is this address in 32bit compat space? */
	377	#ifdef CONFIG_64BIT
	378	return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
	379	#else
	380	return 1;
	381	#endif
	382	}
abc597fe	383	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_in_compat_space_p));
e30ec452	384
078a55fc	385	static int uasm_rel_highest(long val)
e30ec452 TS	386	{
	387	#ifdef CONFIG_64BIT
	388	return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
	389	#else
	390	return 0;
	391	#endif
	392	}
	393
078a55fc	394	static int uasm_rel_higher(long val)
e30ec452 TS	395	{
	396	#ifdef CONFIG_64BIT
	397	return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
	398	#else
	399	return 0;
	400	#endif
	401	}
	402
078a55fc	403	int ISAFUNC(uasm_rel_hi)(long val)
e30ec452 TS	404	{
	405	return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
	406	}
abc597fe	407	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_hi));
e30ec452	408
078a55fc	409	int ISAFUNC(uasm_rel_lo)(long val)
e30ec452 TS	410	{
	411	return ((val & 0xffff) ^ 0x8000) - 0x8000;
	412	}
abc597fe	413	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_lo));
e30ec452	414
078a55fc	415	void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr)
e30ec452	416	{
abc597fe SH	417	if (!ISAFUNC(uasm_in_compat_space_p)(addr)) {
abc597fe SH	418	ISAFUNC(uasm_i_lui)(buf, rs, uasm_rel_highest(addr));
e30ec452	419	if (uasm_rel_higher(addr))
abc597fe SH	420	ISAFUNC(uasm_i_daddiu)(buf, rs, rs, uasm_rel_higher(addr));
	421	if (ISAFUNC(uasm_rel_hi(addr))) {
	422	ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
	423	ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
	424	ISAFUNC(uasm_rel_hi)(addr));
	425	ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
e30ec452	426	} else
abc597fe	427	ISAFUNC(uasm_i_dsll32)(buf, rs, rs, 0);
e30ec452	428	} else
abc597fe	429	ISAFUNC(uasm_i_lui)(buf, rs, ISAFUNC(uasm_rel_hi(addr)));
e30ec452	430	}
abc597fe	431	UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA_mostly));
e30ec452	432
078a55fc	433	void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr)
e30ec452	434	{
abc597fe SH	435	ISAFUNC(UASM_i_LA_mostly)(buf, rs, addr);
	436	if (ISAFUNC(uasm_rel_lo(addr))) {
	437	if (!ISAFUNC(uasm_in_compat_space_p)(addr))
	438	ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
	439	ISAFUNC(uasm_rel_lo(addr)));
e30ec452	440	else
abc597fe SH	441	ISAFUNC(uasm_i_addiu)(buf, rs, rs,
abc597fe SH	442	ISAFUNC(uasm_rel_lo(addr)));
e30ec452 TS	443	}
e30ec452 TS	444	}
abc597fe	445	UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA));
e30ec452 TS	446
e30ec452 TS	447	/* Handle relocations. */
078a55fc	448	void ISAFUNC(uasm_r_mips_pc16)(struct uasm_reloc *rel, u32 addr, int lid)
e30ec452 TS	449	{
	450	(*rel)->addr = addr;
	451	(*rel)->type = R_MIPS_PC16;
	452	(*rel)->lab = lid;
	453	(*rel)++;
	454	}
abc597fe	455	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_r_mips_pc16));
e30ec452	456
078a55fc PG	457	static inline void __resolve_relocs(struct uasm_reloc *rel,
078a55fc PG	458	struct uasm_label *lab);
e30ec452	459
078a55fc PG	460	void ISAFUNC(uasm_resolve_relocs)(struct uasm_reloc *rel,
078a55fc PG	461	struct uasm_label *lab)
e30ec452 TS	462	{
	463	struct uasm_label *l;
	464
	465	for (; rel->lab != UASM_LABEL_INVALID; rel++)
	466	for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
	467	if (rel->lab == l->lab)
	468	__resolve_relocs(rel, l);
	469	}
abc597fe	470	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_resolve_relocs));
e30ec452	471
078a55fc PG	472	void ISAFUNC(uasm_move_relocs)(struct uasm_reloc rel, u32 first, u32 *end,
078a55fc PG	473	long off)
e30ec452 TS	474	{
	475	for (; rel->lab != UASM_LABEL_INVALID; rel++)
	476	if (rel->addr >= first && rel->addr < end)
	477	rel->addr += off;
	478	}
abc597fe	479	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_relocs));
e30ec452	480
078a55fc PG	481	void ISAFUNC(uasm_move_labels)(struct uasm_label lab, u32 first, u32 *end,
078a55fc PG	482	long off)
e30ec452 TS	483	{
	484	for (; lab->lab != UASM_LABEL_INVALID; lab++)
	485	if (lab->addr >= first && lab->addr < end)
	486	lab->addr += off;
	487	}
abc597fe	488	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_labels));
e30ec452	489
078a55fc PG	490	void ISAFUNC(uasm_copy_handler)(struct uasm_reloc rel, struct uasm_label lab,
078a55fc PG	491	u32 first, u32 end, u32 *target)
e30ec452 TS	492	{
	493	long off = (long)(target - first);
	494
	495	memcpy(target, first, (end - first) * sizeof(u32));
	496
abc597fe SH	497	ISAFUNC(uasm_move_relocs(rel, first, end, off));
abc597fe SH	498	ISAFUNC(uasm_move_labels(lab, first, end, off));
e30ec452	499	}
abc597fe	500	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_copy_handler));
e30ec452	501
078a55fc	502	int ISAFUNC(uasm_insn_has_bdelay)(struct uasm_reloc rel, u32 addr)
e30ec452 TS	503	{
	504	for (; rel->lab != UASM_LABEL_INVALID; rel++) {
	505	if (rel->addr == addr
	506	&& (rel->type == R_MIPS_PC16
	507	\|\| rel->type == R_MIPS_26))
	508	return 1;
	509	}
	510
	511	return 0;
	512	}
abc597fe	513	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_insn_has_bdelay));
e30ec452 TS	514
e30ec452 TS	515	/* Convenience functions for labeled branches. */
078a55fc PG	516	void ISAFUNC(uasm_il_bltz)(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc PG	517	int lid)
e30ec452 TS	518	{
e30ec452 TS	519	uasm_r_mips_pc16(r, *p, lid);
abc597fe	520	ISAFUNC(uasm_i_bltz)(p, reg, 0);
e30ec452	521	}
abc597fe	522	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bltz));
e30ec452	523
078a55fc	524	void ISAFUNC(uasm_il_b)(u32 p, struct uasm_reloc r, int lid)
e30ec452 TS	525	{
e30ec452 TS	526	uasm_r_mips_pc16(r, *p, lid);
abc597fe	527	ISAFUNC(uasm_i_b)(p, 0);
e30ec452	528	}
abc597fe	529	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_b));
e30ec452	530
8dee5901 PB	531	void ISAFUNC(uasm_il_beq)(u32 p, struct uasm_reloc r, unsigned int r1,
	532	unsigned int r2, int lid)
	533	{
	534	uasm_r_mips_pc16(r, *p, lid);
	535	ISAFUNC(uasm_i_beq)(p, r1, r2, 0);
	536	}
	537	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beq));
	538
078a55fc PG	539	void ISAFUNC(uasm_il_beqz)(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc PG	540	int lid)
e30ec452 TS	541	{
e30ec452 TS	542	uasm_r_mips_pc16(r, *p, lid);
abc597fe	543	ISAFUNC(uasm_i_beqz)(p, reg, 0);
e30ec452	544	}
abc597fe	545	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqz));
e30ec452	546
078a55fc PG	547	void ISAFUNC(uasm_il_beqzl)(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc PG	548	int lid)
e30ec452 TS	549	{
e30ec452 TS	550	uasm_r_mips_pc16(r, *p, lid);
abc597fe	551	ISAFUNC(uasm_i_beqzl)(p, reg, 0);
e30ec452	552	}
abc597fe	553	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqzl));
e30ec452	554
078a55fc PG	555	void ISAFUNC(uasm_il_bne)(u32 p, struct uasm_reloc r, unsigned int reg1,
078a55fc PG	556	unsigned int reg2, int lid)
fb2a27e7 TS	557	{
fb2a27e7 TS	558	uasm_r_mips_pc16(r, *p, lid);
abc597fe	559	ISAFUNC(uasm_i_bne)(p, reg1, reg2, 0);
fb2a27e7	560	}
abc597fe	561	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bne));
fb2a27e7	562
078a55fc PG	563	void ISAFUNC(uasm_il_bnez)(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc PG	564	int lid)
e30ec452 TS	565	{
e30ec452 TS	566	uasm_r_mips_pc16(r, *p, lid);
abc597fe	567	ISAFUNC(uasm_i_bnez)(p, reg, 0);
e30ec452	568	}
abc597fe	569	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bnez));
e30ec452	570
078a55fc PG	571	void ISAFUNC(uasm_il_bgezl)(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc PG	572	int lid)
e30ec452 TS	573	{
e30ec452 TS	574	uasm_r_mips_pc16(r, *p, lid);
abc597fe	575	ISAFUNC(uasm_i_bgezl)(p, reg, 0);
e30ec452	576	}
abc597fe	577	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgezl));
e30ec452	578
078a55fc PG	579	void ISAFUNC(uasm_il_bgez)(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc PG	580	int lid)
e30ec452 TS	581	{
e30ec452 TS	582	uasm_r_mips_pc16(r, *p, lid);
abc597fe	583	ISAFUNC(uasm_i_bgez)(p, reg, 0);
e30ec452	584	}
abc597fe	585	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgez));
5b97c3f7	586
078a55fc PG	587	void ISAFUNC(uasm_il_bbit0)(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc PG	588	unsigned int bit, int lid)
5b97c3f7 DD	589	{
5b97c3f7 DD	590	uasm_r_mips_pc16(r, *p, lid);
abc597fe	591	ISAFUNC(uasm_i_bbit0)(p, reg, bit, 0);
5b97c3f7	592	}
abc597fe	593	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit0));
5b97c3f7	594
078a55fc PG	595	void ISAFUNC(uasm_il_bbit1)(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc PG	596	unsigned int bit, int lid)
5b97c3f7 DD	597	{
5b97c3f7 DD	598	uasm_r_mips_pc16(r, *p, lid);
abc597fe	599	ISAFUNC(uasm_i_bbit1)(p, reg, bit, 0);
5b97c3f7	600	}
abc597fe	601	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit1));