Commit | Line | Data |
---|---|---|
e30ec452 TS |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * A small micro-assembler. It is intentionally kept simple, does only | |
7 | * support a subset of instructions, and does not try to hide pipeline | |
8 | * effects like branch delay slots. | |
9 | * | |
70342287 | 10 | * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer |
e30ec452 TS |
11 | * Copyright (C) 2005, 2007 Maciej W. Rozycki |
12 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) | |
abc597fe | 13 | * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved. |
e30ec452 TS |
14 | */ |
15 | ||
e30ec452 TS |
16 | enum fields { |
17 | RS = 0x001, | |
18 | RT = 0x002, | |
19 | RD = 0x004, | |
20 | RE = 0x008, | |
21 | SIMM = 0x010, | |
22 | UIMM = 0x020, | |
23 | BIMM = 0x040, | |
24 | JIMM = 0x080, | |
25 | FUNC = 0x100, | |
58b9e223 DD |
26 | SET = 0x200, |
27 | SCIMM = 0x400 | |
e30ec452 TS |
28 | }; |
29 | ||
30 | #define OP_MASK 0x3f | |
31 | #define OP_SH 26 | |
e30ec452 TS |
32 | #define RD_MASK 0x1f |
33 | #define RD_SH 11 | |
34 | #define RE_MASK 0x1f | |
35 | #define RE_SH 6 | |
36 | #define IMM_MASK 0xffff | |
37 | #define IMM_SH 0 | |
38 | #define JIMM_MASK 0x3ffffff | |
39 | #define JIMM_SH 0 | |
40 | #define FUNC_MASK 0x3f | |
41 | #define FUNC_SH 0 | |
42 | #define SET_MASK 0x7 | |
43 | #define SET_SH 0 | |
44 | ||
45 | enum opcode { | |
46 | insn_invalid, | |
71a1c776 SH |
47 | insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1, |
48 | insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl, | |
49 | insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dins, insn_dinsm, | |
4c12a854 | 50 | insn_divu, insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll, |
71a1c776 | 51 | insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret, |
49e9529b PB |
52 | insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_ld, |
53 | insn_ldx, insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, insn_mfc0, | |
f3ec7a23 MC |
54 | insn_mfhi, insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, |
55 | insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll, insn_sllv, insn_sra, | |
56 | insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall, | |
57 | insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_xor, | |
58 | insn_xori, insn_yield, | |
e30ec452 TS |
59 | }; |
60 | ||
61 | struct insn { | |
62 | enum opcode opcode; | |
63 | u32 match; | |
64 | enum fields fields; | |
65 | }; | |
66 | ||
078a55fc | 67 | static inline u32 build_rs(u32 arg) |
e30ec452 | 68 | { |
8d662c8d | 69 | WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n"); |
e30ec452 TS |
70 | |
71 | return (arg & RS_MASK) << RS_SH; | |
72 | } | |
73 | ||
078a55fc | 74 | static inline u32 build_rt(u32 arg) |
e30ec452 | 75 | { |
8d662c8d | 76 | WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n"); |
e30ec452 TS |
77 | |
78 | return (arg & RT_MASK) << RT_SH; | |
79 | } | |
80 | ||
078a55fc | 81 | static inline u32 build_rd(u32 arg) |
e30ec452 | 82 | { |
8d662c8d | 83 | WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n"); |
e30ec452 TS |
84 | |
85 | return (arg & RD_MASK) << RD_SH; | |
86 | } | |
87 | ||
078a55fc | 88 | static inline u32 build_re(u32 arg) |
e30ec452 | 89 | { |
8d662c8d | 90 | WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n"); |
e30ec452 TS |
91 | |
92 | return (arg & RE_MASK) << RE_SH; | |
93 | } | |
94 | ||
078a55fc | 95 | static inline u32 build_simm(s32 arg) |
e30ec452 | 96 | { |
8d662c8d DD |
97 | WARN(arg > 0x7fff || arg < -0x8000, |
98 | KERN_WARNING "Micro-assembler field overflow\n"); | |
e30ec452 TS |
99 | |
100 | return arg & 0xffff; | |
101 | } | |
102 | ||
078a55fc | 103 | static inline u32 build_uimm(u32 arg) |
e30ec452 | 104 | { |
8d662c8d | 105 | WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n"); |
e30ec452 TS |
106 | |
107 | return arg & IMM_MASK; | |
108 | } | |
109 | ||
078a55fc | 110 | static inline u32 build_scimm(u32 arg) |
58b9e223 | 111 | { |
8d662c8d DD |
112 | WARN(arg & ~SCIMM_MASK, |
113 | KERN_WARNING "Micro-assembler field overflow\n"); | |
58b9e223 DD |
114 | |
115 | return (arg & SCIMM_MASK) << SCIMM_SH; | |
116 | } | |
117 | ||
078a55fc | 118 | static inline u32 build_func(u32 arg) |
e30ec452 | 119 | { |
8d662c8d | 120 | WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n"); |
e30ec452 TS |
121 | |
122 | return arg & FUNC_MASK; | |
123 | } | |
124 | ||
078a55fc | 125 | static inline u32 build_set(u32 arg) |
e30ec452 | 126 | { |
8d662c8d | 127 | WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n"); |
e30ec452 TS |
128 | |
129 | return arg & SET_MASK; | |
130 | } | |
131 | ||
078a55fc | 132 | static void build_insn(u32 **buf, enum opcode opc, ...); |
e30ec452 TS |
133 | |
134 | #define I_u1u2u3(op) \ | |
135 | Ip_u1u2u3(op) \ | |
136 | { \ | |
137 | build_insn(buf, insn##op, a, b, c); \ | |
22b0763a DD |
138 | } \ |
139 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
e30ec452 TS |
140 | |
141 | #define I_u2u1u3(op) \ | |
142 | Ip_u2u1u3(op) \ | |
143 | { \ | |
144 | build_insn(buf, insn##op, b, a, c); \ | |
22b0763a DD |
145 | } \ |
146 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
e30ec452 | 147 | |
beef8e02 MC |
148 | #define I_u3u2u1(op) \ |
149 | Ip_u3u2u1(op) \ | |
150 | { \ | |
151 | build_insn(buf, insn##op, c, b, a); \ | |
152 | } \ | |
153 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
154 | ||
e30ec452 TS |
155 | #define I_u3u1u2(op) \ |
156 | Ip_u3u1u2(op) \ | |
157 | { \ | |
158 | build_insn(buf, insn##op, b, c, a); \ | |
22b0763a DD |
159 | } \ |
160 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
e30ec452 TS |
161 | |
162 | #define I_u1u2s3(op) \ | |
163 | Ip_u1u2s3(op) \ | |
164 | { \ | |
165 | build_insn(buf, insn##op, a, b, c); \ | |
22b0763a DD |
166 | } \ |
167 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
e30ec452 TS |
168 | |
169 | #define I_u2s3u1(op) \ | |
170 | Ip_u2s3u1(op) \ | |
171 | { \ | |
172 | build_insn(buf, insn##op, c, a, b); \ | |
22b0763a DD |
173 | } \ |
174 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
e30ec452 TS |
175 | |
176 | #define I_u2u1s3(op) \ | |
177 | Ip_u2u1s3(op) \ | |
178 | { \ | |
179 | build_insn(buf, insn##op, b, a, c); \ | |
22b0763a DD |
180 | } \ |
181 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
e30ec452 | 182 | |
92078e06 DD |
183 | #define I_u2u1msbu3(op) \ |
184 | Ip_u2u1msbu3(op) \ | |
185 | { \ | |
186 | build_insn(buf, insn##op, b, a, c+d-1, c); \ | |
22b0763a DD |
187 | } \ |
188 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
92078e06 | 189 | |
c42aef09 DD |
190 | #define I_u2u1msb32u3(op) \ |
191 | Ip_u2u1msbu3(op) \ | |
192 | { \ | |
193 | build_insn(buf, insn##op, b, a, c+d-33, c); \ | |
194 | } \ | |
195 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
196 | ||
70342287 | 197 | #define I_u2u1msbdu3(op) \ |
e6de1a09 SH |
198 | Ip_u2u1msbu3(op) \ |
199 | { \ | |
200 | build_insn(buf, insn##op, b, a, d-1, c); \ | |
201 | } \ | |
202 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
203 | ||
e30ec452 TS |
204 | #define I_u1u2(op) \ |
205 | Ip_u1u2(op) \ | |
206 | { \ | |
207 | build_insn(buf, insn##op, a, b); \ | |
22b0763a DD |
208 | } \ |
209 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
e30ec452 | 210 | |
d674dd14 PB |
211 | #define I_u2u1(op) \ |
212 | Ip_u1u2(op) \ | |
213 | { \ | |
214 | build_insn(buf, insn##op, b, a); \ | |
215 | } \ | |
216 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
217 | ||
e30ec452 TS |
218 | #define I_u1s2(op) \ |
219 | Ip_u1s2(op) \ | |
220 | { \ | |
221 | build_insn(buf, insn##op, a, b); \ | |
22b0763a DD |
222 | } \ |
223 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
e30ec452 TS |
224 | |
225 | #define I_u1(op) \ | |
226 | Ip_u1(op) \ | |
227 | { \ | |
228 | build_insn(buf, insn##op, a); \ | |
22b0763a DD |
229 | } \ |
230 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
e30ec452 TS |
231 | |
232 | #define I_0(op) \ | |
233 | Ip_0(op) \ | |
234 | { \ | |
235 | build_insn(buf, insn##op); \ | |
22b0763a DD |
236 | } \ |
237 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
e30ec452 TS |
238 | |
239 | I_u2u1s3(_addiu) | |
240 | I_u3u1u2(_addu) | |
241 | I_u2u1u3(_andi) | |
242 | I_u3u1u2(_and) | |
243 | I_u1u2s3(_beq) | |
244 | I_u1u2s3(_beql) | |
245 | I_u1s2(_bgez) | |
246 | I_u1s2(_bgezl) | |
247 | I_u1s2(_bltz) | |
248 | I_u1s2(_bltzl) | |
249 | I_u1u2s3(_bne) | |
fb2a27e7 | 250 | I_u2s3u1(_cache) |
e30ec452 TS |
251 | I_u1u2u3(_dmfc0) |
252 | I_u1u2u3(_dmtc0) | |
253 | I_u2u1s3(_daddiu) | |
254 | I_u3u1u2(_daddu) | |
4c12a854 | 255 | I_u1u2(_divu) |
e30ec452 TS |
256 | I_u2u1u3(_dsll) |
257 | I_u2u1u3(_dsll32) | |
258 | I_u2u1u3(_dsra) | |
259 | I_u2u1u3(_dsrl) | |
260 | I_u2u1u3(_dsrl32) | |
92078e06 | 261 | I_u2u1u3(_drotr) |
de6d5b55 | 262 | I_u2u1u3(_drotr32) |
e30ec452 TS |
263 | I_u3u1u2(_dsubu) |
264 | I_0(_eret) | |
e6de1a09 SH |
265 | I_u2u1msbdu3(_ext) |
266 | I_u2u1msbu3(_ins) | |
e30ec452 TS |
267 | I_u1(_j) |
268 | I_u1(_jal) | |
49e9529b | 269 | I_u2u1(_jalr) |
e30ec452 TS |
270 | I_u1(_jr) |
271 | I_u2s3u1(_ld) | |
272 | I_u2s3u1(_ll) | |
273 | I_u2s3u1(_lld) | |
274 | I_u1s2(_lui) | |
275 | I_u2s3u1(_lw) | |
276 | I_u1u2u3(_mfc0) | |
f3ec7a23 | 277 | I_u1(_mfhi) |
e30ec452 TS |
278 | I_u1u2u3(_mtc0) |
279 | I_u2u1u3(_ori) | |
5808184f | 280 | I_u3u1u2(_or) |
e30ec452 TS |
281 | I_0(_rfe) |
282 | I_u2s3u1(_sc) | |
283 | I_u2s3u1(_scd) | |
284 | I_u2s3u1(_sd) | |
285 | I_u2u1u3(_sll) | |
bef581ba | 286 | I_u3u2u1(_sllv) |
e30ec452 TS |
287 | I_u2u1u3(_sra) |
288 | I_u2u1u3(_srl) | |
f31318fd | 289 | I_u3u2u1(_srlv) |
32546f38 | 290 | I_u2u1u3(_rotr) |
e30ec452 TS |
291 | I_u3u1u2(_subu) |
292 | I_u2s3u1(_sw) | |
729ff561 | 293 | I_u1(_sync) |
e30ec452 | 294 | I_0(_tlbp) |
32546f38 | 295 | I_0(_tlbr) |
e30ec452 TS |
296 | I_0(_tlbwi) |
297 | I_0(_tlbwr) | |
53ed1389 | 298 | I_u1(_wait); |
e30ec452 TS |
299 | I_u3u1u2(_xor) |
300 | I_u2u1u3(_xori) | |
d674dd14 | 301 | I_u2u1(_yield) |
92078e06 | 302 | I_u2u1msbu3(_dins); |
c42aef09 | 303 | I_u2u1msb32u3(_dinsm); |
58b9e223 | 304 | I_u1(_syscall); |
5b97c3f7 DD |
305 | I_u1u2s3(_bbit0); |
306 | I_u1u2s3(_bbit1); | |
bb3d68c3 DD |
307 | I_u3u1u2(_lwx) |
308 | I_u3u1u2(_ldx) | |
e30ec452 | 309 | |
c9941158 DD |
310 | #ifdef CONFIG_CPU_CAVIUM_OCTEON |
311 | #include <asm/octeon/octeon.h> | |
078a55fc | 312 | void ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b, |
c9941158 DD |
313 | unsigned int c) |
314 | { | |
315 | if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5) | |
316 | /* | |
317 | * As per erratum Core-14449, replace prefetches 0-4, | |
318 | * 6-24 with 'pref 28'. | |
319 | */ | |
320 | build_insn(buf, insn_pref, c, 28, b); | |
321 | else | |
322 | build_insn(buf, insn_pref, c, a, b); | |
323 | } | |
abc597fe | 324 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_i_pref)); |
c9941158 DD |
325 | #else |
326 | I_u2s3u1(_pref) | |
327 | #endif | |
328 | ||
e30ec452 | 329 | /* Handle labels. */ |
078a55fc | 330 | void ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr, int lid) |
e30ec452 TS |
331 | { |
332 | (*lab)->addr = addr; | |
333 | (*lab)->lab = lid; | |
334 | (*lab)++; | |
335 | } | |
abc597fe | 336 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_build_label)); |
e30ec452 | 337 | |
078a55fc | 338 | int ISAFUNC(uasm_in_compat_space_p)(long addr) |
e30ec452 TS |
339 | { |
340 | /* Is this address in 32bit compat space? */ | |
341 | #ifdef CONFIG_64BIT | |
342 | return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L); | |
343 | #else | |
344 | return 1; | |
345 | #endif | |
346 | } | |
abc597fe | 347 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_in_compat_space_p)); |
e30ec452 | 348 | |
078a55fc | 349 | static int uasm_rel_highest(long val) |
e30ec452 TS |
350 | { |
351 | #ifdef CONFIG_64BIT | |
352 | return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; | |
353 | #else | |
354 | return 0; | |
355 | #endif | |
356 | } | |
357 | ||
078a55fc | 358 | static int uasm_rel_higher(long val) |
e30ec452 TS |
359 | { |
360 | #ifdef CONFIG_64BIT | |
361 | return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; | |
362 | #else | |
363 | return 0; | |
364 | #endif | |
365 | } | |
366 | ||
078a55fc | 367 | int ISAFUNC(uasm_rel_hi)(long val) |
e30ec452 TS |
368 | { |
369 | return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; | |
370 | } | |
abc597fe | 371 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_hi)); |
e30ec452 | 372 | |
078a55fc | 373 | int ISAFUNC(uasm_rel_lo)(long val) |
e30ec452 TS |
374 | { |
375 | return ((val & 0xffff) ^ 0x8000) - 0x8000; | |
376 | } | |
abc597fe | 377 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_lo)); |
e30ec452 | 378 | |
078a55fc | 379 | void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr) |
e30ec452 | 380 | { |
abc597fe SH |
381 | if (!ISAFUNC(uasm_in_compat_space_p)(addr)) { |
382 | ISAFUNC(uasm_i_lui)(buf, rs, uasm_rel_highest(addr)); | |
e30ec452 | 383 | if (uasm_rel_higher(addr)) |
abc597fe SH |
384 | ISAFUNC(uasm_i_daddiu)(buf, rs, rs, uasm_rel_higher(addr)); |
385 | if (ISAFUNC(uasm_rel_hi(addr))) { | |
386 | ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16); | |
387 | ISAFUNC(uasm_i_daddiu)(buf, rs, rs, | |
388 | ISAFUNC(uasm_rel_hi)(addr)); | |
389 | ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16); | |
e30ec452 | 390 | } else |
abc597fe | 391 | ISAFUNC(uasm_i_dsll32)(buf, rs, rs, 0); |
e30ec452 | 392 | } else |
abc597fe | 393 | ISAFUNC(uasm_i_lui)(buf, rs, ISAFUNC(uasm_rel_hi(addr))); |
e30ec452 | 394 | } |
abc597fe | 395 | UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA_mostly)); |
e30ec452 | 396 | |
078a55fc | 397 | void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr) |
e30ec452 | 398 | { |
abc597fe SH |
399 | ISAFUNC(UASM_i_LA_mostly)(buf, rs, addr); |
400 | if (ISAFUNC(uasm_rel_lo(addr))) { | |
401 | if (!ISAFUNC(uasm_in_compat_space_p)(addr)) | |
402 | ISAFUNC(uasm_i_daddiu)(buf, rs, rs, | |
403 | ISAFUNC(uasm_rel_lo(addr))); | |
e30ec452 | 404 | else |
abc597fe SH |
405 | ISAFUNC(uasm_i_addiu)(buf, rs, rs, |
406 | ISAFUNC(uasm_rel_lo(addr))); | |
e30ec452 TS |
407 | } |
408 | } | |
abc597fe | 409 | UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA)); |
e30ec452 TS |
410 | |
411 | /* Handle relocations. */ | |
078a55fc | 412 | void ISAFUNC(uasm_r_mips_pc16)(struct uasm_reloc **rel, u32 *addr, int lid) |
e30ec452 TS |
413 | { |
414 | (*rel)->addr = addr; | |
415 | (*rel)->type = R_MIPS_PC16; | |
416 | (*rel)->lab = lid; | |
417 | (*rel)++; | |
418 | } | |
abc597fe | 419 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_r_mips_pc16)); |
e30ec452 | 420 | |
078a55fc PG |
421 | static inline void __resolve_relocs(struct uasm_reloc *rel, |
422 | struct uasm_label *lab); | |
e30ec452 | 423 | |
078a55fc PG |
424 | void ISAFUNC(uasm_resolve_relocs)(struct uasm_reloc *rel, |
425 | struct uasm_label *lab) | |
e30ec452 TS |
426 | { |
427 | struct uasm_label *l; | |
428 | ||
429 | for (; rel->lab != UASM_LABEL_INVALID; rel++) | |
430 | for (l = lab; l->lab != UASM_LABEL_INVALID; l++) | |
431 | if (rel->lab == l->lab) | |
432 | __resolve_relocs(rel, l); | |
433 | } | |
abc597fe | 434 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_resolve_relocs)); |
e30ec452 | 435 | |
078a55fc PG |
436 | void ISAFUNC(uasm_move_relocs)(struct uasm_reloc *rel, u32 *first, u32 *end, |
437 | long off) | |
e30ec452 TS |
438 | { |
439 | for (; rel->lab != UASM_LABEL_INVALID; rel++) | |
440 | if (rel->addr >= first && rel->addr < end) | |
441 | rel->addr += off; | |
442 | } | |
abc597fe | 443 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_relocs)); |
e30ec452 | 444 | |
078a55fc PG |
445 | void ISAFUNC(uasm_move_labels)(struct uasm_label *lab, u32 *first, u32 *end, |
446 | long off) | |
e30ec452 TS |
447 | { |
448 | for (; lab->lab != UASM_LABEL_INVALID; lab++) | |
449 | if (lab->addr >= first && lab->addr < end) | |
450 | lab->addr += off; | |
451 | } | |
abc597fe | 452 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_labels)); |
e30ec452 | 453 | |
078a55fc PG |
454 | void ISAFUNC(uasm_copy_handler)(struct uasm_reloc *rel, struct uasm_label *lab, |
455 | u32 *first, u32 *end, u32 *target) | |
e30ec452 TS |
456 | { |
457 | long off = (long)(target - first); | |
458 | ||
459 | memcpy(target, first, (end - first) * sizeof(u32)); | |
460 | ||
abc597fe SH |
461 | ISAFUNC(uasm_move_relocs(rel, first, end, off)); |
462 | ISAFUNC(uasm_move_labels(lab, first, end, off)); | |
e30ec452 | 463 | } |
abc597fe | 464 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_copy_handler)); |
e30ec452 | 465 | |
078a55fc | 466 | int ISAFUNC(uasm_insn_has_bdelay)(struct uasm_reloc *rel, u32 *addr) |
e30ec452 TS |
467 | { |
468 | for (; rel->lab != UASM_LABEL_INVALID; rel++) { | |
469 | if (rel->addr == addr | |
470 | && (rel->type == R_MIPS_PC16 | |
471 | || rel->type == R_MIPS_26)) | |
472 | return 1; | |
473 | } | |
474 | ||
475 | return 0; | |
476 | } | |
abc597fe | 477 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_insn_has_bdelay)); |
e30ec452 TS |
478 | |
479 | /* Convenience functions for labeled branches. */ | |
078a55fc PG |
480 | void ISAFUNC(uasm_il_bltz)(u32 **p, struct uasm_reloc **r, unsigned int reg, |
481 | int lid) | |
e30ec452 TS |
482 | { |
483 | uasm_r_mips_pc16(r, *p, lid); | |
abc597fe | 484 | ISAFUNC(uasm_i_bltz)(p, reg, 0); |
e30ec452 | 485 | } |
abc597fe | 486 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bltz)); |
e30ec452 | 487 | |
078a55fc | 488 | void ISAFUNC(uasm_il_b)(u32 **p, struct uasm_reloc **r, int lid) |
e30ec452 TS |
489 | { |
490 | uasm_r_mips_pc16(r, *p, lid); | |
abc597fe | 491 | ISAFUNC(uasm_i_b)(p, 0); |
e30ec452 | 492 | } |
abc597fe | 493 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_b)); |
e30ec452 | 494 | |
8dee5901 PB |
495 | void ISAFUNC(uasm_il_beq)(u32 **p, struct uasm_reloc **r, unsigned int r1, |
496 | unsigned int r2, int lid) | |
497 | { | |
498 | uasm_r_mips_pc16(r, *p, lid); | |
499 | ISAFUNC(uasm_i_beq)(p, r1, r2, 0); | |
500 | } | |
501 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beq)); | |
502 | ||
078a55fc PG |
503 | void ISAFUNC(uasm_il_beqz)(u32 **p, struct uasm_reloc **r, unsigned int reg, |
504 | int lid) | |
e30ec452 TS |
505 | { |
506 | uasm_r_mips_pc16(r, *p, lid); | |
abc597fe | 507 | ISAFUNC(uasm_i_beqz)(p, reg, 0); |
e30ec452 | 508 | } |
abc597fe | 509 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqz)); |
e30ec452 | 510 | |
078a55fc PG |
511 | void ISAFUNC(uasm_il_beqzl)(u32 **p, struct uasm_reloc **r, unsigned int reg, |
512 | int lid) | |
e30ec452 TS |
513 | { |
514 | uasm_r_mips_pc16(r, *p, lid); | |
abc597fe | 515 | ISAFUNC(uasm_i_beqzl)(p, reg, 0); |
e30ec452 | 516 | } |
abc597fe | 517 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqzl)); |
e30ec452 | 518 | |
078a55fc PG |
519 | void ISAFUNC(uasm_il_bne)(u32 **p, struct uasm_reloc **r, unsigned int reg1, |
520 | unsigned int reg2, int lid) | |
fb2a27e7 TS |
521 | { |
522 | uasm_r_mips_pc16(r, *p, lid); | |
abc597fe | 523 | ISAFUNC(uasm_i_bne)(p, reg1, reg2, 0); |
fb2a27e7 | 524 | } |
abc597fe | 525 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bne)); |
fb2a27e7 | 526 | |
078a55fc PG |
527 | void ISAFUNC(uasm_il_bnez)(u32 **p, struct uasm_reloc **r, unsigned int reg, |
528 | int lid) | |
e30ec452 TS |
529 | { |
530 | uasm_r_mips_pc16(r, *p, lid); | |
abc597fe | 531 | ISAFUNC(uasm_i_bnez)(p, reg, 0); |
e30ec452 | 532 | } |
abc597fe | 533 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bnez)); |
e30ec452 | 534 | |
078a55fc PG |
535 | void ISAFUNC(uasm_il_bgezl)(u32 **p, struct uasm_reloc **r, unsigned int reg, |
536 | int lid) | |
e30ec452 TS |
537 | { |
538 | uasm_r_mips_pc16(r, *p, lid); | |
abc597fe | 539 | ISAFUNC(uasm_i_bgezl)(p, reg, 0); |
e30ec452 | 540 | } |
abc597fe | 541 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgezl)); |
e30ec452 | 542 | |
078a55fc PG |
543 | void ISAFUNC(uasm_il_bgez)(u32 **p, struct uasm_reloc **r, unsigned int reg, |
544 | int lid) | |
e30ec452 TS |
545 | { |
546 | uasm_r_mips_pc16(r, *p, lid); | |
abc597fe | 547 | ISAFUNC(uasm_i_bgez)(p, reg, 0); |
e30ec452 | 548 | } |
abc597fe | 549 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgez)); |
5b97c3f7 | 550 | |
078a55fc PG |
551 | void ISAFUNC(uasm_il_bbit0)(u32 **p, struct uasm_reloc **r, unsigned int reg, |
552 | unsigned int bit, int lid) | |
5b97c3f7 DD |
553 | { |
554 | uasm_r_mips_pc16(r, *p, lid); | |
abc597fe | 555 | ISAFUNC(uasm_i_bbit0)(p, reg, bit, 0); |
5b97c3f7 | 556 | } |
abc597fe | 557 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit0)); |
5b97c3f7 | 558 | |
078a55fc PG |
559 | void ISAFUNC(uasm_il_bbit1)(u32 **p, struct uasm_reloc **r, unsigned int reg, |
560 | unsigned int bit, int lid) | |
5b97c3f7 DD |
561 | { |
562 | uasm_r_mips_pc16(r, *p, lid); | |
abc597fe | 563 | ISAFUNC(uasm_i_bbit1)(p, reg, bit, 0); |
5b97c3f7 | 564 | } |
abc597fe | 565 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit1)); |