[deliverable/linux.git] / arch / mips / mm / uasm.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * A small micro-assembler. It is intentionally kept simple, does only
 * support a subset of instructions, and does not try to hide pipeline
 * effects like branch delay slots.
 *
 * Copyright (C) 2004, 2005, 2006, 2008  Thiemo Seufer
 * Copyright (C) 2005, 2007  Maciej W. Rozycki
 * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
 */

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/init.h>

#include <asm/inst.h>
#include <asm/elf.h>
#include <asm/bugs.h>
#include <asm/uasm.h>

enum fields {
	RS = 0x001,
	RT = 0x002,
	RD = 0x004,
	RE = 0x008,
	SIMM = 0x010,
	UIMM = 0x020,
	BIMM = 0x040,
	JIMM = 0x080,
	FUNC = 0x100,
	SET = 0x200
};

#define OP_MASK		0x3f
#define OP_SH		26
#define RS_MASK		0x1f
#define RS_SH		21
#define RT_MASK		0x1f
#define RT_SH		16
#define RD_MASK		0x1f
#define RD_SH		11
#define RE_MASK		0x1f
#define RE_SH		6
#define IMM_MASK	0xffff
#define IMM_SH		0
#define JIMM_MASK	0x3ffffff
#define JIMM_SH		0
#define FUNC_MASK	0x3f
#define FUNC_SH		0
#define SET_MASK	0x7
#define SET_SH		0

enum opcode {
	insn_invalid,
	insn_addu, insn_addiu, insn_and, insn_andi, insn_beq,
	insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
	insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0,
	insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
	insn_dsrl32, insn_drotr, insn_dsubu, insn_eret, insn_j, insn_jal,
	insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0,
	insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd,
	insn_sd, insn_sll, insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw,
	insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori,
	insn_dins
};

struct insn {
	enum opcode opcode;
	u32 match;
	enum fields fields;
};

/* This macro sets the non-variable bits of an instruction. */
#define M(a, b, c, d, e, f)					\
	((a) << OP_SH						\
	 | (b) << RS_SH						\
	 | (c) << RT_SH						\
	 | (d) << RD_SH						\
	 | (e) << RE_SH						\
	 | (f) << FUNC_SH)

static struct insn insn_table[] __cpuinitdata = {
	{ insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
	{ insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
	{ insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
	{ insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
	{ insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
	{ insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
	{ insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
	{ insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM },
	{ insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
	{ insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM },
	{ insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
	{ insn_cache,  M(cache_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
	{ insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
	{ insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
	{ insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
	{ insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
	{ insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
	{ insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
	{ insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
	{ insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
	{ insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
	{ insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
	{ insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
	{ insn_eret,  M(cop0_op, cop_op, 0, 0, 0, eret_op),  0 },
	{ insn_j,  M(j_op, 0, 0, 0, 0, 0),  JIMM },
	{ insn_jal,  M(jal_op, 0, 0, 0, 0, 0),  JIMM },
	{ insn_jr,  M(spec_op, 0, 0, 0, 0, jr_op),  RS },
	{ insn_ld,  M(ld_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
	{ insn_ll,  M(ll_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
	{ insn_lld,  M(lld_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
	{ insn_lui,  M(lui_op, 0, 0, 0, 0, 0),  RT | SIMM },
	{ insn_lw,  M(lw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
	{ insn_mfc0,  M(cop0_op, mfc_op, 0, 0, 0, 0),  RT | RD | SET},
	{ insn_mtc0,  M(cop0_op, mtc_op, 0, 0, 0, 0),  RT | RD | SET},
	{ insn_ori,  M(ori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },
	{ insn_pref,  M(pref_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
	{ insn_rfe,  M(cop0_op, cop_op, 0, 0, 0, rfe_op),  0 },
	{ insn_sc,  M(sc_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
	{ insn_scd,  M(scd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
	{ insn_sd,  M(sd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
	{ insn_sll,  M(spec_op, 0, 0, 0, 0, sll_op),  RT | RD | RE },
	{ insn_sra,  M(spec_op, 0, 0, 0, 0, sra_op),  RT | RD | RE },
	{ insn_srl,  M(spec_op, 0, 0, 0, 0, srl_op),  RT | RD | RE },
	{ insn_rotr,  M(spec_op, 1, 0, 0, 0, srl_op),  RT | RD | RE },
	{ insn_subu,  M(spec_op, 0, 0, 0, 0, subu_op),  RS | RT | RD },
	{ insn_sw,  M(sw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
	{ insn_tlbp,  M(cop0_op, cop_op, 0, 0, 0, tlbp_op),  0 },
	{ insn_tlbr,  M(cop0_op, cop_op, 0, 0, 0, tlbr_op),  0 },
	{ insn_tlbwi,  M(cop0_op, cop_op, 0, 0, 0, tlbwi_op),  0 },
	{ insn_tlbwr,  M(cop0_op, cop_op, 0, 0, 0, tlbwr_op),  0 },
	{ insn_xor,  M(spec_op, 0, 0, 0, 0, xor_op),  RS | RT | RD },
	{ insn_xori,  M(xori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },
	{ insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
	{ insn_invalid, 0, 0 }
};

#undef M

static inline __cpuinit u32 build_rs(u32 arg)
{
	if (arg & ~RS_MASK)
		printk(KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & RS_MASK) << RS_SH;
}

static inline __cpuinit u32 build_rt(u32 arg)
{
	if (arg & ~RT_MASK)
		printk(KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & RT_MASK) << RT_SH;
}

static inline __cpuinit u32 build_rd(u32 arg)
{
	if (arg & ~RD_MASK)
		printk(KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & RD_MASK) << RD_SH;
}

static inline __cpuinit u32 build_re(u32 arg)
{
	if (arg & ~RE_MASK)
		printk(KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & RE_MASK) << RE_SH;
}

static inline __cpuinit u32 build_simm(s32 arg)
{
	if (arg > 0x7fff || arg < -0x8000)
		printk(KERN_WARNING "Micro-assembler field overflow\n");

	return arg & 0xffff;
}

static inline __cpuinit u32 build_uimm(u32 arg)
{
	if (arg & ~IMM_MASK)
		printk(KERN_WARNING "Micro-assembler field overflow\n");

	return arg & IMM_MASK;
}

static inline __cpuinit u32 build_bimm(s32 arg)
{
	if (arg > 0x1ffff || arg < -0x20000)
		printk(KERN_WARNING "Micro-assembler field overflow\n");

	if (arg & 0x3)
		printk(KERN_WARNING "Invalid micro-assembler branch target\n");

	return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
}

static inline __cpuinit u32 build_jimm(u32 arg)
{
	if (arg & ~((JIMM_MASK) << 2))
		printk(KERN_WARNING "Micro-assembler field overflow\n");

	return (arg >> 2) & JIMM_MASK;
}

static inline __cpuinit u32 build_func(u32 arg)
{
	if (arg & ~FUNC_MASK)
		printk(KERN_WARNING "Micro-assembler field overflow\n");

	return arg & FUNC_MASK;
}

static inline __cpuinit u32 build_set(u32 arg)
{
	if (arg & ~SET_MASK)
		printk(KERN_WARNING "Micro-assembler field overflow\n");

	return arg & SET_MASK;
}

/*
 * The order of opcode arguments is implicitly left to right,
 * starting with RS and ending with FUNC or IMM.
 */
static void __cpuinit build_insn(u32 **buf, enum opcode opc, ...)
{
	struct insn *ip = NULL;
	unsigned int i;
	va_list ap;
	u32 op;

	for (i = 0; insn_table[i].opcode != insn_invalid; i++)
		if (insn_table[i].opcode == opc) {
			ip = &insn_table[i];
			break;
		}

	if (!ip || (opc == insn_daddiu && r4k_daddiu_bug()))
		panic("Unsupported Micro-assembler instruction %d", opc);

	op = ip->match;
	va_start(ap, opc);
	if (ip->fields & RS)
		op |= build_rs(va_arg(ap, u32));
	if (ip->fields & RT)
		op |= build_rt(va_arg(ap, u32));
	if (ip->fields & RD)
		op |= build_rd(va_arg(ap, u32));
	if (ip->fields & RE)
		op |= build_re(va_arg(ap, u32));
	if (ip->fields & SIMM)
		op |= build_simm(va_arg(ap, s32));
	if (ip->fields & UIMM)
		op |= build_uimm(va_arg(ap, u32));
	if (ip->fields & BIMM)
		op |= build_bimm(va_arg(ap, s32));
	if (ip->fields & JIMM)
		op |= build_jimm(va_arg(ap, u32));
	if (ip->fields & FUNC)
		op |= build_func(va_arg(ap, u32));
	if (ip->fields & SET)
		op |= build_set(va_arg(ap, u32));
	va_end(ap);

	**buf = op;
	(*buf)++;
}

#define I_u1u2u3(op)					\
Ip_u1u2u3(op)						\
{							\
	build_insn(buf, insn##op, a, b, c);		\
}

#define I_u2u1u3(op)					\
Ip_u2u1u3(op)						\
{							\
	build_insn(buf, insn##op, b, a, c);		\
}

#define I_u3u1u2(op)					\
Ip_u3u1u2(op)						\
{							\
	build_insn(buf, insn##op, b, c, a);		\
}

#define I_u1u2s3(op)					\
Ip_u1u2s3(op)						\
{							\
	build_insn(buf, insn##op, a, b, c);		\
}

#define I_u2s3u1(op)					\
Ip_u2s3u1(op)						\
{							\
	build_insn(buf, insn##op, c, a, b);		\
}

#define I_u2u1s3(op)					\
Ip_u2u1s3(op)						\
{							\
	build_insn(buf, insn##op, b, a, c);		\
}

#define I_u2u1msbu3(op)					\
Ip_u2u1msbu3(op)					\
{							\
	build_insn(buf, insn##op, b, a, c+d-1, c);	\
}

#define I_u1u2(op)					\
Ip_u1u2(op)						\
{							\
	build_insn(buf, insn##op, a, b);		\
}

#define I_u1s2(op)					\
Ip_u1s2(op)						\
{							\
	build_insn(buf, insn##op, a, b);		\
}

#define I_u1(op)					\
Ip_u1(op)						\
{							\
	build_insn(buf, insn##op, a);			\
}

#define I_0(op)						\
Ip_0(op)						\
{							\
	build_insn(buf, insn##op);			\
}

I_u2u1s3(_addiu)
I_u3u1u2(_addu)
I_u2u1u3(_andi)
I_u3u1u2(_and)
I_u1u2s3(_beq)
I_u1u2s3(_beql)
I_u1s2(_bgez)
I_u1s2(_bgezl)
I_u1s2(_bltz)
I_u1s2(_bltzl)
I_u1u2s3(_bne)
I_u2s3u1(_cache)
I_u1u2u3(_dmfc0)
I_u1u2u3(_dmtc0)
I_u2u1s3(_daddiu)
I_u3u1u2(_daddu)
I_u2u1u3(_dsll)
I_u2u1u3(_dsll32)
I_u2u1u3(_dsra)
I_u2u1u3(_dsrl)
I_u2u1u3(_dsrl32)
I_u2u1u3(_drotr)
I_u3u1u2(_dsubu)
I_0(_eret)
I_u1(_j)
I_u1(_jal)
I_u1(_jr)
I_u2s3u1(_ld)
I_u2s3u1(_ll)
I_u2s3u1(_lld)
I_u1s2(_lui)
I_u2s3u1(_lw)
I_u1u2u3(_mfc0)
I_u1u2u3(_mtc0)
I_u2u1u3(_ori)
I_u2s3u1(_pref)
I_0(_rfe)
I_u2s3u1(_sc)
I_u2s3u1(_scd)
I_u2s3u1(_sd)
I_u2u1u3(_sll)
I_u2u1u3(_sra)
I_u2u1u3(_srl)
I_u2u1u3(_rotr)
I_u3u1u2(_subu)
I_u2s3u1(_sw)
I_0(_tlbp)
I_0(_tlbr)
I_0(_tlbwi)
I_0(_tlbwr)
I_u3u1u2(_xor)
I_u2u1u3(_xori)
I_u2u1msbu3(_dins);

/* Handle labels. */
void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
{
	(*lab)->addr = addr;
	(*lab)->lab = lid;
	(*lab)++;
}

int __cpuinit uasm_in_compat_space_p(long addr)
{
	/* Is this address in 32bit compat space? */
#ifdef CONFIG_64BIT
	return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
#else
	return 1;
#endif
}

static int __cpuinit uasm_rel_highest(long val)
{
#ifdef CONFIG_64BIT
	return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
#else
	return 0;
#endif
}

static int __cpuinit uasm_rel_higher(long val)
{
#ifdef CONFIG_64BIT
	return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
#else
	return 0;
#endif
}

int __cpuinit uasm_rel_hi(long val)
{
	return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
}

int __cpuinit uasm_rel_lo(long val)
{
	return ((val & 0xffff) ^ 0x8000) - 0x8000;
}

void __cpuinit UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
{
	if (!uasm_in_compat_space_p(addr)) {
		uasm_i_lui(buf, rs, uasm_rel_highest(addr));
		if (uasm_rel_higher(addr))
			uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(addr));
		if (uasm_rel_hi(addr)) {
			uasm_i_dsll(buf, rs, rs, 16);
			uasm_i_daddiu(buf, rs, rs, uasm_rel_hi(addr));
			uasm_i_dsll(buf, rs, rs, 16);
		} else
			uasm_i_dsll32(buf, rs, rs, 0);
	} else
		uasm_i_lui(buf, rs, uasm_rel_hi(addr));
}

void __cpuinit UASM_i_LA(u32 **buf, unsigned int rs, long addr)
{
	UASM_i_LA_mostly(buf, rs, addr);
	if (uasm_rel_lo(addr)) {
		if (!uasm_in_compat_space_p(addr))
			uasm_i_daddiu(buf, rs, rs, uasm_rel_lo(addr));
		else
			uasm_i_addiu(buf, rs, rs, uasm_rel_lo(addr));
	}
}

/* Handle relocations. */
void __cpuinit
uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid)
{
	(*rel)->addr = addr;
	(*rel)->type = R_MIPS_PC16;
	(*rel)->lab = lid;
	(*rel)++;
}

static inline void __cpuinit
__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
{
	long laddr = (long)lab->addr;
	long raddr = (long)rel->addr;

	switch (rel->type) {
	case R_MIPS_PC16:
		*rel->addr |= build_bimm(laddr - (raddr + 4));
		break;

	default:
		panic("Unsupported Micro-assembler relocation %d",
		      rel->type);
	}
}

void __cpuinit
uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
{
	struct uasm_label *l;

	for (; rel->lab != UASM_LABEL_INVALID; rel++)
		for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
			if (rel->lab == l->lab)
				__resolve_relocs(rel, l);
}

void __cpuinit
uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, long off)
{
	for (; rel->lab != UASM_LABEL_INVALID; rel++)
		if (rel->addr >= first && rel->addr < end)
			rel->addr += off;
}

void __cpuinit
uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, long off)
{
	for (; lab->lab != UASM_LABEL_INVALID; lab++)
		if (lab->addr >= first && lab->addr < end)
			lab->addr += off;
}

void __cpuinit
uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, u32 *first,
		  u32 *end, u32 *target)
{
	long off = (long)(target - first);

	memcpy(target, first, (end - first) * sizeof(u32));

	uasm_move_relocs(rel, first, end, off);
	uasm_move_labels(lab, first, end, off);
}

int __cpuinit uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr)
{
	for (; rel->lab != UASM_LABEL_INVALID; rel++) {
		if (rel->addr == addr
		    && (rel->type == R_MIPS_PC16
			|| rel->type == R_MIPS_26))
			return 1;
	}

	return 0;
}

/* Convenience functions for labeled branches. */
void __cpuinit
uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	uasm_i_bltz(p, reg, 0);
}

void __cpuinit
uasm_il_b(u32 **p, struct uasm_reloc **r, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	uasm_i_b(p, 0);
}

void __cpuinit
uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	uasm_i_beqz(p, reg, 0);
}

void __cpuinit
uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	uasm_i_beqzl(p, reg, 0);
}

void __cpuinit
uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
	unsigned int reg2, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	uasm_i_bne(p, reg1, reg2, 0);
}

void __cpuinit
uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	uasm_i_bnez(p, reg, 0);
}

void __cpuinit
uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	uasm_i_bgezl(p, reg, 0);
}

void __cpuinit
uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	uasm_i_bgez(p, reg, 0);
}
Commit	Line	Data
e30ec452 TS	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* A small micro-assembler. It is intentionally kept simple, does only
	7	* support a subset of instructions, and does not try to hide pipeline
	8	* effects like branch delay slots.
	9	*
	10	* Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
	11	* Copyright (C) 2005, 2007 Maciej W. Rozycki
	12	* Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
	13	*/
	14
	15	#include <linux/kernel.h>
	16	#include <linux/types.h>
	17	#include <linux/init.h>
	18
	19	#include <asm/inst.h>
	20	#include <asm/elf.h>
	21	#include <asm/bugs.h>
3482d713	22	#include <asm/uasm.h>
e30ec452 TS	23
	24	enum fields {
	25	RS = 0x001,
	26	RT = 0x002,
	27	RD = 0x004,
	28	RE = 0x008,
	29	SIMM = 0x010,
	30	UIMM = 0x020,
	31	BIMM = 0x040,
	32	JIMM = 0x080,
	33	FUNC = 0x100,
	34	SET = 0x200
	35	};
	36
	37	#define OP_MASK 0x3f
	38	#define OP_SH 26
	39	#define RS_MASK 0x1f
	40	#define RS_SH 21
	41	#define RT_MASK 0x1f
	42	#define RT_SH 16
	43	#define RD_MASK 0x1f
	44	#define RD_SH 11
	45	#define RE_MASK 0x1f
	46	#define RE_SH 6
	47	#define IMM_MASK 0xffff
	48	#define IMM_SH 0
	49	#define JIMM_MASK 0x3ffffff
	50	#define JIMM_SH 0
	51	#define FUNC_MASK 0x3f
	52	#define FUNC_SH 0
	53	#define SET_MASK 0x7
	54	#define SET_SH 0
	55
	56	enum opcode {
	57	insn_invalid,
	58	insn_addu, insn_addiu, insn_and, insn_andi, insn_beq,
	59	insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
fb2a27e7 TS	60	insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0,
fb2a27e7 TS	61	insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
92078e06 DD	62	insn_dsrl32, insn_drotr, insn_dsubu, insn_eret, insn_j, insn_jal,
92078e06 DD	63	insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0,
fb2a27e7	64	insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd,
32546f38 DD	65	insn_sd, insn_sll, insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw,
	66	insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori,
	67	insn_dins
e30ec452 TS	68	};
	69
	70	struct insn {
	71	enum opcode opcode;
	72	u32 match;
	73	enum fields fields;
	74	};
	75
	76	/* This macro sets the non-variable bits of an instruction. */
	77	#define M(a, b, c, d, e, f) \
	78	((a) << OP_SH \
	79	\| (b) << RS_SH \
	80	\| (c) << RT_SH \
	81	\| (d) << RD_SH \
	82	\| (e) << RE_SH \
	83	\| (f) << FUNC_SH)
	84
234fcd14	85	static struct insn insn_table[] __cpuinitdata = {
e30ec452 TS	86	{ insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM },
	87	{ insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS \| RT \| RD },
	88	{ insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS \| RT \| RD },
	89	{ insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS \| RT \| UIMM },
	90	{ insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS \| RT \| BIMM },
	91	{ insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS \| RT \| BIMM },
	92	{ insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS \| BIMM },
	93	{ insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS \| BIMM },
	94	{ insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS \| BIMM },
	95	{ insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS \| BIMM },
	96	{ insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS \| RT \| BIMM },
fb2a27e7	97	{ insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM },
e30ec452 TS	98	{ insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM },
	99	{ insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS \| RT \| RD },
	100	{ insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT \| RD \| SET},
	101	{ insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT \| RD \| SET},
	102	{ insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT \| RD \| RE },
	103	{ insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT \| RD \| RE },
	104	{ insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT \| RD \| RE },
	105	{ insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT \| RD \| RE },
	106	{ insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT \| RD \| RE },
92078e06	107	{ insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT \| RD \| RE },
e30ec452 TS	108	{ insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS \| RT \| RD },
	109	{ insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 },
	110	{ insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
	111	{ insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM },
	112	{ insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS },
	113	{ insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM },
	114	{ insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM },
	115	{ insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM },
	116	{ insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT \| SIMM },
	117	{ insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM },
	118	{ insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT \| RD \| SET},
	119	{ insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT \| RD \| SET},
	120	{ insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS \| RT \| UIMM },
fb2a27e7	121	{ insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM },
e30ec452 TS	122	{ insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 },
	123	{ insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM },
	124	{ insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM },
	125	{ insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM },
	126	{ insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT \| RD \| RE },
	127	{ insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT \| RD \| RE },
	128	{ insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT \| RD \| RE },
32546f38	129	{ insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT \| RD \| RE },
e30ec452 TS	130	{ insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS \| RT \| RD },
	131	{ insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM },
	132	{ insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 },
32546f38	133	{ insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 },
e30ec452 TS	134	{ insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 },
	135	{ insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 },
	136	{ insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS \| RT \| RD },
	137	{ insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS \| RT \| UIMM },
92078e06	138	{ insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS \| RT \| RD \| RE },
e30ec452 TS	139	{ insn_invalid, 0, 0 }
	140	};
	141
	142	#undef M
	143
234fcd14	144	static inline __cpuinit u32 build_rs(u32 arg)
e30ec452 TS	145	{
	146	if (arg & ~RS_MASK)
	147	printk(KERN_WARNING "Micro-assembler field overflow\n");
	148
	149	return (arg & RS_MASK) << RS_SH;
	150	}
	151
234fcd14	152	static inline __cpuinit u32 build_rt(u32 arg)
e30ec452 TS	153	{
	154	if (arg & ~RT_MASK)
	155	printk(KERN_WARNING "Micro-assembler field overflow\n");
	156
	157	return (arg & RT_MASK) << RT_SH;
	158	}
	159
234fcd14	160	static inline __cpuinit u32 build_rd(u32 arg)
e30ec452 TS	161	{
	162	if (arg & ~RD_MASK)
	163	printk(KERN_WARNING "Micro-assembler field overflow\n");
	164
	165	return (arg & RD_MASK) << RD_SH;
	166	}
	167
234fcd14	168	static inline __cpuinit u32 build_re(u32 arg)
e30ec452 TS	169	{
	170	if (arg & ~RE_MASK)
	171	printk(KERN_WARNING "Micro-assembler field overflow\n");
	172
	173	return (arg & RE_MASK) << RE_SH;
	174	}
	175
234fcd14	176	static inline __cpuinit u32 build_simm(s32 arg)
e30ec452 TS	177	{
	178	if (arg > 0x7fff \|\| arg < -0x8000)
	179	printk(KERN_WARNING "Micro-assembler field overflow\n");
	180
	181	return arg & 0xffff;
	182	}
	183
234fcd14	184	static inline __cpuinit u32 build_uimm(u32 arg)
e30ec452 TS	185	{
	186	if (arg & ~IMM_MASK)
	187	printk(KERN_WARNING "Micro-assembler field overflow\n");
	188
	189	return arg & IMM_MASK;
	190	}
	191
234fcd14	192	static inline __cpuinit u32 build_bimm(s32 arg)
e30ec452 TS	193	{
	194	if (arg > 0x1ffff \|\| arg < -0x20000)
	195	printk(KERN_WARNING "Micro-assembler field overflow\n");
	196
	197	if (arg & 0x3)
	198	printk(KERN_WARNING "Invalid micro-assembler branch target\n");
	199
	200	return ((arg < 0) ? (1 << 15) : 0) \| ((arg >> 2) & 0x7fff);
	201	}
	202
234fcd14	203	static inline __cpuinit u32 build_jimm(u32 arg)
e30ec452 TS	204	{
	205	if (arg & ~((JIMM_MASK) << 2))
	206	printk(KERN_WARNING "Micro-assembler field overflow\n");
	207
	208	return (arg >> 2) & JIMM_MASK;
	209	}
	210
234fcd14	211	static inline __cpuinit u32 build_func(u32 arg)
e30ec452 TS	212	{
	213	if (arg & ~FUNC_MASK)
	214	printk(KERN_WARNING "Micro-assembler field overflow\n");
	215
	216	return arg & FUNC_MASK;
	217	}
	218
234fcd14	219	static inline __cpuinit u32 build_set(u32 arg)
e30ec452 TS	220	{
	221	if (arg & ~SET_MASK)
	222	printk(KERN_WARNING "Micro-assembler field overflow\n");
	223
	224	return arg & SET_MASK;
	225	}
	226
	227	/*
	228	* The order of opcode arguments is implicitly left to right,
	229	* starting with RS and ending with FUNC or IMM.
	230	*/
234fcd14	231	static void __cpuinit build_insn(u32 **buf, enum opcode opc, ...)
e30ec452 TS	232	{
	233	struct insn *ip = NULL;
	234	unsigned int i;
	235	va_list ap;
	236	u32 op;
	237
	238	for (i = 0; insn_table[i].opcode != insn_invalid; i++)
	239	if (insn_table[i].opcode == opc) {
	240	ip = &insn_table[i];
	241	break;
	242	}
	243
	244	if (!ip \|\| (opc == insn_daddiu && r4k_daddiu_bug()))
	245	panic("Unsupported Micro-assembler instruction %d", opc);
	246
	247	op = ip->match;
	248	va_start(ap, opc);
	249	if (ip->fields & RS)
	250	op \|= build_rs(va_arg(ap, u32));
	251	if (ip->fields & RT)
	252	op \|= build_rt(va_arg(ap, u32));
	253	if (ip->fields & RD)
	254	op \|= build_rd(va_arg(ap, u32));
	255	if (ip->fields & RE)
	256	op \|= build_re(va_arg(ap, u32));
	257	if (ip->fields & SIMM)
	258	op \|= build_simm(va_arg(ap, s32));
	259	if (ip->fields & UIMM)
	260	op \|= build_uimm(va_arg(ap, u32));
	261	if (ip->fields & BIMM)
	262	op \|= build_bimm(va_arg(ap, s32));
	263	if (ip->fields & JIMM)
	264	op \|= build_jimm(va_arg(ap, u32));
	265	if (ip->fields & FUNC)
	266	op \|= build_func(va_arg(ap, u32));
	267	if (ip->fields & SET)
	268	op \|= build_set(va_arg(ap, u32));
	269	va_end(ap);
	270
	271	**buf = op;
	272	(*buf)++;
	273	}
	274
	275	#define I_u1u2u3(op) \
	276	Ip_u1u2u3(op) \
	277	{ \
	278	build_insn(buf, insn##op, a, b, c); \
	279	}
	280
	281	#define I_u2u1u3(op) \
	282	Ip_u2u1u3(op) \
	283	{ \
	284	build_insn(buf, insn##op, b, a, c); \
	285	}
	286
	287	#define I_u3u1u2(op) \
	288	Ip_u3u1u2(op) \
	289	{ \
	290	build_insn(buf, insn##op, b, c, a); \
	291	}
	292
	293	#define I_u1u2s3(op) \
	294	Ip_u1u2s3(op) \
	295	{ \
296	build_insn(buf, insn##op, a, b, c); \
297	}
298
299	#define I_u2s3u1(op) \
300	Ip_u2s3u1(op) \
301	{ \
302	build_insn(buf, insn##op, c, a, b); \
303	}
304
305	#define I_u2u1s3(op) \
306	Ip_u2u1s3(op) \
307	{ \
308	build_insn(buf, insn##op, b, a, c); \
309	}
310
92078e06 DD	311	#define I_u2u1msbu3(op) \
	312	Ip_u2u1msbu3(op) \
	313	{ \
	314	build_insn(buf, insn##op, b, a, c+d-1, c); \
	315	}
	316
e30ec452 TS	317	#define I_u1u2(op) \
	318	Ip_u1u2(op) \
	319	{ \
	320	build_insn(buf, insn##op, a, b); \
	321	}
	322
	323	#define I_u1s2(op) \
	324	Ip_u1s2(op) \
	325	{ \
	326	build_insn(buf, insn##op, a, b); \
	327	}
	328
	329	#define I_u1(op) \
	330	Ip_u1(op) \
	331	{ \
	332	build_insn(buf, insn##op, a); \
	333	}
	334
	335	#define I_0(op) \
	336	Ip_0(op) \
	337	{ \
	338	build_insn(buf, insn##op); \
	339	}
	340
	341	I_u2u1s3(_addiu)
	342	I_u3u1u2(_addu)
	343	I_u2u1u3(_andi)
	344	I_u3u1u2(_and)
	345	I_u1u2s3(_beq)
	346	I_u1u2s3(_beql)
	347	I_u1s2(_bgez)
	348	I_u1s2(_bgezl)
	349	I_u1s2(_bltz)
	350	I_u1s2(_bltzl)
	351	I_u1u2s3(_bne)
fb2a27e7	352	I_u2s3u1(_cache)
e30ec452 TS	353	I_u1u2u3(_dmfc0)
	354	I_u1u2u3(_dmtc0)
	355	I_u2u1s3(_daddiu)
	356	I_u3u1u2(_daddu)
	357	I_u2u1u3(_dsll)
	358	I_u2u1u3(_dsll32)
	359	I_u2u1u3(_dsra)
	360	I_u2u1u3(_dsrl)
	361	I_u2u1u3(_dsrl32)
92078e06	362	I_u2u1u3(_drotr)
e30ec452 TS	363	I_u3u1u2(_dsubu)
	364	I_0(_eret)
	365	I_u1(_j)
	366	I_u1(_jal)
	367	I_u1(_jr)
	368	I_u2s3u1(_ld)
	369	I_u2s3u1(_ll)
	370	I_u2s3u1(_lld)
	371	I_u1s2(_lui)
	372	I_u2s3u1(_lw)
	373	I_u1u2u3(_mfc0)
	374	I_u1u2u3(_mtc0)
	375	I_u2u1u3(_ori)
fb2a27e7	376	I_u2s3u1(_pref)
e30ec452 TS	377	I_0(_rfe)
	378	I_u2s3u1(_sc)
	379	I_u2s3u1(_scd)
	380	I_u2s3u1(_sd)
	381	I_u2u1u3(_sll)
	382	I_u2u1u3(_sra)
	383	I_u2u1u3(_srl)
32546f38	384	I_u2u1u3(_rotr)
e30ec452 TS	385	I_u3u1u2(_subu)
	386	I_u2s3u1(_sw)
	387	I_0(_tlbp)
32546f38	388	I_0(_tlbr)
e30ec452 TS	389	I_0(_tlbwi)
	390	I_0(_tlbwr)
	391	I_u3u1u2(_xor)
	392	I_u2u1u3(_xori)
92078e06	393	I_u2u1msbu3(_dins);
e30ec452 TS	394
e30ec452 TS	395	/* Handle labels. */
234fcd14	396	void __cpuinit uasm_build_label(struct uasm_label *lab, u32 addr, int lid)
e30ec452 TS	397	{
	398	(*lab)->addr = addr;
	399	(*lab)->lab = lid;
	400	(*lab)++;
	401	}
	402
234fcd14	403	int __cpuinit uasm_in_compat_space_p(long addr)
e30ec452 TS	404	{
	405	/* Is this address in 32bit compat space? */
	406	#ifdef CONFIG_64BIT
	407	return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
	408	#else
	409	return 1;
	410	#endif
	411	}
	412
17f61e61	413	static int __cpuinit uasm_rel_highest(long val)
e30ec452 TS	414	{
	415	#ifdef CONFIG_64BIT
	416	return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
	417	#else
	418	return 0;
	419	#endif
	420	}
	421
17f61e61	422	static int __cpuinit uasm_rel_higher(long val)
e30ec452 TS	423	{
	424	#ifdef CONFIG_64BIT
	425	return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
	426	#else
	427	return 0;
	428	#endif
	429	}
	430
234fcd14	431	int __cpuinit uasm_rel_hi(long val)
e30ec452 TS	432	{
	433	return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
	434	}
	435
234fcd14	436	int __cpuinit uasm_rel_lo(long val)
e30ec452 TS	437	{
	438	return ((val & 0xffff) ^ 0x8000) - 0x8000;
	439	}
	440
234fcd14	441	void __cpuinit UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
e30ec452 TS	442	{
	443	if (!uasm_in_compat_space_p(addr)) {
	444	uasm_i_lui(buf, rs, uasm_rel_highest(addr));
	445	if (uasm_rel_higher(addr))
	446	uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(addr));
	447	if (uasm_rel_hi(addr)) {
	448	uasm_i_dsll(buf, rs, rs, 16);
	449	uasm_i_daddiu(buf, rs, rs, uasm_rel_hi(addr));
	450	uasm_i_dsll(buf, rs, rs, 16);
	451	} else
	452	uasm_i_dsll32(buf, rs, rs, 0);
	453	} else
	454	uasm_i_lui(buf, rs, uasm_rel_hi(addr));
	455	}
	456
234fcd14	457	void __cpuinit UASM_i_LA(u32 **buf, unsigned int rs, long addr)
e30ec452 TS	458	{
	459	UASM_i_LA_mostly(buf, rs, addr);
	460	if (uasm_rel_lo(addr)) {
	461	if (!uasm_in_compat_space_p(addr))
	462	uasm_i_daddiu(buf, rs, rs, uasm_rel_lo(addr));
	463	else
	464	uasm_i_addiu(buf, rs, rs, uasm_rel_lo(addr));
	465	}
	466	}
	467
	468	/* Handle relocations. */
234fcd14	469	void __cpuinit
e30ec452 TS	470	uasm_r_mips_pc16(struct uasm_reloc *rel, u32 addr, int lid)
	471	{
	472	(*rel)->addr = addr;
	473	(*rel)->type = R_MIPS_PC16;
	474	(*rel)->lab = lid;
	475	(*rel)++;
	476	}
	477
234fcd14	478	static inline void __cpuinit
e30ec452 TS	479	__resolve_relocs(struct uasm_reloc rel, struct uasm_label lab)
	480	{
	481	long laddr = (long)lab->addr;
	482	long raddr = (long)rel->addr;
	483
	484	switch (rel->type) {
	485	case R_MIPS_PC16:
	486	*rel->addr \|= build_bimm(laddr - (raddr + 4));
	487	break;
	488
	489	default:
	490	panic("Unsupported Micro-assembler relocation %d",
	491	rel->type);
	492	}
	493	}
	494
234fcd14	495	void __cpuinit
e30ec452 TS	496	uasm_resolve_relocs(struct uasm_reloc rel, struct uasm_label lab)
	497	{
	498	struct uasm_label *l;
	499
	500	for (; rel->lab != UASM_LABEL_INVALID; rel++)
	501	for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
	502	if (rel->lab == l->lab)
	503	__resolve_relocs(rel, l);
	504	}
	505
234fcd14	506	void __cpuinit
e30ec452 TS	507	uasm_move_relocs(struct uasm_reloc rel, u32 first, u32 *end, long off)
	508	{
	509	for (; rel->lab != UASM_LABEL_INVALID; rel++)
	510	if (rel->addr >= first && rel->addr < end)
	511	rel->addr += off;
	512	}
	513
234fcd14	514	void __cpuinit
e30ec452 TS	515	uasm_move_labels(struct uasm_label lab, u32 first, u32 *end, long off)
	516	{
	517	for (; lab->lab != UASM_LABEL_INVALID; lab++)
	518	if (lab->addr >= first && lab->addr < end)
	519	lab->addr += off;
	520	}
	521
234fcd14	522	void __cpuinit
e30ec452 TS	523	uasm_copy_handler(struct uasm_reloc rel, struct uasm_label lab, u32 *first,
	524	u32 end, u32 target)
	525	{
	526	long off = (long)(target - first);
	527
	528	memcpy(target, first, (end - first) * sizeof(u32));
	529
	530	uasm_move_relocs(rel, first, end, off);
	531	uasm_move_labels(lab, first, end, off);
	532	}
	533
234fcd14	534	int __cpuinit uasm_insn_has_bdelay(struct uasm_reloc rel, u32 addr)
e30ec452 TS	535	{
	536	for (; rel->lab != UASM_LABEL_INVALID; rel++) {
	537	if (rel->addr == addr
	538	&& (rel->type == R_MIPS_PC16
	539	\|\| rel->type == R_MIPS_26))
	540	return 1;
	541	}
	542
	543	return 0;
	544	}
	545
	546	/* Convenience functions for labeled branches. */
234fcd14	547	void __cpuinit
e30ec452 TS	548	uasm_il_bltz(u32 p, struct uasm_reloc r, unsigned int reg, int lid)
	549	{
	550	uasm_r_mips_pc16(r, *p, lid);
	551	uasm_i_bltz(p, reg, 0);
	552	}
	553
234fcd14	554	void __cpuinit
e30ec452 TS	555	uasm_il_b(u32 p, struct uasm_reloc r, int lid)
	556	{
	557	uasm_r_mips_pc16(r, *p, lid);
	558	uasm_i_b(p, 0);
	559	}
	560
234fcd14	561	void __cpuinit
e30ec452 TS	562	uasm_il_beqz(u32 p, struct uasm_reloc r, unsigned int reg, int lid)
	563	{
	564	uasm_r_mips_pc16(r, *p, lid);
	565	uasm_i_beqz(p, reg, 0);
	566	}
	567
234fcd14	568	void __cpuinit
e30ec452 TS	569	uasm_il_beqzl(u32 p, struct uasm_reloc r, unsigned int reg, int lid)
	570	{
	571	uasm_r_mips_pc16(r, *p, lid);
	572	uasm_i_beqzl(p, reg, 0);
	573	}
	574
fb2a27e7 TS	575	void __cpuinit
	576	uasm_il_bne(u32 p, struct uasm_reloc r, unsigned int reg1,
	577	unsigned int reg2, int lid)
	578	{
	579	uasm_r_mips_pc16(r, *p, lid);
	580	uasm_i_bne(p, reg1, reg2, 0);
	581	}
	582
234fcd14	583	void __cpuinit
e30ec452 TS	584	uasm_il_bnez(u32 p, struct uasm_reloc r, unsigned int reg, int lid)
	585	{
	586	uasm_r_mips_pc16(r, *p, lid);
	587	uasm_i_bnez(p, reg, 0);
	588	}
	589
234fcd14	590	void __cpuinit
e30ec452 TS	591	uasm_il_bgezl(u32 p, struct uasm_reloc r, unsigned int reg, int lid)
	592	{
	593	uasm_r_mips_pc16(r, *p, lid);
	594	uasm_i_bgezl(p, reg, 0);
	595	}
	596
234fcd14	597	void __cpuinit
e30ec452 TS	598	uasm_il_bgez(u32 p, struct uasm_reloc r, unsigned int reg, int lid)
	599	{
	600	uasm_r_mips_pc16(r, *p, lid);
	601	uasm_i_bgez(p, reg, 0);
	602	}