[deliverable/linux.git] / arch / mips / mti-malta / malta-int.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
 * Copyright (C) 2001 Ralf Baechle
 * Copyright (C) 2013 Imagination Technologies Ltd.
 *
 * Routines for generic manipulation of the interrupts found on the MIPS
 * Malta board. The interrupt controller is located in the South Bridge
 * a PIIX4 device with two internal 82C95 interrupt controllers.
 */
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irqchip/mips-gic.h>
#include <linux/kernel_stat.h>
#include <linux/kernel.h>
#include <linux/random.h>

#include <asm/traps.h>
#include <asm/i8259.h>
#include <asm/irq_cpu.h>
#include <asm/irq_regs.h>
#include <asm/mips-cm.h>
#include <asm/mips-boards/malta.h>
#include <asm/mips-boards/maltaint.h>
#include <asm/gt64120.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/msc01_pci.h>
#include <asm/msc01_ic.h>
#include <asm/setup.h>
#include <asm/rtlx.h>

static void __iomem *_msc01_biu_base;

static DEFINE_RAW_SPINLOCK(mips_irq_lock);

static inline int mips_pcibios_iack(void)
{
	int irq;

	/*
	 * Determine highest priority pending interrupt by performing
	 * a PCI Interrupt Acknowledge cycle.
	 */
	switch (mips_revision_sconid) {
	case MIPS_REVISION_SCON_SOCIT:
	case MIPS_REVISION_SCON_ROCIT:
	case MIPS_REVISION_SCON_SOCITSC:
	case MIPS_REVISION_SCON_SOCITSCP:
		MSC_READ(MSC01_PCI_IACK, irq);
		irq &= 0xff;
		break;
	case MIPS_REVISION_SCON_GT64120:
		irq = GT_READ(GT_PCI0_IACK_OFS);
		irq &= 0xff;
		break;
	case MIPS_REVISION_SCON_BONITO:
		/* The following will generate a PCI IACK cycle on the
		 * Bonito controller. It's a little bit kludgy, but it
		 * was the easiest way to implement it in hardware at
		 * the given time.
		 */
		BONITO_PCIMAP_CFG = 0x20000;

		/* Flush Bonito register block */
		(void) BONITO_PCIMAP_CFG;
		iob();	  /* sync */

		irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg);
		iob();	  /* sync */
		irq &= 0xff;
		BONITO_PCIMAP_CFG = 0;
		break;
	default:
		pr_emerg("Unknown system controller.\n");
		return -1;
	}
	return irq;
}

static inline int get_int(void)
{
	unsigned long flags;
	int irq;
	raw_spin_lock_irqsave(&mips_irq_lock, flags);

	irq = mips_pcibios_iack();

	/*
	 * The only way we can decide if an interrupt is spurious
	 * is by checking the 8259 registers.  This needs a spinlock
	 * on an SMP system,  so leave it up to the generic code...
	 */

	raw_spin_unlock_irqrestore(&mips_irq_lock, flags);

	return irq;
}

static void malta_hw0_irqdispatch(void)
{
	int irq;

	irq = get_int();
	if (irq < 0) {
		/* interrupt has already been cleared */
		return;
	}

	do_IRQ(MALTA_INT_BASE + irq);

#ifdef CONFIG_MIPS_VPE_APSP_API_MT
	if (aprp_hook)
		aprp_hook();
#endif
}

static irqreturn_t i8259_handler(int irq, void *dev_id)
{
	malta_hw0_irqdispatch();
	return IRQ_HANDLED;
}

static void corehi_irqdispatch(void)
{
	unsigned int intedge, intsteer, pcicmd, pcibadaddr;
	unsigned int pcimstat, intisr, inten, intpol;
	unsigned int intrcause, datalo, datahi;
	struct pt_regs *regs = get_irq_regs();

	pr_emerg("CoreHI interrupt, shouldn't happen, we die here!\n");
	pr_emerg("epc	 : %08lx\nStatus: %08lx\n"
		 "Cause : %08lx\nbadVaddr : %08lx\n",
		 regs->cp0_epc, regs->cp0_status,
		 regs->cp0_cause, regs->cp0_badvaddr);

	/* Read all the registers and then print them as there is a
	   problem with interspersed printk's upsetting the Bonito controller.
	   Do it for the others too.
	*/

	switch (mips_revision_sconid) {
	case MIPS_REVISION_SCON_SOCIT:
	case MIPS_REVISION_SCON_ROCIT:
	case MIPS_REVISION_SCON_SOCITSC:
	case MIPS_REVISION_SCON_SOCITSCP:
		ll_msc_irq();
		break;
	case MIPS_REVISION_SCON_GT64120:
		intrcause = GT_READ(GT_INTRCAUSE_OFS);
		datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
		datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
		pr_emerg("GT_INTRCAUSE = %08x\n", intrcause);
		pr_emerg("GT_CPUERR_ADDR = %02x%08x\n",
				datahi, datalo);
		break;
	case MIPS_REVISION_SCON_BONITO:
		pcibadaddr = BONITO_PCIBADADDR;
		pcimstat = BONITO_PCIMSTAT;
		intisr = BONITO_INTISR;
		inten = BONITO_INTEN;
		intpol = BONITO_INTPOL;
		intedge = BONITO_INTEDGE;
		intsteer = BONITO_INTSTEER;
		pcicmd = BONITO_PCICMD;
		pr_emerg("BONITO_INTISR = %08x\n", intisr);
		pr_emerg("BONITO_INTEN = %08x\n", inten);
		pr_emerg("BONITO_INTPOL = %08x\n", intpol);
		pr_emerg("BONITO_INTEDGE = %08x\n", intedge);
		pr_emerg("BONITO_INTSTEER = %08x\n", intsteer);
		pr_emerg("BONITO_PCICMD = %08x\n", pcicmd);
		pr_emerg("BONITO_PCIBADADDR = %08x\n", pcibadaddr);
		pr_emerg("BONITO_PCIMSTAT = %08x\n", pcimstat);
		break;
	}

	die("CoreHi interrupt", regs);
}

static irqreturn_t corehi_handler(int irq, void *dev_id)
{
	corehi_irqdispatch();
	return IRQ_HANDLED;
}

#ifdef CONFIG_MIPS_MT_SMP

#define MIPS_CPU_IPI_RESCHED_IRQ 0	/* SW int 0 for resched */
#define C_RESCHED C_SW0
#define MIPS_CPU_IPI_CALL_IRQ 1		/* SW int 1 for resched */
#define C_CALL C_SW1
static int cpu_ipi_resched_irq, cpu_ipi_call_irq;

static void ipi_resched_dispatch(void)
{
	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
}

static void ipi_call_dispatch(void)
{
	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
}

static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
{
#ifdef CONFIG_MIPS_VPE_APSP_API_CMP
	if (aprp_hook)
		aprp_hook();
#endif

	scheduler_ipi();

	return IRQ_HANDLED;
}

static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
{
	generic_smp_call_function_interrupt();

	return IRQ_HANDLED;
}

static struct irqaction irq_resched = {
	.handler	= ipi_resched_interrupt,
	.flags		= IRQF_PERCPU,
	.name		= "IPI_resched"
};

static struct irqaction irq_call = {
	.handler	= ipi_call_interrupt,
	.flags		= IRQF_PERCPU,
	.name		= "IPI_call"
};
#endif /* CONFIG_MIPS_MT_SMP */

static struct irqaction i8259irq = {
	.handler = i8259_handler,
	.name = "XT-PIC cascade",
	.flags = IRQF_NO_THREAD,
};

static struct irqaction corehi_irqaction = {
	.handler = corehi_handler,
	.name = "CoreHi",
	.flags = IRQF_NO_THREAD,
};

static msc_irqmap_t msc_irqmap[] __initdata = {
	{MSC01C_INT_TMR,		MSC01_IRQ_EDGE, 0},
	{MSC01C_INT_PCI,		MSC01_IRQ_LEVEL, 0},
};
static int msc_nr_irqs __initdata = ARRAY_SIZE(msc_irqmap);

static msc_irqmap_t msc_eicirqmap[] __initdata = {
	{MSC01E_INT_SW0,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_SW1,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_I8259A,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_SMI,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_COREHI,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_CORELO,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_TMR,		MSC01_IRQ_EDGE, 0},
	{MSC01E_INT_PCI,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_PERFCTR,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_CPUCTR,		MSC01_IRQ_LEVEL, 0}
};

static int msc_nr_eicirqs __initdata = ARRAY_SIZE(msc_eicirqmap);

void __init arch_init_ipiirq(int irq, struct irqaction *action)
{
	setup_irq(irq, action);
	irq_set_handler(irq, handle_percpu_irq);
}

void __init arch_init_irq(void)
{
	int corehi_irq, i8259_irq;

	init_i8259_irqs();

	if (!cpu_has_veic)
		mips_cpu_irq_init();

	if (mips_cm_present()) {
		write_gcr_gic_base(GIC_BASE_ADDR | CM_GCR_GIC_BASE_GICEN_MSK);
		gic_present = 1;
	} else {
		if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) {
			_msc01_biu_base = ioremap_nocache(MSC01_BIU_REG_BASE,
						MSC01_BIU_ADDRSPACE_SZ);
			gic_present =
			  (__raw_readl(_msc01_biu_base + MSC01_SC_CFG_OFS) &
			   MSC01_SC_CFG_GICPRES_MSK) >>
			  MSC01_SC_CFG_GICPRES_SHF;
		}
	}
	if (gic_present)
		pr_debug("GIC present\n");

	switch (mips_revision_sconid) {
	case MIPS_REVISION_SCON_SOCIT:
	case MIPS_REVISION_SCON_ROCIT:
		if (cpu_has_veic)
			init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
					MSC01E_INT_BASE, msc_eicirqmap,
					msc_nr_eicirqs);
		else
			init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
					MSC01C_INT_BASE, msc_irqmap,
					msc_nr_irqs);
		break;

	case MIPS_REVISION_SCON_SOCITSC:
	case MIPS_REVISION_SCON_SOCITSCP:
		if (cpu_has_veic)
			init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
					MSC01E_INT_BASE, msc_eicirqmap,
					msc_nr_eicirqs);
		else
			init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
					MSC01C_INT_BASE, msc_irqmap,
					msc_nr_irqs);
	}

	if (gic_present) {
		int i;

		gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, MIPSCPU_INT_GIC,
			 MIPS_GIC_IRQ_BASE);
		if (!mips_cm_present()) {
			/* Enable the GIC */
			i = __raw_readl(_msc01_biu_base + MSC01_SC_CFG_OFS);
			__raw_writel(i | (0x1 << MSC01_SC_CFG_GICENA_SHF),
				 _msc01_biu_base + MSC01_SC_CFG_OFS);
			pr_debug("GIC Enabled\n");
		}
		i8259_irq = MIPS_GIC_IRQ_BASE + GIC_INT_I8259A;
		corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
	} else {
#if defined(CONFIG_MIPS_MT_SMP)
		/* set up ipi interrupts */
		if (cpu_has_veic) {
			set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch);
			set_vi_handler (MSC01E_INT_SW1, ipi_call_dispatch);
			cpu_ipi_resched_irq = MSC01E_INT_SW0;
			cpu_ipi_call_irq = MSC01E_INT_SW1;
		} else {
			cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE +
				MIPS_CPU_IPI_RESCHED_IRQ;
			cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE +
				MIPS_CPU_IPI_CALL_IRQ;
		}
		arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched);
		arch_init_ipiirq(cpu_ipi_call_irq, &irq_call);
#endif
		if (cpu_has_veic) {
			set_vi_handler(MSC01E_INT_I8259A,
				       malta_hw0_irqdispatch);
			set_vi_handler(MSC01E_INT_COREHI,
				       corehi_irqdispatch);
			i8259_irq = MSC01E_INT_BASE + MSC01E_INT_I8259A;
			corehi_irq = MSC01E_INT_BASE + MSC01E_INT_COREHI;
		} else {
			i8259_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_I8259A;
			corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
		}
	}

	setup_irq(i8259_irq, &i8259irq);
	setup_irq(corehi_irq, &corehi_irqaction);
}

void malta_be_init(void)
{
	/* Could change CM error mask register. */
}

int malta_be_handler(struct pt_regs *regs, int is_fixup)
{
	/* This duplicates the handling in do_be which seems wrong */
	int retval = is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL;

	mips_cm_error_report();

	return retval;
}
Commit	Line	Data
1da177e4	1	/*
5792bf64 SH	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
1da177e4 LT	6	* Carsten Langgaard, carstenl@mips.com
	7	* Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
	8	* Copyright (C) 2001 Ralf Baechle
1336113a	9	* Copyright (C) 2013 Imagination Technologies Ltd.
1da177e4	10	*
1da177e4	11	* Routines for generic manipulation of the interrupts found on the MIPS
5792bf64 SH	12	* Malta board. The interrupt controller is located in the South Bridge
5792bf64 SH	13	* a PIIX4 device with two internal 82C95 interrupt controllers.
1da177e4 LT	14	*/
	15	#include <linux/init.h>
	16	#include <linux/irq.h>
	17	#include <linux/sched.h>
631330f5	18	#include <linux/smp.h>
1da177e4	19	#include <linux/interrupt.h>
54bf038e	20	#include <linux/io.h>
4060bbe9	21	#include <linux/irqchip/mips-gic.h>
1da177e4	22	#include <linux/kernel_stat.h>
25b8ac3b	23	#include <linux/kernel.h>
1da177e4 LT	24	#include <linux/random.h>
1da177e4 LT	25
39b8d525	26	#include <asm/traps.h>
1da177e4	27	#include <asm/i8259.h>
e01402b1	28	#include <asm/irq_cpu.h>
ba38cdf9	29	#include <asm/irq_regs.h>
237036de	30	#include <asm/mips-cm.h>
1da177e4 LT	31	#include <asm/mips-boards/malta.h>
1da177e4 LT	32	#include <asm/mips-boards/maltaint.h>
1da177e4 LT	33	#include <asm/gt64120.h>
	34	#include <asm/mips-boards/generic.h>
	35	#include <asm/mips-boards/msc01_pci.h>
e01402b1	36	#include <asm/msc01_ic.h>
b81947c6	37	#include <asm/setup.h>
1336113a	38	#include <asm/rtlx.h>
39b8d525	39
609ead04	40	static void __iomem *_msc01_biu_base;
1da177e4	41
a963dc70	42	static DEFINE_RAW_SPINLOCK(mips_irq_lock);
1da177e4 LT	43
	44	static inline int mips_pcibios_iack(void)
	45	{
	46	int irq;
1da177e4 LT	47
	48	/*
	49	* Determine highest priority pending interrupt by performing
	50	* a PCI Interrupt Acknowledge cycle.
	51	*/
b72c0526 CD	52	switch (mips_revision_sconid) {
	53	case MIPS_REVISION_SCON_SOCIT:
	54	case MIPS_REVISION_SCON_ROCIT:
	55	case MIPS_REVISION_SCON_SOCITSC:
	56	case MIPS_REVISION_SCON_SOCITSCP:
af825586	57	MSC_READ(MSC01_PCI_IACK, irq);
1da177e4 LT	58	irq &= 0xff;
1da177e4 LT	59	break;
b72c0526	60	case MIPS_REVISION_SCON_GT64120:
1da177e4 LT	61	irq = GT_READ(GT_PCI0_IACK_OFS);
	62	irq &= 0xff;
	63	break;
b72c0526	64	case MIPS_REVISION_SCON_BONITO:
1da177e4 LT	65	/* The following will generate a PCI IACK cycle on the
	66	* Bonito controller. It's a little bit kludgy, but it
	67	* was the easiest way to implement it in hardware at
	68	* the given time.
	69	*/
	70	BONITO_PCIMAP_CFG = 0x20000;
	71
	72	/* Flush Bonito register block */
6be63bbb	73	(void) BONITO_PCIMAP_CFG;
70342287	74	iob(); /* sync */
1da177e4	75
accfd35a	76	irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg);
70342287	77	iob(); /* sync */
1da177e4 LT	78	irq &= 0xff;
	79	BONITO_PCIMAP_CFG = 0;
	80	break;
	81	default:
5792bf64	82	pr_emerg("Unknown system controller.\n");
1da177e4 LT	83	return -1;
	84	}
	85	return irq;
	86	}
	87
e01402b1	88	static inline int get_int(void)
1da177e4 LT	89	{
1da177e4 LT	90	unsigned long flags;
e01402b1	91	int irq;
a963dc70	92	raw_spin_lock_irqsave(&mips_irq_lock, flags);
1da177e4	93
e01402b1	94	irq = mips_pcibios_iack();
1da177e4 LT	95
1da177e4 LT	96	/*
479a0e3e RB	97	* The only way we can decide if an interrupt is spurious
	98	* is by checking the 8259 registers. This needs a spinlock
	99	* on an SMP system, so leave it up to the generic code...
1da177e4	100	*/
1da177e4	101
a963dc70	102	raw_spin_unlock_irqrestore(&mips_irq_lock, flags);
1da177e4	103
e01402b1	104	return irq;
1da177e4 LT	105	}
1da177e4 LT	106
937a8015	107	static void malta_hw0_irqdispatch(void)
1da177e4 LT	108	{
	109	int irq;
	110
e01402b1	111	irq = get_int();
41c594ab	112	if (irq < 0) {
cd80d548 DV	113	/* interrupt has already been cleared */
cd80d548 DV	114	return;
41c594ab	115	}
1da177e4	116
937a8015	117	do_IRQ(MALTA_INT_BASE + irq);
1336113a	118
9c1f6e00	119	#ifdef CONFIG_MIPS_VPE_APSP_API_MT
1336113a DCZ	120	if (aprp_hook)
	121	aprp_hook();
	122	#endif
1da177e4 LT	123	}
1da177e4 LT	124
18743d27	125	static irqreturn_t i8259_handler(int irq, void *dev_id)
39b8d525	126	{
18743d27 AB	127	malta_hw0_irqdispatch();
18743d27 AB	128	return IRQ_HANDLED;
39b8d525 RB	129	}
39b8d525 RB	130
937a8015	131	static void corehi_irqdispatch(void)
1da177e4	132	{
937a8015	133	unsigned int intedge, intsteer, pcicmd, pcibadaddr;
af825586	134	unsigned int pcimstat, intisr, inten, intpol;
21a151d8	135	unsigned int intrcause, datalo, datahi;
ba38cdf9	136	struct pt_regs *regs = get_irq_regs();
1da177e4	137
5792bf64 SH	138	pr_emerg("CoreHI interrupt, shouldn't happen, we die here!\n");
	139	pr_emerg("epc : %08lx\nStatus: %08lx\n"
	140	"Cause : %08lx\nbadVaddr : %08lx\n",
	141	regs->cp0_epc, regs->cp0_status,
	142	regs->cp0_cause, regs->cp0_badvaddr);
e01402b1 RB	143
	144	/* Read all the registers and then print them as there is a
	145	problem with interspersed printk's upsetting the Bonito controller.
	146	Do it for the others too.
	147	*/
	148
b72c0526	149	switch (mips_revision_sconid) {
af825586	150	case MIPS_REVISION_SCON_SOCIT:
b72c0526 CD	151	case MIPS_REVISION_SCON_ROCIT:
	152	case MIPS_REVISION_SCON_SOCITSC:
	153	case MIPS_REVISION_SCON_SOCITSCP:
af825586 DV	154	ll_msc_irq();
	155	break;
	156	case MIPS_REVISION_SCON_GT64120:
	157	intrcause = GT_READ(GT_INTRCAUSE_OFS);
	158	datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
	159	datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
5792bf64 SH	160	pr_emerg("GT_INTRCAUSE = %08x\n", intrcause);
5792bf64 SH	161	pr_emerg("GT_CPUERR_ADDR = %02x%08x\n",
8216d348	162	datahi, datalo);
af825586 DV	163	break;
	164	case MIPS_REVISION_SCON_BONITO:
	165	pcibadaddr = BONITO_PCIBADADDR;
	166	pcimstat = BONITO_PCIMSTAT;
	167	intisr = BONITO_INTISR;
	168	inten = BONITO_INTEN;
	169	intpol = BONITO_INTPOL;
	170	intedge = BONITO_INTEDGE;
	171	intsteer = BONITO_INTSTEER;
	172	pcicmd = BONITO_PCICMD;
5792bf64 SH	173	pr_emerg("BONITO_INTISR = %08x\n", intisr);
	174	pr_emerg("BONITO_INTEN = %08x\n", inten);
	175	pr_emerg("BONITO_INTPOL = %08x\n", intpol);
	176	pr_emerg("BONITO_INTEDGE = %08x\n", intedge);
	177	pr_emerg("BONITO_INTSTEER = %08x\n", intsteer);
	178	pr_emerg("BONITO_PCICMD = %08x\n", pcicmd);
	179	pr_emerg("BONITO_PCIBADADDR = %08x\n", pcibadaddr);
	180	pr_emerg("BONITO_PCIMSTAT = %08x\n", pcimstat);
af825586 DV	181	break;
af825586 DV	182	}
1da177e4	183
af825586	184	die("CoreHi interrupt", regs);
1da177e4 LT	185	}
1da177e4 LT	186
18743d27 AB	187	static irqreturn_t corehi_handler(int irq, void *dev_id)
	188	{
	189	corehi_irqdispatch();
	190	return IRQ_HANDLED;
	191	}
	192
39b8d525 RB	193	#ifdef CONFIG_MIPS_MT_SMP
39b8d525 RB	194
39b8d525 RB	195	#define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */
	196	#define C_RESCHED C_SW0
	197	#define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for resched */
	198	#define C_CALL C_SW1
	199	static int cpu_ipi_resched_irq, cpu_ipi_call_irq;
	200
	201	static void ipi_resched_dispatch(void)
	202	{
	203	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
	204	}
	205
	206	static void ipi_call_dispatch(void)
	207	{
	208	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
	209	}
	210
	211	static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
	212	{
9c1f6e00	213	#ifdef CONFIG_MIPS_VPE_APSP_API_CMP
1336113a DCZ	214	if (aprp_hook)
	215	aprp_hook();
	216	#endif
	217
184748cc PZ	218	scheduler_ipi();
184748cc PZ	219
39b8d525 RB	220	return IRQ_HANDLED;
	221	}
	222
	223	static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
	224	{
4ace6139	225	generic_smp_call_function_interrupt();
39b8d525 RB	226
	227	return IRQ_HANDLED;
	228	}
	229
	230	static struct irqaction irq_resched = {
	231	.handler = ipi_resched_interrupt,
8b5690f8	232	.flags = IRQF_PERCPU,
39b8d525 RB	233	.name = "IPI_resched"
	234	};
	235
	236	static struct irqaction irq_call = {
	237	.handler = ipi_call_interrupt,
8b5690f8	238	.flags = IRQF_PERCPU,
39b8d525 RB	239	.name = "IPI_call"
39b8d525 RB	240	};
18743d27	241	#endif /* CONFIG_MIPS_MT_SMP */
39b8d525	242
e01402b1	243	static struct irqaction i8259irq = {
18743d27	244	.handler = i8259_handler,
5a4a4ad8 WZ	245	.name = "XT-PIC cascade",
5a4a4ad8 WZ	246	.flags = IRQF_NO_THREAD,
e01402b1 RB	247	};
	248
	249	static struct irqaction corehi_irqaction = {
18743d27	250	.handler = corehi_handler,
5a4a4ad8 WZ	251	.name = "CoreHi",
5a4a4ad8 WZ	252	.flags = IRQF_NO_THREAD,
e01402b1 RB	253	};
e01402b1 RB	254
5792bf64	255	static msc_irqmap_t msc_irqmap[] __initdata = {
e01402b1 RB	256	{MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0},
	257	{MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0},
	258	};
5792bf64	259	static int msc_nr_irqs __initdata = ARRAY_SIZE(msc_irqmap);
e01402b1	260
5792bf64	261	static msc_irqmap_t msc_eicirqmap[] __initdata = {
e01402b1 RB	262	{MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0},
	263	{MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0},
	264	{MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0},
	265	{MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0},
	266	{MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0},
	267	{MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0},
	268	{MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0},
	269	{MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0},
	270	{MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0},
	271	{MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0}
	272	};
39b8d525	273
5792bf64	274	static int msc_nr_eicirqs __initdata = ARRAY_SIZE(msc_eicirqmap);
e01402b1	275
7098f748 CD	276	void __init arch_init_ipiirq(int irq, struct irqaction *action)
	277	{
	278	setup_irq(irq, action);
e4ec7989	279	irq_set_handler(irq, handle_percpu_irq);
7098f748 CD	280	}
7098f748 CD	281
1da177e4 LT	282	void __init arch_init_irq(void)
1da177e4 LT	283	{
18743d27 AB	284	int corehi_irq, i8259_irq;
18743d27 AB	285
1da177e4	286	init_i8259_irqs();
e01402b1 RB	287
e01402b1 RB	288	if (!cpu_has_veic)
97dcb82d	289	mips_cpu_irq_init();
e01402b1	290
237036de PB	291	if (mips_cm_present()) {
237036de PB	292	write_gcr_gic_base(GIC_BASE_ADDR \| CM_GCR_GIC_BASE_GICEN_MSK);
39b8d525 RB	293	gic_present = 1;
39b8d525 RB	294	} else {
05cf2079	295	if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) {
609ead04	296	_msc01_biu_base = ioremap_nocache(MSC01_BIU_REG_BASE,
05cf2079	297	MSC01_BIU_ADDRSPACE_SZ);
609ead04 AB	298	gic_present =
	299	(__raw_readl(_msc01_biu_base + MSC01_SC_CFG_OFS) &
	300	MSC01_SC_CFG_GICPRES_MSK) >>
	301	MSC01_SC_CFG_GICPRES_SHF;
05cf2079	302	}
39b8d525 RB	303	}
39b8d525 RB	304	if (gic_present)
7098f748	305	pr_debug("GIC present\n");
39b8d525	306
af825586 DV	307	switch (mips_revision_sconid) {
	308	case MIPS_REVISION_SCON_SOCIT:
	309	case MIPS_REVISION_SCON_ROCIT:
d725cf38	310	if (cpu_has_veic)
f8071496 DV	311	init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
	312	MSC01E_INT_BASE, msc_eicirqmap,
	313	msc_nr_eicirqs);
d725cf38	314	else
f8071496 DV	315	init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
	316	MSC01C_INT_BASE, msc_irqmap,
	317	msc_nr_irqs);
d725cf38 CD	318	break;
d725cf38 CD	319
af825586 DV	320	case MIPS_REVISION_SCON_SOCITSC:
af825586 DV	321	case MIPS_REVISION_SCON_SOCITSCP:
e01402b1	322	if (cpu_has_veic)
f8071496 DV	323	init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
	324	MSC01E_INT_BASE, msc_eicirqmap,
	325	msc_nr_eicirqs);
e01402b1	326	else
f8071496 DV	327	init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
	328	MSC01C_INT_BASE, msc_irqmap,
	329	msc_nr_irqs);
e01402b1 RB	330	}
e01402b1 RB	331
39b8d525	332	if (gic_present) {
39b8d525	333	int i;
18743d27 AB	334
	335	gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, MIPSCPU_INT_GIC,
	336	MIPS_GIC_IRQ_BASE);
237036de	337	if (!mips_cm_present()) {
39b8d525	338	/* Enable the GIC */
609ead04 AB	339	i = __raw_readl(_msc01_biu_base + MSC01_SC_CFG_OFS);
	340	__raw_writel(i \| (0x1 << MSC01_SC_CFG_GICENA_SHF),
	341	_msc01_biu_base + MSC01_SC_CFG_OFS);
39b8d525 RB	342	pr_debug("GIC Enabled\n");
39b8d525 RB	343	}
18743d27 AB	344	i8259_irq = MIPS_GIC_IRQ_BASE + GIC_INT_I8259A;
18743d27 AB	345	corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
39b8d525	346	} else {
7098f748	347	#if defined(CONFIG_MIPS_MT_SMP)
39b8d525 RB	348	/* set up ipi interrupts */
	349	if (cpu_has_veic) {
	350	set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch);
	351	set_vi_handler (MSC01E_INT_SW1, ipi_call_dispatch);
	352	cpu_ipi_resched_irq = MSC01E_INT_SW0;
	353	cpu_ipi_call_irq = MSC01E_INT_SW1;
	354	} else {
5792bf64 SH	355	cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE +
	356	MIPS_CPU_IPI_RESCHED_IRQ;
	357	cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE +
	358	MIPS_CPU_IPI_CALL_IRQ;
39b8d525	359	}
7098f748 CD	360	arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched);
7098f748 CD	361	arch_init_ipiirq(cpu_ipi_call_irq, &irq_call);
39b8d525	362	#endif
18743d27 AB	363	if (cpu_has_veic) {
	364	set_vi_handler(MSC01E_INT_I8259A,
	365	malta_hw0_irqdispatch);
	366	set_vi_handler(MSC01E_INT_COREHI,
	367	corehi_irqdispatch);
	368	i8259_irq = MSC01E_INT_BASE + MSC01E_INT_I8259A;
	369	corehi_irq = MSC01E_INT_BASE + MSC01E_INT_COREHI;
	370	} else {
	371	i8259_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_I8259A;
	372	corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
	373	}
7098f748	374	}
18743d27 AB	375
	376	setup_irq(i8259_irq, &i8259irq);
	377	setup_irq(corehi_irq, &corehi_irqaction);
39b8d525 RB	378	}
	379
	380	void malta_be_init(void)
	381	{
5792bf64	382	/* Could change CM error mask register. */
39b8d525 RB	383	}
39b8d525 RB	384
39b8d525 RB	385	int malta_be_handler(struct pt_regs *regs, int is_fixup)
	386	{
	387	/* This duplicates the handling in do_be which seems wrong */
	388	int retval = is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
	389
3885c2b4	390	mips_cm_error_report();
39b8d525 RB	391
39b8d525 RB	392	return retval;
1da177e4	393	}