Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[deliverable/linux.git] / arch / mips / mti-malta / malta-memory.c
CommitLineData
1da177e4 1/*
49bffbdc
SH
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
1da177e4
LT
5 *
6 * PROM library functions for acquiring/using memory descriptors given to
7 * us from the YAMON.
49bffbdc
SH
8 *
9 * Copyright (C) 1999,2000,2012 MIPS Technologies, Inc.
10 * All rights reserved.
11 * Authors: Carsten Langgaard <carstenl@mips.com>
12 * Steven J. Hill <sjhill@mips.com>
1da177e4 13 */
1da177e4 14#include <linux/init.h>
1da177e4 15#include <linux/bootmem.h>
e01402b1 16#include <linux/string.h>
1da177e4
LT
17
18#include <asm/bootinfo.h>
296b7c68 19#include <asm/cdmm.h>
3a551e25 20#include <asm/maar.h>
9c1f1257 21#include <asm/sections.h>
b431f09d 22#include <asm/fw/fw.h>
1da177e4 23
b431f09d 24static fw_memblock_t mdesc[FW_MAX_MEMBLOCKS];
1da177e4 25
70342287 26/* determined physical memory size, not overridden by command line args */
e1a4e469
RB
27unsigned long physical_memsize = 0L;
28
e6ca4e5b 29fw_memblock_t * __init fw_getmdesc(int eva)
1da177e4 30{
acd8bc1a 31 char *memsize_str, *ememsize_str = NULL, *ptr;
f8647b50 32 unsigned long memsize = 0, ememsize = 0;
7580c9c3 33 static char cmdline[COMMAND_LINE_SIZE] __initdata;
49bffbdc 34 int tmp;
1da177e4 35
e1a4e469 36 /* otherwise look in the environment */
e6ca4e5b 37
b431f09d 38 memsize_str = fw_getenv("memsize");
64615682
MC
39 if (memsize_str) {
40 tmp = kstrtoul(memsize_str, 0, &memsize);
41 if (tmp)
42 pr_warn("Failed to read the 'memsize' env variable.\n");
43 }
e6ca4e5b
MC
44 if (eva) {
45 /* Look for ememsize for EVA */
46 ememsize_str = fw_getenv("ememsize");
64615682
MC
47 if (ememsize_str) {
48 tmp = kstrtoul(ememsize_str, 0, &ememsize);
49 if (tmp)
50 pr_warn("Failed to read the 'ememsize' env variable.\n");
51 }
e6ca4e5b
MC
52 }
53 if (!memsize && !ememsize) {
49bffbdc 54 pr_warn("memsize not set in YAMON, set to default (32Mb)\n");
e1a4e469
RB
55 physical_memsize = 0x02000000;
56 } else {
f7f8aea4
MC
57 if (memsize > (256 << 20)) { /* memsize should be capped to 256M */
58 pr_warn("Unsupported memsize value (0x%lx) detected! "
59 "Using 0x10000000 (256M) instead\n",
60 memsize);
61 memsize = 256 << 20;
62 }
e6ca4e5b
MC
63 /* If ememsize is set, then set physical_memsize to that */
64 physical_memsize = ememsize ? : memsize;
1da177e4 65 }
73499682
EO
66
67#ifdef CONFIG_CPU_BIG_ENDIAN
e1a4e469
RB
68 /* SOC-it swaps, or perhaps doesn't swap, when DMA'ing the last
69 word of physical memory */
70 physical_memsize -= PAGE_SIZE;
73499682
EO
71#endif
72
e1a4e469
RB
73 /* Check the command line for a memsize directive that overrides
74 the physical/default amount */
75 strcpy(cmdline, arcs_cmdline);
76 ptr = strstr(cmdline, "memsize=");
77 if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' '))
78 ptr = strstr(ptr, " memsize=");
e6ca4e5b
MC
79 /* And now look for ememsize */
80 if (eva) {
81 ptr = strstr(cmdline, "ememsize=");
82 if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' '))
83 ptr = strstr(ptr, " ememsize=");
84 }
e1a4e469
RB
85
86 if (ptr)
e6ca4e5b 87 memsize = memparse(ptr + 8 + (eva ? 1 : 0), &ptr);
e1a4e469
RB
88 else
89 memsize = physical_memsize;
90
e6ca4e5b
MC
91 /* Last 64K for HIGHMEM arithmetics */
92 if (memsize > 0x7fff0000)
93 memsize = 0x7fff0000;
94
1da177e4
LT
95 memset(mdesc, 0, sizeof(mdesc));
96
b431f09d 97 mdesc[0].type = fw_dontuse;
3bdd8e6e 98 mdesc[0].base = PHYS_OFFSET;
1da177e4
LT
99 mdesc[0].size = 0x00001000;
100
b431f09d 101 mdesc[1].type = fw_code;
3bdd8e6e 102 mdesc[1].base = mdesc[0].base + 0x00001000UL;
1da177e4
LT
103 mdesc[1].size = 0x000ef000;
104
1da177e4
LT
105 /*
106 * The area 0x000f0000-0x000fffff is allocated for BIOS memory by the
107 * south bridge and PCI access always forwarded to the ISA Bus and
108 * BIOSCS# is always generated.
109 * This mean that this area can't be used as DMA memory for PCI
110 * devices.
111 */
b431f09d 112 mdesc[2].type = fw_dontuse;
3bdd8e6e 113 mdesc[2].base = mdesc[0].base + 0x000f0000UL;
1da177e4 114 mdesc[2].size = 0x00010000;
1da177e4 115
b431f09d 116 mdesc[3].type = fw_dontuse;
3bdd8e6e 117 mdesc[3].base = mdesc[0].base + 0x00100000UL;
49bffbdc 118 mdesc[3].size = CPHYSADDR(PFN_ALIGN((unsigned long)&_end)) -
3bdd8e6e 119 0x00100000UL;
1da177e4 120
b431f09d 121 mdesc[4].type = fw_free;
3bdd8e6e
MC
122 mdesc[4].base = mdesc[0].base + CPHYSADDR(PFN_ALIGN(&_end));
123 mdesc[4].size = memsize - CPHYSADDR(mdesc[4].base);
1da177e4
LT
124
125 return &mdesc[0];
126}
127
d1965c06
MC
128static void free_init_pages_eva_malta(void *begin, void *end)
129{
130 free_init_pages("unused kernel", __pa_symbol((unsigned long *)begin),
131 __pa_symbol((unsigned long *)end));
132}
133
b431f09d 134static int __init fw_memtype_classify(unsigned int type)
1da177e4
LT
135{
136 switch (type) {
b431f09d 137 case fw_free:
1da177e4 138 return BOOT_MEM_RAM;
b431f09d 139 case fw_code:
1da177e4
LT
140 return BOOT_MEM_ROM_DATA;
141 default:
142 return BOOT_MEM_RESERVED;
143 }
144}
145
b431f09d 146void __init fw_meminit(void)
1da177e4 147{
b431f09d 148 fw_memblock_t *p;
1da177e4 149
e6ca4e5b 150 p = fw_getmdesc(config_enabled(CONFIG_EVA));
d1965c06
MC
151 free_init_pages_eva = (config_enabled(CONFIG_EVA) ?
152 free_init_pages_eva_malta : NULL);
1da177e4
LT
153
154 while (p->size) {
155 long type;
156 unsigned long base, size;
157
b431f09d 158 type = fw_memtype_classify(p->type);
1da177e4
LT
159 base = p->base;
160 size = p->size;
161
162 add_memory_region(base, size, type);
70342287 163 p++;
1da177e4
LT
164 }
165}
166
c44e8d5e 167void __init prom_free_prom_memory(void)
1da177e4 168{
1da177e4
LT
169 unsigned long addr;
170 int i;
171
172 for (i = 0; i < boot_mem_map.nr_map; i++) {
173 if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
174 continue;
175
c44e8d5e 176 addr = boot_mem_map.map[i].addr;
49bffbdc 177 free_init_pages("YAMON memory",
c44e8d5e 178 addr, addr + boot_mem_map.map[i].size);
1da177e4 179 }
1da177e4 180}
3a551e25
PB
181
182unsigned platform_maar_init(unsigned num_pairs)
183{
184 phys_addr_t mem_end = (physical_memsize & ~0xffffull) - 1;
185 struct maar_config cfg[] = {
186 /* DRAM preceding I/O */
187 { 0x00000000, 0x0fffffff, MIPS_MAAR_S },
188
189 /* DRAM following I/O */
190 { 0x20000000, mem_end, MIPS_MAAR_S },
191
192 /* DRAM alias in upper half of physical */
193 { 0x80000000, 0x80000000 + mem_end, MIPS_MAAR_S },
194 };
195 unsigned i, num_cfg = ARRAY_SIZE(cfg);
196
197 /* If DRAM fits before I/O, drop the region following it */
198 if (physical_memsize <= 0x10000000) {
199 num_cfg--;
200 for (i = 1; i < num_cfg; i++)
201 cfg[i] = cfg[i + 1];
202 }
203
204 return maar_config(cfg, num_cfg, num_pairs);
205}
296b7c68
JH
206
207phys_addr_t mips_cdmm_phys_base(void)
208{
209 /* This address is "typically unused" */
210 return 0x1fc10000;
211}
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