Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Carsten Langgaard, carstenl@mips.com | |
3 | * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can distribute it and/or modify it | |
6 | * under the terms of the GNU General Public License (Version 2) as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 | * for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along | |
15 | * with this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | |
17 | * | |
18 | * Setting up the clock on the MIPS boards. | |
19 | */ | |
1da177e4 | 20 | #include <linux/types.h> |
334955ef | 21 | #include <linux/i8253.h> |
1da177e4 LT |
22 | #include <linux/init.h> |
23 | #include <linux/kernel_stat.h> | |
24e1df66 | 24 | #include <linux/math64.h> |
1da177e4 LT |
25 | #include <linux/sched.h> |
26 | #include <linux/spinlock.h> | |
27 | #include <linux/interrupt.h> | |
4060bbe9 | 28 | #include <linux/irqchip/mips-gic.h> |
1da177e4 LT |
29 | #include <linux/timex.h> |
30 | #include <linux/mc146818rtc.h> | |
31 | ||
8ff374b9 | 32 | #include <asm/cpu.h> |
1da177e4 | 33 | #include <asm/mipsregs.h> |
41c594ab | 34 | #include <asm/mipsmtregs.h> |
e01402b1 RB |
35 | #include <asm/hardirq.h> |
36 | #include <asm/irq.h> | |
1da177e4 | 37 | #include <asm/div64.h> |
b81947c6 | 38 | #include <asm/setup.h> |
1da177e4 LT |
39 | #include <asm/time.h> |
40 | #include <asm/mc146818-time.h> | |
e01402b1 | 41 | #include <asm/msc01_ic.h> |
1da177e4 LT |
42 | |
43 | #include <asm/mips-boards/generic.h> | |
e01402b1 | 44 | #include <asm/mips-boards/maltaint.h> |
1da177e4 | 45 | |
e01402b1 | 46 | static int mips_cpu_timer_irq; |
39b8d525 | 47 | static int mips_cpu_perf_irq; |
3b1d4ed5 | 48 | extern int cp0_perfcount_irq; |
1da177e4 | 49 | |
b0854514 AB |
50 | static unsigned int gic_frequency; |
51 | ||
937a8015 | 52 | static void mips_timer_dispatch(void) |
1da177e4 | 53 | { |
937a8015 | 54 | do_IRQ(mips_cpu_timer_irq); |
e01402b1 RB |
55 | } |
56 | ||
ffe9ee47 CD |
57 | static void mips_perf_dispatch(void) |
58 | { | |
39b8d525 | 59 | do_IRQ(mips_cpu_perf_irq); |
ffe9ee47 CD |
60 | } |
61 | ||
778eeb1b SH |
62 | static unsigned int freqround(unsigned int freq, unsigned int amount) |
63 | { | |
64 | freq += amount; | |
65 | freq -= freq % (amount*2); | |
66 | return freq; | |
67 | } | |
68 | ||
1da177e4 | 69 | /* |
778eeb1b | 70 | * Estimate CPU and GIC frequencies. |
1da177e4 | 71 | */ |
778eeb1b | 72 | static void __init estimate_frequencies(void) |
1da177e4 | 73 | { |
e79f55a8 | 74 | unsigned long flags; |
778eeb1b | 75 | unsigned int count, start; |
24e1df66 JH |
76 | unsigned char secs1, secs2, ctrl; |
77 | int secs; | |
7d9ad5d8 | 78 | cycle_t giccount = 0, gicstart = 0; |
1da177e4 | 79 | |
eda3d33c JH |
80 | #if defined(CONFIG_KVM_GUEST) && CONFIG_KVM_GUEST_TIMER_FREQ |
81 | mips_hpt_frequency = CONFIG_KVM_GUEST_TIMER_FREQ * 1000000; | |
9843b030 SL |
82 | return; |
83 | #endif | |
84 | ||
1da177e4 LT |
85 | local_irq_save(flags); |
86 | ||
aab4673b JH |
87 | if (gic_present) |
88 | gic_start_count(); | |
89 | ||
24e1df66 JH |
90 | /* |
91 | * Read counters exactly on rising edge of update flag. | |
92 | * This helps get an accurate reading under virtualisation. | |
93 | */ | |
1da177e4 LT |
94 | while (CMOS_READ(RTC_REG_A) & RTC_UIP); |
95 | while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); | |
70e46f48 | 96 | start = read_c0_count(); |
aab4673b | 97 | if (gic_present) |
7d9ad5d8 | 98 | gicstart = gic_read_count(); |
1da177e4 | 99 | |
24e1df66 | 100 | /* Wait for falling edge before reading RTC. */ |
1da177e4 | 101 | while (CMOS_READ(RTC_REG_A) & RTC_UIP); |
24e1df66 | 102 | secs1 = CMOS_READ(RTC_SECONDS); |
1da177e4 | 103 | |
24e1df66 JH |
104 | /* Read counters again exactly on rising edge of update flag. */ |
105 | while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); | |
778eeb1b SH |
106 | count = read_c0_count(); |
107 | if (gic_present) | |
7d9ad5d8 | 108 | giccount = gic_read_count(); |
1da177e4 | 109 | |
24e1df66 JH |
110 | /* Wait for falling edge before reading RTC again. */ |
111 | while (CMOS_READ(RTC_REG_A) & RTC_UIP); | |
112 | secs2 = CMOS_READ(RTC_SECONDS); | |
113 | ||
114 | ctrl = CMOS_READ(RTC_CONTROL); | |
115 | ||
1da177e4 | 116 | local_irq_restore(flags); |
1da177e4 | 117 | |
24e1df66 JH |
118 | if (!(ctrl & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { |
119 | secs1 = bcd2bin(secs1); | |
120 | secs2 = bcd2bin(secs2); | |
121 | } | |
122 | secs = secs2 - secs1; | |
123 | if (secs < 1) | |
124 | secs += 60; | |
125 | ||
778eeb1b | 126 | count -= start; |
24e1df66 | 127 | count /= secs; |
778eeb1b | 128 | mips_hpt_frequency = count; |
dfa762e1 | 129 | |
dfa762e1 | 130 | if (gic_present) { |
24e1df66 | 131 | giccount = div_u64(giccount - gicstart, secs); |
778eeb1b | 132 | gic_frequency = giccount; |
dfa762e1 | 133 | } |
1da177e4 LT |
134 | } |
135 | ||
d4f587c6 | 136 | void read_persistent_clock(struct timespec *ts) |
1da177e4 | 137 | { |
d4f587c6 MS |
138 | ts->tv_sec = mc146818_get_cmos_time(); |
139 | ts->tv_nsec = 0; | |
1da177e4 LT |
140 | } |
141 | ||
602e8a34 JH |
142 | int get_c0_fdc_int(void) |
143 | { | |
6249ecbb JH |
144 | /* |
145 | * Some cores claim the FDC is routable through the GIC, but it doesn't | |
146 | * actually seem to be connected for those Malta bitstreams. | |
147 | */ | |
148 | switch (current_cpu_type()) { | |
149 | case CPU_INTERAPTIV: | |
150 | case CPU_PROAPTIV: | |
151 | return -1; | |
152 | }; | |
602e8a34 JH |
153 | |
154 | if (cpu_has_veic) | |
6249ecbb | 155 | return -1; |
602e8a34 | 156 | else if (gic_present) |
6249ecbb | 157 | return gic_get_c0_fdc_int(); |
602e8a34 | 158 | else if (cp0_fdc_irq >= 0) |
6249ecbb | 159 | return MIPS_CPU_IRQ_BASE + cp0_fdc_irq; |
602e8a34 | 160 | else |
6249ecbb | 161 | return -1; |
602e8a34 JH |
162 | } |
163 | ||
a669efc4 | 164 | int get_c0_perfcount_int(void) |
ffe9ee47 | 165 | { |
e01402b1 | 166 | if (cpu_has_veic) { |
49a89efb | 167 | set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch); |
39b8d525 | 168 | mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; |
e9de688d AB |
169 | } else if (gic_present) { |
170 | mips_cpu_perf_irq = gic_get_c0_perfcount_int(); | |
a669efc4 | 171 | } else if (cp0_perfcount_irq >= 0) { |
39b8d525 | 172 | mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; |
a669efc4 AB |
173 | } else { |
174 | mips_cpu_perf_irq = -1; | |
e01402b1 | 175 | } |
a669efc4 AB |
176 | |
177 | return mips_cpu_perf_irq; | |
ffe9ee47 | 178 | } |
0cb0985f | 179 | EXPORT_SYMBOL_GPL(get_c0_perfcount_int); |
e01402b1 | 180 | |
078a55fc | 181 | unsigned int get_c0_compare_int(void) |
ffe9ee47 | 182 | { |
ffe9ee47 | 183 | if (cpu_has_veic) { |
49a89efb | 184 | set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch); |
ffe9ee47 | 185 | mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; |
e9de688d AB |
186 | } else if (gic_present) { |
187 | mips_cpu_timer_irq = gic_get_c0_compare_int(); | |
188 | } else { | |
3b1d4ed5 | 189 | mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; |
ffe9ee47 | 190 | } |
e01402b1 | 191 | |
38760d40 RB |
192 | return mips_cpu_timer_irq; |
193 | } | |
194 | ||
a87ea88d PB |
195 | static void __init init_rtc(void) |
196 | { | |
106eccb4 | 197 | unsigned char freq, ctrl; |
a87ea88d | 198 | |
106eccb4 JH |
199 | /* Set 32KHz time base if not already set */ |
200 | freq = CMOS_READ(RTC_FREQ_SELECT); | |
201 | if ((freq & RTC_DIV_CTL) != RTC_REF_CLCK_32KHZ) | |
202 | CMOS_WRITE(RTC_REF_CLCK_32KHZ, RTC_FREQ_SELECT); | |
a87ea88d | 203 | |
106eccb4 JH |
204 | /* Ensure SET bit is clear so RTC can run */ |
205 | ctrl = CMOS_READ(RTC_CONTROL); | |
206 | if (ctrl & RTC_SET) | |
207 | CMOS_WRITE(ctrl & ~RTC_SET, RTC_CONTROL); | |
a87ea88d PB |
208 | } |
209 | ||
38760d40 RB |
210 | void __init plat_time_init(void) |
211 | { | |
8ff374b9 | 212 | unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK); |
778eeb1b | 213 | unsigned int freq; |
38760d40 | 214 | |
a87ea88d | 215 | init_rtc(); |
778eeb1b | 216 | estimate_frequencies(); |
38760d40 | 217 | |
778eeb1b SH |
218 | freq = mips_hpt_frequency; |
219 | if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && | |
220 | (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) | |
221 | freq *= 2; | |
222 | freq = freqround(freq, 5000); | |
dfa762e1 | 223 | printk("CPU frequency %d.%02d MHz\n", freq/1000000, |
778eeb1b | 224 | (freq%1000000)*100/1000000); |
778eeb1b | 225 | |
dfa762e1 | 226 | mips_scroll_message(); |
38760d40 | 227 | |
778eeb1b SH |
228 | #ifdef CONFIG_I8253 |
229 | /* Only Malta has a PIT. */ | |
38760d40 | 230 | setup_pit_timer(); |
340ee4b9 | 231 | #endif |
ffe9ee47 | 232 | |
8a19b8f1 | 233 | #ifdef CONFIG_MIPS_GIC |
dfa762e1 SH |
234 | if (gic_present) { |
235 | freq = freqround(gic_frequency, 5000); | |
236 | printk("GIC frequency %d.%02d MHz\n", freq/1000000, | |
237 | (freq%1000000)*100/1000000); | |
fa5635a2 | 238 | #ifdef CONFIG_CLKSRC_MIPS_GIC |
dfa762e1 SH |
239 | gic_clocksource_init(gic_frequency); |
240 | #endif | |
241 | } | |
242 | #endif | |
1da177e4 | 243 | } |