[deliverable/linux.git] / arch / mips / netlogic / xlp / nlm_hal.c

/*
 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
 * reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the NetLogic
 * license below:
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/delay.h>

#include <asm/mipsregs.h>
#include <asm/time.h>

#include <asm/netlogic/common.h>
#include <asm/netlogic/haldefs.h>
#include <asm/netlogic/xlp-hal/iomap.h>
#include <asm/netlogic/xlp-hal/xlp.h>
#include <asm/netlogic/xlp-hal/bridge.h>
#include <asm/netlogic/xlp-hal/pic.h>
#include <asm/netlogic/xlp-hal/sys.h>

/* Main initialization */
void nlm_node_init(int node)
{
	struct nlm_soc_info *nodep;

	nodep = nlm_get_node(node);
	if (node == 0)
		nodep->coremask = 1;	/* node 0, boot cpu */
	nodep->sysbase = nlm_get_sys_regbase(node);
	nodep->picbase = nlm_get_pic_regbase(node);
	nodep->ebase = read_c0_ebase() & (~((1 << 12) - 1));
	if (cpu_is_xlp9xx())
		nodep->socbus = xlp9xx_get_socbus(node);
	else
		nodep->socbus = 0;
	spin_lock_init(&nodep->piclock);
}

static int xlp9xx_irq_to_irt(int irq)
{
	switch (irq) {
	case PIC_GPIO_IRQ:
		return 12;
	case PIC_9XX_XHCI_0_IRQ:
		return 114;
	case PIC_9XX_XHCI_1_IRQ:
		return 115;
	case PIC_UART_0_IRQ:
		return 133;
	case PIC_UART_1_IRQ:
		return 134;
	case PIC_SATA_IRQ:
		return 143;
	case PIC_SPI_IRQ:
		return 152;
	case PIC_MMC_IRQ:
		return 153;
	case PIC_PCIE_LINK_LEGACY_IRQ(0):
	case PIC_PCIE_LINK_LEGACY_IRQ(1):
	case PIC_PCIE_LINK_LEGACY_IRQ(2):
	case PIC_PCIE_LINK_LEGACY_IRQ(3):
		return 191 + irq - PIC_PCIE_LINK_LEGACY_IRQ_BASE;
	}
	return -1;
}

static int xlp_irq_to_irt(int irq)
{
	uint64_t pcibase;
	int devoff, irt;

	devoff = 0;
	switch (irq) {
	case PIC_UART_0_IRQ:
		devoff = XLP_IO_UART0_OFFSET(0);
		break;
	case PIC_UART_1_IRQ:
		devoff = XLP_IO_UART1_OFFSET(0);
		break;
	case PIC_MMC_IRQ:
		devoff = XLP_IO_MMC_OFFSET(0);
		break;
	case PIC_I2C_0_IRQ:	/* I2C will be fixed up */
	case PIC_I2C_1_IRQ:
	case PIC_I2C_2_IRQ:
	case PIC_I2C_3_IRQ:
		if (cpu_is_xlpii())
			devoff = XLP2XX_IO_I2C_OFFSET(0);
		else
			devoff = XLP_IO_I2C0_OFFSET(0);
		break;
	case PIC_SATA_IRQ:
		devoff = XLP_IO_SATA_OFFSET(0);
		break;
	case PIC_GPIO_IRQ:
		devoff = XLP_IO_GPIO_OFFSET(0);
		break;
	case PIC_NAND_IRQ:
		devoff = XLP_IO_NAND_OFFSET(0);
		break;
	case PIC_SPI_IRQ:
		devoff = XLP_IO_SPI_OFFSET(0);
		break;
	default:
		if (cpu_is_xlpii()) {
			switch (irq) {
				/* XLP2XX has three XHCI USB controller */
			case PIC_2XX_XHCI_0_IRQ:
				devoff = XLP2XX_IO_USB_XHCI0_OFFSET(0);
				break;
			case PIC_2XX_XHCI_1_IRQ:
				devoff = XLP2XX_IO_USB_XHCI1_OFFSET(0);
				break;
			case PIC_2XX_XHCI_2_IRQ:
				devoff = XLP2XX_IO_USB_XHCI2_OFFSET(0);
				break;
			}
		} else {
			switch (irq) {
			case PIC_EHCI_0_IRQ:
				devoff = XLP_IO_USB_EHCI0_OFFSET(0);
				break;
			case PIC_EHCI_1_IRQ:
				devoff = XLP_IO_USB_EHCI1_OFFSET(0);
				break;
			case PIC_OHCI_0_IRQ:
				devoff = XLP_IO_USB_OHCI0_OFFSET(0);
				break;
			case PIC_OHCI_1_IRQ:
				devoff = XLP_IO_USB_OHCI1_OFFSET(0);
				break;
			case PIC_OHCI_2_IRQ:
				devoff = XLP_IO_USB_OHCI2_OFFSET(0);
				break;
			case PIC_OHCI_3_IRQ:
				devoff = XLP_IO_USB_OHCI3_OFFSET(0);
				break;
			}
		}
	}

	if (devoff != 0) {
		pcibase = nlm_pcicfg_base(devoff);
		irt = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) & 0xffff;
		/* HW weirdness, I2C IRT entry has to be fixed up */
		switch (irq) {
		case PIC_I2C_1_IRQ:
			irt = irt + 1; break;
		case PIC_I2C_2_IRQ:
			irt = irt + 2; break;
		case PIC_I2C_3_IRQ:
			irt = irt + 3; break;
		}
	} else if (irq >= PIC_PCIE_LINK_LEGACY_IRQ(0) &&
			irq <= PIC_PCIE_LINK_LEGACY_IRQ(3)) {
		/* HW bug, PCI IRT entries are bad on early silicon, fix */
		irt = PIC_IRT_PCIE_LINK_INDEX(irq -
					PIC_PCIE_LINK_LEGACY_IRQ_BASE);
	} else {
		irt = -1;
	}
	return irt;
}

int nlm_irq_to_irt(int irq)
{
	/* return -2 for irqs without 1-1 mapping */
	if (irq >= PIC_PCIE_LINK_MSI_IRQ(0) && irq <= PIC_PCIE_LINK_MSI_IRQ(3))
		return -2;
	if (irq >= PIC_PCIE_MSIX_IRQ(0) && irq <= PIC_PCIE_MSIX_IRQ(3))
		return -2;

	if (cpu_is_xlp9xx())
		return xlp9xx_irq_to_irt(irq);
	else
		return xlp_irq_to_irt(irq);
}

unsigned int nlm_get_core_frequency(int node, int core)
{
	unsigned int pll_divf, pll_divr, dfs_div, ext_div;
	unsigned int rstval, dfsval, denom;
	uint64_t num, sysbase;

	sysbase = nlm_get_node(node)->sysbase;
	if (cpu_is_xlp9xx())
		rstval = nlm_read_sys_reg(sysbase, SYS_9XX_POWER_ON_RESET_CFG);
	else
		rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG);
	if (cpu_is_xlpii()) {
		num = 1000000ULL * (400 * 3 + 100 * (rstval >> 26));
		denom = 3;
	} else {
		dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE);
		pll_divf = ((rstval >> 10) & 0x7f) + 1;
		pll_divr = ((rstval >> 8)  & 0x3) + 1;
		ext_div  = ((rstval >> 30) & 0x3) + 1;
		dfs_div  = ((dfsval >> (core * 4)) & 0xf) + 1;

		num = 800000000ULL * pll_divf;
		denom = 3 * pll_divr * ext_div * dfs_div;
	}
	do_div(num, denom);
	return (unsigned int)num;
}

/* Calculate Frequency to the PIC from PLL.
 * freq_out = ( ref_freq/2 * (6 + ctrl2[7:0]) + ctrl2[20:8]/2^13 ) /
 * ((2^ctrl0[7:5]) * Table(ctrl0[26:24]))
 */
static unsigned int nlm_2xx_get_pic_frequency(int node)
{
	u32 ctrl_val0, ctrl_val2, vco_post_div, pll_post_div;
	u32 mdiv, fdiv, pll_out_freq_den, reg_select, ref_div, pic_div;
	u64 ref_clk, sysbase, pll_out_freq_num, ref_clk_select;

	sysbase = nlm_get_node(node)->sysbase;

	/* Find ref_clk_base */
	ref_clk_select =
		(nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG) >> 18) & 0x3;
	switch (ref_clk_select) {
	case 0:
		ref_clk = 200000000ULL;
		ref_div = 3;
		break;
	case 1:
		ref_clk = 100000000ULL;
		ref_div = 1;
		break;
	case 2:
		ref_clk = 125000000ULL;
		ref_div = 1;
		break;
	case 3:
		ref_clk = 400000000ULL;
		ref_div = 3;
		break;
	}

	/* Find the clock source PLL device for PIC */
	reg_select = (nlm_read_sys_reg(sysbase, SYS_CLK_DEV_SEL) >> 22) & 0x3;
	switch (reg_select) {
	case 0:
		ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0);
		ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2);
		break;
	case 1:
		ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(0));
		ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(0));
		break;
	case 2:
		ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(1));
		ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(1));
		break;
	case 3:
		ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(2));
		ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(2));
		break;
	}

	vco_post_div = (ctrl_val0 >> 5) & 0x7;
	pll_post_div = (ctrl_val0 >> 24) & 0x7;
	mdiv = ctrl_val2 & 0xff;
	fdiv = (ctrl_val2 >> 8) & 0xfff;

	/* Find PLL post divider value */
	switch (pll_post_div) {
	case 1:
		pll_post_div = 2;
		break;
	case 3:
		pll_post_div = 4;
		break;
	case 7:
		pll_post_div = 8;
		break;
	case 6:
		pll_post_div = 16;
		break;
	case 0:
	default:
		pll_post_div = 1;
		break;
	}

	fdiv = fdiv/(1 << 13);
	pll_out_freq_num = ((ref_clk >> 1) * (6 + mdiv)) + fdiv;
	pll_out_freq_den = (1 << vco_post_div) * pll_post_div * 3;

	if (pll_out_freq_den > 0)
		do_div(pll_out_freq_num, pll_out_freq_den);

	/* PIC post divider, which happens after PLL */
	pic_div = (nlm_read_sys_reg(sysbase, SYS_CLK_DEV_DIV) >> 22) & 0x3;
	do_div(pll_out_freq_num, 1 << pic_div);

	return pll_out_freq_num;
}

unsigned int nlm_get_pic_frequency(int node)
{
	/* TODO Has to calculate freq as like 2xx */
	if (cpu_is_xlp9xx())
		return 250000000;

	if (cpu_is_xlpii())
		return nlm_2xx_get_pic_frequency(node);
	else
		return 133333333;
}

unsigned int nlm_get_cpu_frequency(void)
{
	return nlm_get_core_frequency(0, 0);
}

/*
 * Fills upto 8 pairs of entries containing the DRAM map of a node
 * if n < 0, get dram map for all nodes
 */
int xlp_get_dram_map(int n, uint64_t *dram_map)
{
	uint64_t bridgebase, base, lim;
	uint32_t val;
	unsigned int barreg, limreg, xlatreg;
	int i, node, rv;

	/* Look only at mapping on Node 0, we don't handle crazy configs */
	bridgebase = nlm_get_bridge_regbase(0);
	rv = 0;
	for (i = 0; i < 8; i++) {
		if (cpu_is_xlp9xx()) {
			barreg = BRIDGE_9XX_DRAM_BAR(i);
			limreg = BRIDGE_9XX_DRAM_LIMIT(i);
			xlatreg = BRIDGE_9XX_DRAM_NODE_TRANSLN(i);
		} else {
			barreg = BRIDGE_DRAM_BAR(i);
			limreg = BRIDGE_DRAM_LIMIT(i);
			xlatreg = BRIDGE_DRAM_NODE_TRANSLN(i);
		}
		if (n >= 0) {
			/* node specified, get node mapping of BAR */
			val = nlm_read_bridge_reg(bridgebase, xlatreg);
			node = (val >> 1) & 0x3;
			if (n != node)
				continue;
		}
		val = nlm_read_bridge_reg(bridgebase, barreg);
		val = (val >>  12) & 0xfffff;
		base = (uint64_t) val << 20;
		val = nlm_read_bridge_reg(bridgebase, limreg);
		val = (val >>  12) & 0xfffff;
		if (val == 0)   /* BAR not used */
			continue;
		lim = ((uint64_t)val + 1) << 20;
		dram_map[rv] = base;
		dram_map[rv + 1] = lim;
		rv += 2;
	}
	return rv;
}
Commit	Line	Data
65040e22 J	1	/*
	2	* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
	3	* reserved.
	4	*
	5	* This software is available to you under a choice of one of two
	6	* licenses. You may choose to be licensed under the terms of the GNU
	7	* General Public License (GPL) Version 2, available from the file
	8	* COPYING in the main directory of this source tree, or the NetLogic
	9	* license below:
	10	*
	11	* Redistribution and use in source and binary forms, with or without
	12	* modification, are permitted provided that the following conditions
	13	* are met:
	14	*
	15	* 1. Redistributions of source code must retain the above copyright
	16	* notice, this list of conditions and the following disclaimer.
	17	* 2. Redistributions in binary form must reproduce the above copyright
	18	* notice, this list of conditions and the following disclaimer in
	19	* the documentation and/or other materials provided with the
	20	* distribution.
	21	*
	22	* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
	23	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	24	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	25	* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	27	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	28	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
	29	* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
	30	* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
	31	* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
	32	* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	33	*/
	34
	35	#include <linux/types.h>
	36	#include <linux/kernel.h>
	37	#include <linux/mm.h>
	38	#include <linux/delay.h>
	39
	40	#include <asm/mipsregs.h>
	41	#include <asm/time.h>
	42
77ae798f	43	#include <asm/netlogic/common.h>
65040e22 J	44	#include <asm/netlogic/haldefs.h>
	45	#include <asm/netlogic/xlp-hal/iomap.h>
	46	#include <asm/netlogic/xlp-hal/xlp.h>
a2ba6cd6	47	#include <asm/netlogic/xlp-hal/bridge.h>
65040e22 J	48	#include <asm/netlogic/xlp-hal/pic.h>
	49	#include <asm/netlogic/xlp-hal/sys.h>
	50
65040e22	51	/* Main initialization */
77ae798f	52	void nlm_node_init(int node)
65040e22	53	{
77ae798f J	54	struct nlm_soc_info *nodep;
	55
	56	nodep = nlm_get_node(node);
3e468567 J	57	if (node == 0)
3e468567 J	58	nodep->coremask = 1; /* node 0, boot cpu */
77ae798f J	59	nodep->sysbase = nlm_get_sys_regbase(node);
	60	nodep->picbase = nlm_get_pic_regbase(node);
	61	nodep->ebase = read_c0_ebase() & (~((1 << 12) - 1));
5513c760 J	62	if (cpu_is_xlp9xx())
	63	nodep->socbus = xlp9xx_get_socbus(node);
	64	else
	65	nodep->socbus = 0;
77ae798f	66	spin_lock_init(&nodep->piclock);
65040e22 J	67	}
65040e22 J	68
0d57eba0 J	69	static int xlp9xx_irq_to_irt(int irq)
	70	{
	71	switch (irq) {
	72	case PIC_GPIO_IRQ:
	73	return 12;
	74	case PIC_9XX_XHCI_0_IRQ:
	75	return 114;
	76	case PIC_9XX_XHCI_1_IRQ:
	77	return 115;
	78	case PIC_UART_0_IRQ:
	79	return 133;
	80	case PIC_UART_1_IRQ:
	81	return 134;
	82	case PIC_SATA_IRQ:
	83	return 143;
	84	case PIC_SPI_IRQ:
	85	return 152;
	86	case PIC_MMC_IRQ:
	87	return 153;
	88	case PIC_PCIE_LINK_LEGACY_IRQ(0):
	89	case PIC_PCIE_LINK_LEGACY_IRQ(1):
	90	case PIC_PCIE_LINK_LEGACY_IRQ(2):
	91	case PIC_PCIE_LINK_LEGACY_IRQ(3):
	92	return 191 + irq - PIC_PCIE_LINK_LEGACY_IRQ_BASE;
	93	}
	94	return -1;
	95	}
	96
	97	static int xlp_irq_to_irt(int irq)
65040e22	98	{
3c0553e7 J	99	uint64_t pcibase;
3c0553e7 J	100	int devoff, irt;
65040e22	101
9eac3591	102	devoff = 0;
65040e22 J	103	switch (irq) {
65040e22 J	104	case PIC_UART_0_IRQ:
3c0553e7 J	105	devoff = XLP_IO_UART0_OFFSET(0);
3c0553e7 J	106	break;
65040e22	107	case PIC_UART_1_IRQ:
3c0553e7 J	108	devoff = XLP_IO_UART1_OFFSET(0);
3c0553e7 J	109	break;
57d7cdb6	110	case PIC_MMC_IRQ:
0d57eba0	111	devoff = XLP_IO_MMC_OFFSET(0);
3c0553e7	112	break;
e5be1fd0	113	case PIC_I2C_0_IRQ: /* I2C will be fixed up */
57d7cdb6	114	case PIC_I2C_1_IRQ:
e5be1fd0 GR	115	case PIC_I2C_2_IRQ:
	116	case PIC_I2C_3_IRQ:
	117	if (cpu_is_xlpii())
	118	devoff = XLP2XX_IO_I2C_OFFSET(0);
	119	else
	120	devoff = XLP_IO_I2C0_OFFSET(0);
3c0553e7	121	break;
0d57eba0 J	122	case PIC_SATA_IRQ:
	123	devoff = XLP_IO_SATA_OFFSET(0);
	124	break;
	125	case PIC_GPIO_IRQ:
	126	devoff = XLP_IO_GPIO_OFFSET(0);
	127	break;
	128	case PIC_NAND_IRQ:
	129	devoff = XLP_IO_NAND_OFFSET(0);
	130	break;
	131	case PIC_SPI_IRQ:
	132	devoff = XLP_IO_SPI_OFFSET(0);
	133	break;
65040e22	134	default:
9eac3591 GR	135	if (cpu_is_xlpii()) {
	136	switch (irq) {
	137	/* XLP2XX has three XHCI USB controller */
	138	case PIC_2XX_XHCI_0_IRQ:
	139	devoff = XLP2XX_IO_USB_XHCI0_OFFSET(0);
	140	break;
	141	case PIC_2XX_XHCI_1_IRQ:
	142	devoff = XLP2XX_IO_USB_XHCI1_OFFSET(0);
	143	break;
	144	case PIC_2XX_XHCI_2_IRQ:
	145	devoff = XLP2XX_IO_USB_XHCI2_OFFSET(0);
	146	break;
	147	}
	148	} else {
	149	switch (irq) {
	150	case PIC_EHCI_0_IRQ:
	151	devoff = XLP_IO_USB_EHCI0_OFFSET(0);
	152	break;
	153	case PIC_EHCI_1_IRQ:
	154	devoff = XLP_IO_USB_EHCI1_OFFSET(0);
	155	break;
	156	case PIC_OHCI_0_IRQ:
	157	devoff = XLP_IO_USB_OHCI0_OFFSET(0);
	158	break;
	159	case PIC_OHCI_1_IRQ:
	160	devoff = XLP_IO_USB_OHCI1_OFFSET(0);
	161	break;
	162	case PIC_OHCI_2_IRQ:
	163	devoff = XLP_IO_USB_OHCI2_OFFSET(0);
	164	break;
	165	case PIC_OHCI_3_IRQ:
	166	devoff = XLP_IO_USB_OHCI3_OFFSET(0);
	167	break;
	168	}
	169	}
65040e22	170	}
3c0553e7 J	171
	172	if (devoff != 0) {
	173	pcibase = nlm_pcicfg_base(devoff);
	174	irt = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) & 0xffff;
e5be1fd0 GR	175	/* HW weirdness, I2C IRT entry has to be fixed up */
	176	switch (irq) {
	177	case PIC_I2C_1_IRQ:
	178	irt = irt + 1; break;
	179	case PIC_I2C_2_IRQ:
	180	irt = irt + 2; break;
	181	case PIC_I2C_3_IRQ:
	182	irt = irt + 3; break;
	183	}
c24a8a7a J	184	} else if (irq >= PIC_PCIE_LINK_LEGACY_IRQ(0) &&
c24a8a7a J	185	irq <= PIC_PCIE_LINK_LEGACY_IRQ(3)) {
3c0553e7	186	/* HW bug, PCI IRT entries are bad on early silicon, fix */
c24a8a7a J	187	irt = PIC_IRT_PCIE_LINK_INDEX(irq -
c24a8a7a J	188	PIC_PCIE_LINK_LEGACY_IRQ_BASE);
3c0553e7 J	189	} else {
	190	irt = -1;
	191	}
	192	return irt;
65040e22 J	193	}
65040e22 J	194
0d57eba0 J	195	int nlm_irq_to_irt(int irq)
	196	{
	197	/* return -2 for irqs without 1-1 mapping */
	198	if (irq >= PIC_PCIE_LINK_MSI_IRQ(0) && irq <= PIC_PCIE_LINK_MSI_IRQ(3))
	199	return -2;
	200	if (irq >= PIC_PCIE_MSIX_IRQ(0) && irq <= PIC_PCIE_MSIX_IRQ(3))
	201	return -2;
	202
	203	if (cpu_is_xlp9xx())
	204	return xlp9xx_irq_to_irt(irq);
	205	else
	206	return xlp_irq_to_irt(irq);
	207	}
	208
77ae798f	209	unsigned int nlm_get_core_frequency(int node, int core)
65040e22	210	{
2aa54b20 J	211	unsigned int pll_divf, pll_divr, dfs_div, ext_div;
2aa54b20 J	212	unsigned int rstval, dfsval, denom;
77ae798f	213	uint64_t num, sysbase;
65040e22	214
77ae798f	215	sysbase = nlm_get_node(node)->sysbase;
861c0569 J	216	if (cpu_is_xlp9xx())
	217	rstval = nlm_read_sys_reg(sysbase, SYS_9XX_POWER_ON_RESET_CFG);
	218	else
	219	rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG);
57ceb4b0 GR	220	if (cpu_is_xlpii()) {
	221	num = 1000000ULL * (400 * 3 + 100 * (rstval >> 26));
	222	denom = 3;
	223	} else {
	224	dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE);
	225	pll_divf = ((rstval >> 10) & 0x7f) + 1;
	226	pll_divr = ((rstval >> 8) & 0x3) + 1;
	227	ext_div = ((rstval >> 30) & 0x3) + 1;
	228	dfs_div = ((dfsval >> (core * 4)) & 0xf) + 1;
	229
	230	num = 800000000ULL * pll_divf;
	231	denom = 3 * pll_divr * ext_div * dfs_div;
	232	}
65040e22 J	233	do_div(num, denom);
	234	return (unsigned int)num;
	235	}
2aa54b20	236
57ceb4b0 GR	237	/* Calculate Frequency to the PIC from PLL.
	238	* freq_out = ( ref_freq/2 * (6 + ctrl2[7:0]) + ctrl2[20:8]/2^13 ) /
	239	* ((2^ctrl0[7:5]) * Table(ctrl0[26:24]))
	240	*/
	241	static unsigned int nlm_2xx_get_pic_frequency(int node)
	242	{
	243	u32 ctrl_val0, ctrl_val2, vco_post_div, pll_post_div;
	244	u32 mdiv, fdiv, pll_out_freq_den, reg_select, ref_div, pic_div;
	245	u64 ref_clk, sysbase, pll_out_freq_num, ref_clk_select;
	246
	247	sysbase = nlm_get_node(node)->sysbase;
	248
	249	/* Find ref_clk_base */
	250	ref_clk_select =
	251	(nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG) >> 18) & 0x3;
	252	switch (ref_clk_select) {
	253	case 0:
	254	ref_clk = 200000000ULL;
	255	ref_div = 3;
	256	break;
	257	case 1:
	258	ref_clk = 100000000ULL;
	259	ref_div = 1;
	260	break;
	261	case 2:
	262	ref_clk = 125000000ULL;
	263	ref_div = 1;
	264	break;
	265	case 3:
	266	ref_clk = 400000000ULL;
	267	ref_div = 3;
	268	break;
	269	}
	270
	271	/* Find the clock source PLL device for PIC */
	272	reg_select = (nlm_read_sys_reg(sysbase, SYS_CLK_DEV_SEL) >> 22) & 0x3;
	273	switch (reg_select) {
	274	case 0:
	275	ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0);
	276	ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2);
	277	break;
	278	case 1:
	279	ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(0));
	280	ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(0));
	281	break;
	282	case 2:
	283	ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(1));
	284	ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(1));
	285	break;
	286	case 3:
	287	ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(2));
	288	ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(2));
	289	break;
	290	}
	291
	292	vco_post_div = (ctrl_val0 >> 5) & 0x7;
	293	pll_post_div = (ctrl_val0 >> 24) & 0x7;
	294	mdiv = ctrl_val2 & 0xff;
	295	fdiv = (ctrl_val2 >> 8) & 0xfff;
	296
	297	/* Find PLL post divider value */
	298	switch (pll_post_div) {
	299	case 1:
	300	pll_post_div = 2;
301	break;
302	case 3:
303	pll_post_div = 4;
304	break;
305	case 7:
306	pll_post_div = 8;
307	break;
308	case 6:
309	pll_post_div = 16;
310	break;
311	case 0:
312	default:
313	pll_post_div = 1;
314	break;
315	}
316
317	fdiv = fdiv/(1 << 13);
318	pll_out_freq_num = ((ref_clk >> 1) * (6 + mdiv)) + fdiv;
319	pll_out_freq_den = (1 << vco_post_div) * pll_post_div * 3;
320
321	if (pll_out_freq_den > 0)
322	do_div(pll_out_freq_num, pll_out_freq_den);
323
324	/* PIC post divider, which happens after PLL */
325	pic_div = (nlm_read_sys_reg(sysbase, SYS_CLK_DEV_DIV) >> 22) & 0x3;
326	do_div(pll_out_freq_num, 1 << pic_div);
327
328	return pll_out_freq_num;
329	}
330
331	unsigned int nlm_get_pic_frequency(int node)
332	{
d150cef4 J	333	/* TODO Has to calculate freq as like 2xx */
	334	if (cpu_is_xlp9xx())
	335	return 250000000;
	336
57ceb4b0 GR	337	if (cpu_is_xlpii())
	338	return nlm_2xx_get_pic_frequency(node);
	339	else
	340	return 133333333;
	341	}
	342
2aa54b20 J	343	unsigned int nlm_get_cpu_frequency(void)
2aa54b20 J	344	{
77ae798f	345	return nlm_get_core_frequency(0, 0);
2aa54b20	346	}
a2ba6cd6 J	347
	348	/*
	349	* Fills upto 8 pairs of entries containing the DRAM map of a node
	350	* if n < 0, get dram map for all nodes
	351	*/
	352	int xlp_get_dram_map(int n, uint64_t *dram_map)
	353	{
	354	uint64_t bridgebase, base, lim;
	355	uint32_t val;
e7aa6c66	356	unsigned int barreg, limreg, xlatreg;
a2ba6cd6 J	357	int i, node, rv;
	358
	359	/* Look only at mapping on Node 0, we don't handle crazy configs */
	360	bridgebase = nlm_get_bridge_regbase(0);
	361	rv = 0;
	362	for (i = 0; i < 8; i++) {
e7aa6c66 J	363	if (cpu_is_xlp9xx()) {
	364	barreg = BRIDGE_9XX_DRAM_BAR(i);
	365	limreg = BRIDGE_9XX_DRAM_LIMIT(i);
	366	xlatreg = BRIDGE_9XX_DRAM_NODE_TRANSLN(i);
	367	} else {
	368	barreg = BRIDGE_DRAM_BAR(i);
	369	limreg = BRIDGE_DRAM_LIMIT(i);
	370	xlatreg = BRIDGE_DRAM_NODE_TRANSLN(i);
	371	}
	372	if (n >= 0) {
	373	/* node specified, get node mapping of BAR */
	374	val = nlm_read_bridge_reg(bridgebase, xlatreg);
	375	node = (val >> 1) & 0x3;
	376	if (n != node)
	377	continue;
	378	}
	379	val = nlm_read_bridge_reg(bridgebase, barreg);
a2ba6cd6 J	380	val = (val >> 12) & 0xfffff;
a2ba6cd6 J	381	base = (uint64_t) val << 20;
e7aa6c66	382	val = nlm_read_bridge_reg(bridgebase, limreg);
a2ba6cd6 J	383	val = (val >> 12) & 0xfffff;
	384	if (val == 0) /* BAR not used */
	385	continue;
	386	lim = ((uint64_t)val + 1) << 20;
	387	dram_map[rv] = base;
	388	dram_map[rv + 1] = lim;
	389	rv += 2;
	390	}
	391	return rv;
	392	}