[deliverable/linux.git] / arch / mips / netlogic / xlp / nlm_hal.c

/*
 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
 * reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the NetLogic
 * license below:
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/delay.h>

#include <asm/mipsregs.h>
#include <asm/time.h>

#include <asm/netlogic/common.h>
#include <asm/netlogic/haldefs.h>
#include <asm/netlogic/xlp-hal/iomap.h>
#include <asm/netlogic/xlp-hal/xlp.h>
#include <asm/netlogic/xlp-hal/bridge.h>
#include <asm/netlogic/xlp-hal/pic.h>
#include <asm/netlogic/xlp-hal/sys.h>

/* Main initialization */
void nlm_node_init(int node)
{
	struct nlm_soc_info *nodep;

	nodep = nlm_get_node(node);
	nodep->sysbase = nlm_get_sys_regbase(node);
	nodep->picbase = nlm_get_pic_regbase(node);
	nodep->ebase = read_c0_ebase() & (~((1 << 12) - 1));
	if (cpu_is_xlp9xx())
		nodep->socbus = xlp9xx_get_socbus(node);
	else
		nodep->socbus = 0;
	spin_lock_init(&nodep->piclock);
}

int nlm_irq_to_irt(int irq)
{
	uint64_t pcibase;
	int devoff, irt;

	/* bypass for 9xx */
	if (cpu_is_xlp9xx()) {
		switch (irq) {
		case PIC_9XX_XHCI_0_IRQ:
			return 114;
		case PIC_9XX_XHCI_1_IRQ:
			return 115;
		case PIC_UART_0_IRQ:
			return 133;
		case PIC_UART_1_IRQ:
			return 134;
		case PIC_PCIE_LINK_LEGACY_IRQ(0):
		case PIC_PCIE_LINK_LEGACY_IRQ(1):
		case PIC_PCIE_LINK_LEGACY_IRQ(2):
		case PIC_PCIE_LINK_LEGACY_IRQ(3):
			return 191 + irq - PIC_PCIE_LINK_LEGACY_IRQ_BASE;
		}
		return -1;
	}

	devoff = 0;
	switch (irq) {
	case PIC_UART_0_IRQ:
		devoff = XLP_IO_UART0_OFFSET(0);
		break;
	case PIC_UART_1_IRQ:
		devoff = XLP_IO_UART1_OFFSET(0);
		break;
	case PIC_MMC_IRQ:
		devoff = XLP_IO_SD_OFFSET(0);
		break;
	case PIC_I2C_0_IRQ:	/* I2C will be fixed up */
	case PIC_I2C_1_IRQ:
	case PIC_I2C_2_IRQ:
	case PIC_I2C_3_IRQ:
		if (cpu_is_xlpii())
			devoff = XLP2XX_IO_I2C_OFFSET(0);
		else
			devoff = XLP_IO_I2C0_OFFSET(0);
		break;
	default:
		if (cpu_is_xlpii()) {
			switch (irq) {
				/* XLP2XX has three XHCI USB controller */
			case PIC_2XX_XHCI_0_IRQ:
				devoff = XLP2XX_IO_USB_XHCI0_OFFSET(0);
				break;
			case PIC_2XX_XHCI_1_IRQ:
				devoff = XLP2XX_IO_USB_XHCI1_OFFSET(0);
				break;
			case PIC_2XX_XHCI_2_IRQ:
				devoff = XLP2XX_IO_USB_XHCI2_OFFSET(0);
				break;
			}
		} else {
			switch (irq) {
			case PIC_EHCI_0_IRQ:
				devoff = XLP_IO_USB_EHCI0_OFFSET(0);
				break;
			case PIC_EHCI_1_IRQ:
				devoff = XLP_IO_USB_EHCI1_OFFSET(0);
				break;
			case PIC_OHCI_0_IRQ:
				devoff = XLP_IO_USB_OHCI0_OFFSET(0);
				break;
			case PIC_OHCI_1_IRQ:
				devoff = XLP_IO_USB_OHCI1_OFFSET(0);
				break;
			case PIC_OHCI_2_IRQ:
				devoff = XLP_IO_USB_OHCI2_OFFSET(0);
				break;
			case PIC_OHCI_3_IRQ:
				devoff = XLP_IO_USB_OHCI3_OFFSET(0);
				break;
			}
		}
	}

	if (devoff != 0) {
		pcibase = nlm_pcicfg_base(devoff);
		irt = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) & 0xffff;
		/* HW weirdness, I2C IRT entry has to be fixed up */
		switch (irq) {
		case PIC_I2C_1_IRQ:
			irt = irt + 1; break;
		case PIC_I2C_2_IRQ:
			irt = irt + 2; break;
		case PIC_I2C_3_IRQ:
			irt = irt + 3; break;
		}
	} else if (irq >= PIC_PCIE_LINK_LEGACY_IRQ(0) &&
			irq <= PIC_PCIE_LINK_LEGACY_IRQ(3)) {
		/* HW bug, PCI IRT entries are bad on early silicon, fix */
		irt = PIC_IRT_PCIE_LINK_INDEX(irq -
					PIC_PCIE_LINK_LEGACY_IRQ_BASE);
	} else if (irq >= PIC_PCIE_LINK_MSI_IRQ(0) &&
			irq <= PIC_PCIE_LINK_MSI_IRQ(3)) {
		irt = -2;
	} else if (irq >= PIC_PCIE_MSIX_IRQ(0) &&
			irq <= PIC_PCIE_MSIX_IRQ(3)) {
		irt = -2;
	} else {
		irt = -1;
	}
	return irt;
}

unsigned int nlm_get_core_frequency(int node, int core)
{
	unsigned int pll_divf, pll_divr, dfs_div, ext_div;
	unsigned int rstval, dfsval, denom;
	uint64_t num, sysbase;

	sysbase = nlm_get_node(node)->sysbase;
	if (cpu_is_xlp9xx())
		rstval = nlm_read_sys_reg(sysbase, SYS_9XX_POWER_ON_RESET_CFG);
	else
		rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG);
	if (cpu_is_xlpii()) {
		num = 1000000ULL * (400 * 3 + 100 * (rstval >> 26));
		denom = 3;
	} else {
		dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE);
		pll_divf = ((rstval >> 10) & 0x7f) + 1;
		pll_divr = ((rstval >> 8)  & 0x3) + 1;
		ext_div  = ((rstval >> 30) & 0x3) + 1;
		dfs_div  = ((dfsval >> (core * 4)) & 0xf) + 1;

		num = 800000000ULL * pll_divf;
		denom = 3 * pll_divr * ext_div * dfs_div;
	}
	do_div(num, denom);
	return (unsigned int)num;
}

/* Calculate Frequency to the PIC from PLL.
 * freq_out = ( ref_freq/2 * (6 + ctrl2[7:0]) + ctrl2[20:8]/2^13 ) /
 * ((2^ctrl0[7:5]) * Table(ctrl0[26:24]))
 */
static unsigned int nlm_2xx_get_pic_frequency(int node)
{
	u32 ctrl_val0, ctrl_val2, vco_post_div, pll_post_div;
	u32 mdiv, fdiv, pll_out_freq_den, reg_select, ref_div, pic_div;
	u64 ref_clk, sysbase, pll_out_freq_num, ref_clk_select;

	sysbase = nlm_get_node(node)->sysbase;

	/* Find ref_clk_base */
	ref_clk_select =
		(nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG) >> 18) & 0x3;
	switch (ref_clk_select) {
	case 0:
		ref_clk = 200000000ULL;
		ref_div = 3;
		break;
	case 1:
		ref_clk = 100000000ULL;
		ref_div = 1;
		break;
	case 2:
		ref_clk = 125000000ULL;
		ref_div = 1;
		break;
	case 3:
		ref_clk = 400000000ULL;
		ref_div = 3;
		break;
	}

	/* Find the clock source PLL device for PIC */
	reg_select = (nlm_read_sys_reg(sysbase, SYS_CLK_DEV_SEL) >> 22) & 0x3;
	switch (reg_select) {
	case 0:
		ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0);
		ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2);
		break;
	case 1:
		ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(0));
		ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(0));
		break;
	case 2:
		ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(1));
		ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(1));
		break;
	case 3:
		ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(2));
		ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(2));
		break;
	}

	vco_post_div = (ctrl_val0 >> 5) & 0x7;
	pll_post_div = (ctrl_val0 >> 24) & 0x7;
	mdiv = ctrl_val2 & 0xff;
	fdiv = (ctrl_val2 >> 8) & 0xfff;

	/* Find PLL post divider value */
	switch (pll_post_div) {
	case 1:
		pll_post_div = 2;
		break;
	case 3:
		pll_post_div = 4;
		break;
	case 7:
		pll_post_div = 8;
		break;
	case 6:
		pll_post_div = 16;
		break;
	case 0:
	default:
		pll_post_div = 1;
		break;
	}

	fdiv = fdiv/(1 << 13);
	pll_out_freq_num = ((ref_clk >> 1) * (6 + mdiv)) + fdiv;
	pll_out_freq_den = (1 << vco_post_div) * pll_post_div * 3;

	if (pll_out_freq_den > 0)
		do_div(pll_out_freq_num, pll_out_freq_den);

	/* PIC post divider, which happens after PLL */
	pic_div = (nlm_read_sys_reg(sysbase, SYS_CLK_DEV_DIV) >> 22) & 0x3;
	do_div(pll_out_freq_num, 1 << pic_div);

	return pll_out_freq_num;
}

unsigned int nlm_get_pic_frequency(int node)
{
	/* TODO Has to calculate freq as like 2xx */
	if (cpu_is_xlp9xx())
		return 250000000;

	if (cpu_is_xlpii())
		return nlm_2xx_get_pic_frequency(node);
	else
		return 133333333;
}

unsigned int nlm_get_cpu_frequency(void)
{
	return nlm_get_core_frequency(0, 0);
}

/*
 * Fills upto 8 pairs of entries containing the DRAM map of a node
 * if n < 0, get dram map for all nodes
 */
int xlp_get_dram_map(int n, uint64_t *dram_map)
{
	uint64_t bridgebase, base, lim;
	uint32_t val;
	unsigned int barreg, limreg, xlatreg;
	int i, node, rv;

	/* Look only at mapping on Node 0, we don't handle crazy configs */
	bridgebase = nlm_get_bridge_regbase(0);
	rv = 0;
	for (i = 0; i < 8; i++) {
		if (cpu_is_xlp9xx()) {
			barreg = BRIDGE_9XX_DRAM_BAR(i);
			limreg = BRIDGE_9XX_DRAM_LIMIT(i);
			xlatreg = BRIDGE_9XX_DRAM_NODE_TRANSLN(i);
		} else {
			barreg = BRIDGE_DRAM_BAR(i);
			limreg = BRIDGE_DRAM_LIMIT(i);
			xlatreg = BRIDGE_DRAM_NODE_TRANSLN(i);
		}
		if (n >= 0) {
			/* node specified, get node mapping of BAR */
			val = nlm_read_bridge_reg(bridgebase, xlatreg);
			node = (val >> 1) & 0x3;
			if (n != node)
				continue;
		}
		val = nlm_read_bridge_reg(bridgebase, barreg);
		val = (val >>  12) & 0xfffff;
		base = (uint64_t) val << 20;
		val = nlm_read_bridge_reg(bridgebase, limreg);
		val = (val >>  12) & 0xfffff;
		if (val == 0)   /* BAR not used */
			continue;
		lim = ((uint64_t)val + 1) << 20;
		dram_map[rv] = base;
		dram_map[rv + 1] = lim;
		rv += 2;
	}
	return rv;
}
Commit	Line	Data
65040e22 J	1	/*
	2	* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
	3	* reserved.
	4	*
	5	* This software is available to you under a choice of one of two
	6	* licenses. You may choose to be licensed under the terms of the GNU
	7	* General Public License (GPL) Version 2, available from the file
	8	* COPYING in the main directory of this source tree, or the NetLogic
	9	* license below:
	10	*
	11	* Redistribution and use in source and binary forms, with or without
	12	* modification, are permitted provided that the following conditions
	13	* are met:
	14	*
	15	* 1. Redistributions of source code must retain the above copyright
	16	* notice, this list of conditions and the following disclaimer.
	17	* 2. Redistributions in binary form must reproduce the above copyright
	18	* notice, this list of conditions and the following disclaimer in
	19	* the documentation and/or other materials provided with the
	20	* distribution.
	21	*
	22	* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
	23	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	24	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	25	* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	27	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	28	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
	29	* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
	30	* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
	31	* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
	32	* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	33	*/
	34
	35	#include <linux/types.h>
	36	#include <linux/kernel.h>
	37	#include <linux/mm.h>
	38	#include <linux/delay.h>
	39
	40	#include <asm/mipsregs.h>
	41	#include <asm/time.h>
	42
77ae798f	43	#include <asm/netlogic/common.h>
65040e22 J	44	#include <asm/netlogic/haldefs.h>
	45	#include <asm/netlogic/xlp-hal/iomap.h>
	46	#include <asm/netlogic/xlp-hal/xlp.h>
a2ba6cd6	47	#include <asm/netlogic/xlp-hal/bridge.h>
65040e22 J	48	#include <asm/netlogic/xlp-hal/pic.h>
	49	#include <asm/netlogic/xlp-hal/sys.h>
	50
65040e22	51	/* Main initialization */
77ae798f	52	void nlm_node_init(int node)
65040e22	53	{
77ae798f J	54	struct nlm_soc_info *nodep;
	55
	56	nodep = nlm_get_node(node);
	57	nodep->sysbase = nlm_get_sys_regbase(node);
	58	nodep->picbase = nlm_get_pic_regbase(node);
	59	nodep->ebase = read_c0_ebase() & (~((1 << 12) - 1));
5513c760 J	60	if (cpu_is_xlp9xx())
	61	nodep->socbus = xlp9xx_get_socbus(node);
	62	else
	63	nodep->socbus = 0;
77ae798f	64	spin_lock_init(&nodep->piclock);
65040e22 J	65	}
	66
	67	int nlm_irq_to_irt(int irq)
	68	{
3c0553e7 J	69	uint64_t pcibase;
3c0553e7 J	70	int devoff, irt;
65040e22	71
d150cef4 J	72	/* bypass for 9xx */
	73	if (cpu_is_xlp9xx()) {
	74	switch (irq) {
3262b21e GR	75	case PIC_9XX_XHCI_0_IRQ:
	76	return 114;
	77	case PIC_9XX_XHCI_1_IRQ:
	78	return 115;
d150cef4 J	79	case PIC_UART_0_IRQ:
	80	return 133;
	81	case PIC_UART_1_IRQ:
	82	return 134;
b6ba1c52 J	83	case PIC_PCIE_LINK_LEGACY_IRQ(0):
	84	case PIC_PCIE_LINK_LEGACY_IRQ(1):
	85	case PIC_PCIE_LINK_LEGACY_IRQ(2):
	86	case PIC_PCIE_LINK_LEGACY_IRQ(3):
	87	return 191 + irq - PIC_PCIE_LINK_LEGACY_IRQ_BASE;
d150cef4 J	88	}
	89	return -1;
	90	}
	91
9eac3591	92	devoff = 0;
65040e22 J	93	switch (irq) {
65040e22 J	94	case PIC_UART_0_IRQ:
3c0553e7 J	95	devoff = XLP_IO_UART0_OFFSET(0);
3c0553e7 J	96	break;
65040e22	97	case PIC_UART_1_IRQ:
3c0553e7 J	98	devoff = XLP_IO_UART1_OFFSET(0);
3c0553e7 J	99	break;
57d7cdb6	100	case PIC_MMC_IRQ:
3c0553e7 J	101	devoff = XLP_IO_SD_OFFSET(0);
3c0553e7 J	102	break;
e5be1fd0	103	case PIC_I2C_0_IRQ: /* I2C will be fixed up */
57d7cdb6	104	case PIC_I2C_1_IRQ:
e5be1fd0 GR	105	case PIC_I2C_2_IRQ:
	106	case PIC_I2C_3_IRQ:
	107	if (cpu_is_xlpii())
	108	devoff = XLP2XX_IO_I2C_OFFSET(0);
	109	else
	110	devoff = XLP_IO_I2C0_OFFSET(0);
3c0553e7	111	break;
65040e22	112	default:
9eac3591 GR	113	if (cpu_is_xlpii()) {
	114	switch (irq) {
	115	/* XLP2XX has three XHCI USB controller */
	116	case PIC_2XX_XHCI_0_IRQ:
	117	devoff = XLP2XX_IO_USB_XHCI0_OFFSET(0);
	118	break;
	119	case PIC_2XX_XHCI_1_IRQ:
	120	devoff = XLP2XX_IO_USB_XHCI1_OFFSET(0);
	121	break;
	122	case PIC_2XX_XHCI_2_IRQ:
	123	devoff = XLP2XX_IO_USB_XHCI2_OFFSET(0);
	124	break;
	125	}
	126	} else {
	127	switch (irq) {
	128	case PIC_EHCI_0_IRQ:
	129	devoff = XLP_IO_USB_EHCI0_OFFSET(0);
	130	break;
	131	case PIC_EHCI_1_IRQ:
	132	devoff = XLP_IO_USB_EHCI1_OFFSET(0);
	133	break;
	134	case PIC_OHCI_0_IRQ:
	135	devoff = XLP_IO_USB_OHCI0_OFFSET(0);
	136	break;
	137	case PIC_OHCI_1_IRQ:
	138	devoff = XLP_IO_USB_OHCI1_OFFSET(0);
	139	break;
	140	case PIC_OHCI_2_IRQ:
	141	devoff = XLP_IO_USB_OHCI2_OFFSET(0);
	142	break;
	143	case PIC_OHCI_3_IRQ:
	144	devoff = XLP_IO_USB_OHCI3_OFFSET(0);
	145	break;
	146	}
	147	}
65040e22	148	}
3c0553e7 J	149
	150	if (devoff != 0) {
	151	pcibase = nlm_pcicfg_base(devoff);
	152	irt = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) & 0xffff;
e5be1fd0 GR	153	/* HW weirdness, I2C IRT entry has to be fixed up */
	154	switch (irq) {
	155	case PIC_I2C_1_IRQ:
	156	irt = irt + 1; break;
	157	case PIC_I2C_2_IRQ:
	158	irt = irt + 2; break;
	159	case PIC_I2C_3_IRQ:
	160	irt = irt + 3; break;
	161	}
c24a8a7a J	162	} else if (irq >= PIC_PCIE_LINK_LEGACY_IRQ(0) &&
c24a8a7a J	163	irq <= PIC_PCIE_LINK_LEGACY_IRQ(3)) {
3c0553e7	164	/* HW bug, PCI IRT entries are bad on early silicon, fix */
c24a8a7a J	165	irt = PIC_IRT_PCIE_LINK_INDEX(irq -
	166	PIC_PCIE_LINK_LEGACY_IRQ_BASE);
	167	} else if (irq >= PIC_PCIE_LINK_MSI_IRQ(0) &&
	168	irq <= PIC_PCIE_LINK_MSI_IRQ(3)) {
	169	irt = -2;
	170	} else if (irq >= PIC_PCIE_MSIX_IRQ(0) &&
	171	irq <= PIC_PCIE_MSIX_IRQ(3)) {
	172	irt = -2;
3c0553e7 J	173	} else {
	174	irt = -1;
	175	}
	176	return irt;
65040e22 J	177	}
65040e22 J	178
77ae798f	179	unsigned int nlm_get_core_frequency(int node, int core)
65040e22	180	{
2aa54b20 J	181	unsigned int pll_divf, pll_divr, dfs_div, ext_div;
2aa54b20 J	182	unsigned int rstval, dfsval, denom;
77ae798f	183	uint64_t num, sysbase;
65040e22	184
77ae798f	185	sysbase = nlm_get_node(node)->sysbase;
861c0569 J	186	if (cpu_is_xlp9xx())
	187	rstval = nlm_read_sys_reg(sysbase, SYS_9XX_POWER_ON_RESET_CFG);
	188	else
	189	rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG);
57ceb4b0 GR	190	if (cpu_is_xlpii()) {
	191	num = 1000000ULL * (400 * 3 + 100 * (rstval >> 26));
	192	denom = 3;
	193	} else {
	194	dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE);
	195	pll_divf = ((rstval >> 10) & 0x7f) + 1;
	196	pll_divr = ((rstval >> 8) & 0x3) + 1;
	197	ext_div = ((rstval >> 30) & 0x3) + 1;
	198	dfs_div = ((dfsval >> (core * 4)) & 0xf) + 1;
	199
	200	num = 800000000ULL * pll_divf;
	201	denom = 3 * pll_divr * ext_div * dfs_div;
	202	}
65040e22 J	203	do_div(num, denom);
	204	return (unsigned int)num;
	205	}
2aa54b20	206
57ceb4b0 GR	207	/* Calculate Frequency to the PIC from PLL.
	208	* freq_out = ( ref_freq/2 * (6 + ctrl2[7:0]) + ctrl2[20:8]/2^13 ) /
	209	* ((2^ctrl0[7:5]) * Table(ctrl0[26:24]))
	210	*/
	211	static unsigned int nlm_2xx_get_pic_frequency(int node)
	212	{
	213	u32 ctrl_val0, ctrl_val2, vco_post_div, pll_post_div;
	214	u32 mdiv, fdiv, pll_out_freq_den, reg_select, ref_div, pic_div;
	215	u64 ref_clk, sysbase, pll_out_freq_num, ref_clk_select;
	216
	217	sysbase = nlm_get_node(node)->sysbase;
	218
	219	/* Find ref_clk_base */
	220	ref_clk_select =
	221	(nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG) >> 18) & 0x3;
	222	switch (ref_clk_select) {
	223	case 0:
	224	ref_clk = 200000000ULL;
	225	ref_div = 3;
	226	break;
	227	case 1:
	228	ref_clk = 100000000ULL;
	229	ref_div = 1;
	230	break;
	231	case 2:
	232	ref_clk = 125000000ULL;
	233	ref_div = 1;
	234	break;
	235	case 3:
	236	ref_clk = 400000000ULL;
	237	ref_div = 3;
	238	break;
	239	}
	240
	241	/* Find the clock source PLL device for PIC */
	242	reg_select = (nlm_read_sys_reg(sysbase, SYS_CLK_DEV_SEL) >> 22) & 0x3;
	243	switch (reg_select) {
	244	case 0:
	245	ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0);
	246	ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2);
	247	break;
	248	case 1:
	249	ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(0));
	250	ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(0));
	251	break;
	252	case 2:
	253	ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(1));
	254	ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(1));
	255	break;
	256	case 3:
	257	ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(2));
	258	ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(2));
	259	break;
	260	}
	261
	262	vco_post_div = (ctrl_val0 >> 5) & 0x7;
	263	pll_post_div = (ctrl_val0 >> 24) & 0x7;
	264	mdiv = ctrl_val2 & 0xff;
	265	fdiv = (ctrl_val2 >> 8) & 0xfff;
	266
	267	/* Find PLL post divider value */
	268	switch (pll_post_div) {
	269	case 1:
	270	pll_post_div = 2;
271	break;
272	case 3:
273	pll_post_div = 4;
274	break;
275	case 7:
276	pll_post_div = 8;
277	break;
278	case 6:
279	pll_post_div = 16;
280	break;
281	case 0:
282	default:
283	pll_post_div = 1;
284	break;
285	}
286
287	fdiv = fdiv/(1 << 13);
288	pll_out_freq_num = ((ref_clk >> 1) * (6 + mdiv)) + fdiv;
289	pll_out_freq_den = (1 << vco_post_div) * pll_post_div * 3;
290
291	if (pll_out_freq_den > 0)
292	do_div(pll_out_freq_num, pll_out_freq_den);
293
294	/* PIC post divider, which happens after PLL */
295	pic_div = (nlm_read_sys_reg(sysbase, SYS_CLK_DEV_DIV) >> 22) & 0x3;
296	do_div(pll_out_freq_num, 1 << pic_div);
297
298	return pll_out_freq_num;
299	}
300
301	unsigned int nlm_get_pic_frequency(int node)
302	{
d150cef4 J	303	/* TODO Has to calculate freq as like 2xx */
	304	if (cpu_is_xlp9xx())
	305	return 250000000;
	306
57ceb4b0 GR	307	if (cpu_is_xlpii())
	308	return nlm_2xx_get_pic_frequency(node);
	309	else
	310	return 133333333;
	311	}
	312
2aa54b20 J	313	unsigned int nlm_get_cpu_frequency(void)
2aa54b20 J	314	{
77ae798f	315	return nlm_get_core_frequency(0, 0);
2aa54b20	316	}
a2ba6cd6 J	317
	318	/*
	319	* Fills upto 8 pairs of entries containing the DRAM map of a node
	320	* if n < 0, get dram map for all nodes
	321	*/
	322	int xlp_get_dram_map(int n, uint64_t *dram_map)
	323	{
	324	uint64_t bridgebase, base, lim;
	325	uint32_t val;
e7aa6c66	326	unsigned int barreg, limreg, xlatreg;
a2ba6cd6 J	327	int i, node, rv;
	328
	329	/* Look only at mapping on Node 0, we don't handle crazy configs */
	330	bridgebase = nlm_get_bridge_regbase(0);
	331	rv = 0;
	332	for (i = 0; i < 8; i++) {
e7aa6c66 J	333	if (cpu_is_xlp9xx()) {
	334	barreg = BRIDGE_9XX_DRAM_BAR(i);
	335	limreg = BRIDGE_9XX_DRAM_LIMIT(i);
	336	xlatreg = BRIDGE_9XX_DRAM_NODE_TRANSLN(i);
	337	} else {
	338	barreg = BRIDGE_DRAM_BAR(i);
	339	limreg = BRIDGE_DRAM_LIMIT(i);
	340	xlatreg = BRIDGE_DRAM_NODE_TRANSLN(i);
	341	}
	342	if (n >= 0) {
	343	/* node specified, get node mapping of BAR */
	344	val = nlm_read_bridge_reg(bridgebase, xlatreg);
	345	node = (val >> 1) & 0x3;
	346	if (n != node)
	347	continue;
	348	}
	349	val = nlm_read_bridge_reg(bridgebase, barreg);
a2ba6cd6 J	350	val = (val >> 12) & 0xfffff;
a2ba6cd6 J	351	base = (uint64_t) val << 20;
e7aa6c66	352	val = nlm_read_bridge_reg(bridgebase, limreg);
a2ba6cd6 J	353	val = (val >> 12) & 0xfffff;
	354	if (val == 0) /* BAR not used */
	355	continue;
	356	lim = ((uint64_t)val + 1) << 20;
	357	dram_map[rv] = base;
	358	dram_map[rv + 1] = lim;
	359	rv += 2;
	360	}
	361	return rv;
	362	}