[deliverable/linux.git] / arch / mips / oprofile / op_model_loongson2.c

/*
 * Loongson2 performance counter driver for oprofile
 *
 * Copyright (C) 2009 Lemote Inc.
 * Author: Yanhua <yanh@lemote.com>
 * Author: Wu Zhangjin <wuzhangjin@gmail.com>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/init.h>
#include <linux/oprofile.h>
#include <linux/interrupt.h>

#include <loongson.h>			/* LOONGSON2_PERFCNT_IRQ */
#include "op_impl.h"

#define LOONGSON2_CPU_TYPE	"mips/loongson2"

#define LOONGSON2_PERFCNT_OVERFLOW		(1ULL   << 31)

#define LOONGSON2_PERFCTRL_EXL			(1UL	<<  0)
#define LOONGSON2_PERFCTRL_KERNEL		(1UL    <<  1)
#define LOONGSON2_PERFCTRL_SUPERVISOR		(1UL    <<  2)
#define LOONGSON2_PERFCTRL_USER			(1UL    <<  3)
#define LOONGSON2_PERFCTRL_ENABLE		(1UL    <<  4)
#define LOONGSON2_PERFCTRL_EVENT(idx, event) \
	(((event) & 0x0f) << ((idx) ? 9 : 5))

#define read_c0_perfctrl() __read_64bit_c0_register($24, 0)
#define write_c0_perfctrl(val) __write_64bit_c0_register($24, 0, val)
#define read_c0_perfcnt() __read_64bit_c0_register($25, 0)
#define write_c0_perfcnt(val) __write_64bit_c0_register($25, 0, val)

static struct loongson2_register_config {
	unsigned int ctrl;
	unsigned long long reset_counter1;
	unsigned long long reset_counter2;
	int cnt1_enabled, cnt2_enabled;
} reg;

static char *oprofid = "LoongsonPerf";
static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id);

static void loongson2_reg_setup(struct op_counter_config *cfg)
{
	unsigned int ctrl = 0;

	reg.reset_counter1 = 0;
	reg.reset_counter2 = 0;

	/*
	 * Compute the performance counter ctrl word.
	 * For now, count kernel and user mode.
	 */
	if (cfg[0].enabled) {
		ctrl |= LOONGSON2_PERFCTRL_EVENT(0, cfg[0].event);
		reg.reset_counter1 = 0x80000000ULL - cfg[0].count;
	}

	if (cfg[1].enabled) {
		ctrl |= LOONGSON2_PERFCTRL_EVENT(1, cfg[1].event);
		reg.reset_counter2 = 0x80000000ULL - cfg[1].count;
	}

	if (cfg[0].enabled || cfg[1].enabled) {
		ctrl |= LOONGSON2_PERFCTRL_EXL | LOONGSON2_PERFCTRL_ENABLE;
		if (cfg[0].kernel || cfg[1].kernel)
			ctrl |= LOONGSON2_PERFCTRL_KERNEL;
		if (cfg[0].user || cfg[1].user)
			ctrl |= LOONGSON2_PERFCTRL_USER;
	}

	reg.ctrl = ctrl;

	reg.cnt1_enabled = cfg[0].enabled;
	reg.cnt2_enabled = cfg[1].enabled;
}

static void loongson2_cpu_setup(void *args)
{
	write_c0_perfcnt((reg.reset_counter2 << 32) | reg.reset_counter1);
}

static void loongson2_cpu_start(void *args)
{
	/* Start all counters on current CPU */
	if (reg.cnt1_enabled || reg.cnt2_enabled)
		write_c0_perfctrl(reg.ctrl);
}

static void loongson2_cpu_stop(void *args)
{
	/* Stop all counters on current CPU */
	write_c0_perfctrl(0);
	memset(&reg, 0, sizeof(reg));
}

static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id)
{
	uint64_t counter, counter1, counter2;
	struct pt_regs *regs = get_irq_regs();
	int enabled;

	/* Check whether the irq belongs to me */
	enabled = read_c0_perfctrl() & LOONGSON2_PERFCTRL_ENABLE;
	if (!enabled)
		return IRQ_NONE;
	enabled = reg.cnt1_enabled | reg.cnt2_enabled;
	if (!enabled)
		return IRQ_NONE;

	counter = read_c0_perfcnt();
	counter1 = counter & 0xffffffff;
	counter2 = counter >> 32;

	if (counter1 & LOONGSON2_PERFCNT_OVERFLOW) {
		if (reg.cnt1_enabled)
			oprofile_add_sample(regs, 0);
		counter1 = reg.reset_counter1;
	}
	if (counter2 & LOONGSON2_PERFCNT_OVERFLOW) {
		if (reg.cnt2_enabled)
			oprofile_add_sample(regs, 1);
		counter2 = reg.reset_counter2;
	}

	write_c0_perfcnt((counter2 << 32) | counter1);

	return IRQ_HANDLED;
}

static int __init loongson2_init(void)
{
	return request_irq(LOONGSON2_PERFCNT_IRQ, loongson2_perfcount_handler,
			   IRQF_SHARED, "Perfcounter", oprofid);
}

static void loongson2_exit(void)
{
	write_c0_perfctrl(0);
	free_irq(LOONGSON2_PERFCNT_IRQ, oprofid);
}

struct op_mips_model op_model_loongson2_ops = {
	.reg_setup = loongson2_reg_setup,
	.cpu_setup = loongson2_cpu_setup,
	.init = loongson2_init,
	.exit = loongson2_exit,
	.cpu_start = loongson2_cpu_start,
	.cpu_stop = loongson2_cpu_stop,
	.cpu_type = LOONGSON2_CPU_TYPE,
	.num_counters = 2
};
Commit	Line	Data
67b35e5d WZ	1	/*
	2	* Loongson2 performance counter driver for oprofile
	3	*
937893cf	4	* Copyright (C) 2009 Lemote Inc.
67b35e5d	5	* Author: Yanhua <yanh@lemote.com>
f7a904df	6	* Author: Wu Zhangjin <wuzhangjin@gmail.com>
67b35e5d WZ	7	*
	8	* This file is subject to the terms and conditions of the GNU General Public
	9	* License. See the file "COPYING" in the main directory of this archive
	10	* for more details.
67b35e5d WZ	11	*/
	12	#include <linux/init.h>
	13	#include <linux/oprofile.h>
	14	#include <linux/interrupt.h>
	15
	16	#include <loongson.h> /* LOONGSON2_PERFCNT_IRQ */
	17	#include "op_impl.h"
	18
55f4e1d4	19	#define LOONGSON2_CPU_TYPE "mips/loongson2"
67b35e5d	20
852151bd WZ	21	#define LOONGSON2_PERFCNT_OVERFLOW (1ULL << 31)
	22
	23	#define LOONGSON2_PERFCTRL_EXL (1UL << 0)
	24	#define LOONGSON2_PERFCTRL_KERNEL (1UL << 1)
	25	#define LOONGSON2_PERFCTRL_SUPERVISOR (1UL << 2)
	26	#define LOONGSON2_PERFCTRL_USER (1UL << 3)
	27	#define LOONGSON2_PERFCTRL_ENABLE (1UL << 4)
86e5a520 WZ	28	#define LOONGSON2_PERFCTRL_EVENT(idx, event) \
86e5a520 WZ	29	(((event) & 0x0f) << ((idx) ? 9 : 5))
67b35e5d	30
67b35e5d WZ	31	#define read_c0_perfctrl() __read_64bit_c0_register($24, 0)
	32	#define write_c0_perfctrl(val) __write_64bit_c0_register($24, 0, val)
	33	#define read_c0_perfcnt() __read_64bit_c0_register($25, 0)
	34	#define write_c0_perfcnt(val) __write_64bit_c0_register($25, 0, val)
	35
	36	static struct loongson2_register_config {
	37	unsigned int ctrl;
	38	unsigned long long reset_counter1;
	39	unsigned long long reset_counter2;
8813d33e	40	int cnt1_enabled, cnt2_enabled;
67b35e5d WZ	41	} reg;
67b35e5d WZ	42
67b35e5d WZ	43	static char *oprofid = "LoongsonPerf";
67b35e5d WZ	44	static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id);
67b35e5d WZ	45
	46	static void loongson2_reg_setup(struct op_counter_config *cfg)
	47	{
	48	unsigned int ctrl = 0;
	49
	50	reg.reset_counter1 = 0;
	51	reg.reset_counter2 = 0;
893556e6 WZ	52
	53	/*
	54	* Compute the performance counter ctrl word.
	55	* For now, count kernel and user mode.
	56	*/
67b35e5d	57	if (cfg[0].enabled) {
86e5a520	58	ctrl \|= LOONGSON2_PERFCTRL_EVENT(0, cfg[0].event);
67b35e5d WZ	59	reg.reset_counter1 = 0x80000000ULL - cfg[0].count;
	60	}
	61
	62	if (cfg[1].enabled) {
86e5a520	63	ctrl \|= LOONGSON2_PERFCTRL_EVENT(1, cfg[1].event);
c838abc5	64	reg.reset_counter2 = 0x80000000ULL - cfg[1].count;
67b35e5d WZ	65	}
	66
	67	if (cfg[0].enabled \|\| cfg[1].enabled) {
852151bd	68	ctrl \|= LOONGSON2_PERFCTRL_EXL \| LOONGSON2_PERFCTRL_ENABLE;
67b35e5d	69	if (cfg[0].kernel \|\| cfg[1].kernel)
852151bd	70	ctrl \|= LOONGSON2_PERFCTRL_KERNEL;
67b35e5d	71	if (cfg[0].user \|\| cfg[1].user)
852151bd	72	ctrl \|= LOONGSON2_PERFCTRL_USER;
67b35e5d WZ	73	}
	74
	75	reg.ctrl = ctrl;
	76
8813d33e UKK	77	reg.cnt1_enabled = cfg[0].enabled;
8813d33e UKK	78	reg.cnt2_enabled = cfg[1].enabled;
67b35e5d WZ	79	}
67b35e5d WZ	80
67b35e5d WZ	81	static void loongson2_cpu_setup(void *args)
67b35e5d WZ	82	{
6d8c2873	83	write_c0_perfcnt((reg.reset_counter2 << 32) \| reg.reset_counter1);
67b35e5d WZ	84	}
	85
	86	static void loongson2_cpu_start(void *args)
	87	{
	88	/* Start all counters on current CPU */
8813d33e	89	if (reg.cnt1_enabled \|\| reg.cnt2_enabled)
67b35e5d WZ	90	write_c0_perfctrl(reg.ctrl);
	91	}
	92
	93	static void loongson2_cpu_stop(void *args)
	94	{
	95	/* Stop all counters on current CPU */
	96	write_c0_perfctrl(0);
	97	memset(&reg, 0, sizeof(reg));
	98	}
	99
	100	static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id)
	101	{
	102	uint64_t counter, counter1, counter2;
	103	struct pt_regs *regs = get_irq_regs();
	104	int enabled;
67b35e5d	105
67b35e5d	106	/* Check whether the irq belongs to me */
852151bd	107	enabled = read_c0_perfctrl() & LOONGSON2_PERFCTRL_ENABLE;
937893cf WZ	108	if (!enabled)
937893cf WZ	109	return IRQ_NONE;
8813d33e	110	enabled = reg.cnt1_enabled \| reg.cnt2_enabled;
67b35e5d WZ	111	if (!enabled)
	112	return IRQ_NONE;
	113
	114	counter = read_c0_perfcnt();
	115	counter1 = counter & 0xffffffff;
	116	counter2 = counter >> 32;
	117
67b35e5d	118	if (counter1 & LOONGSON2_PERFCNT_OVERFLOW) {
8813d33e	119	if (reg.cnt1_enabled)
67b35e5d WZ	120	oprofile_add_sample(regs, 0);
	121	counter1 = reg.reset_counter1;
	122	}
	123	if (counter2 & LOONGSON2_PERFCNT_OVERFLOW) {
8813d33e	124	if (reg.cnt2_enabled)
67b35e5d WZ	125	oprofile_add_sample(regs, 1);
	126	counter2 = reg.reset_counter2;
	127	}
	128
67b35e5d WZ	129	write_c0_perfcnt((counter2 << 32) \| counter1);
	130
	131	return IRQ_HANDLED;
	132	}
	133
	134	static int __init loongson2_init(void)
	135	{
	136	return request_irq(LOONGSON2_PERFCNT_IRQ, loongson2_perfcount_handler,
	137	IRQF_SHARED, "Perfcounter", oprofid);
	138	}
	139
	140	static void loongson2_exit(void)
	141	{
	142	write_c0_perfctrl(0);
	143	free_irq(LOONGSON2_PERFCNT_IRQ, oprofid);
	144	}
	145
	146	struct op_mips_model op_model_loongson2_ops = {
	147	.reg_setup = loongson2_reg_setup,
	148	.cpu_setup = loongson2_cpu_setup,
	149	.init = loongson2_init,
	150	.exit = loongson2_exit,
	151	.cpu_start = loongson2_cpu_start,
	152	.cpu_stop = loongson2_cpu_stop,
	153	.cpu_type = LOONGSON2_CPU_TYPE,
	154	.num_counters = 2
	155	};