[deliverable/linux.git] / arch / mips / oprofile / op_model_mipsxx.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2004, 2005 by Ralf Baechle
 * Copyright (C) 2005 by MIPS Technologies, Inc.
 */
#include <linux/oprofile.h>
#include <linux/interrupt.h>
#include <linux/smp.h>

#include "op_impl.h"

#define M_PERFCTL_EXL			(1UL      <<  0)
#define M_PERFCTL_KERNEL		(1UL      <<  1)
#define M_PERFCTL_SUPERVISOR		(1UL      <<  2)
#define M_PERFCTL_USER			(1UL      <<  3)
#define M_PERFCTL_INTERRUPT_ENABLE	(1UL      <<  4)
#define M_PERFCTL_EVENT(event)		((event)  << 5)
#define M_PERFCTL_VPEID(vpe)		((vpe)    << 16)
#define M_PERFCTL_MT_EN(filter)		((filter) << 20)
#define    M_TC_EN_ALL			M_PERFCTL_MT_EN(0)
#define    M_TC_EN_VPE			M_PERFCTL_MT_EN(1)
#define    M_TC_EN_TC			M_PERFCTL_MT_EN(2)
#define M_PERFCTL_TCID(tcid)		((tcid)   << 22)
#define M_PERFCTL_WIDE			(1UL      << 30)
#define M_PERFCTL_MORE			(1UL      << 31)

#define M_COUNTER_OVERFLOW		(1UL      << 31)

#ifdef CONFIG_MIPS_MT_SMP
#define WHAT	(M_TC_EN_VPE | M_PERFCTL_VPEID(smp_processor_id()))
#else
#define WHAT	0
#endif

#define __define_perf_accessors(r, n, np)				\
									\
static inline unsigned int r_c0_ ## r ## n(void)			\
{									\
	unsigned int cpu = smp_processor_id();				\
									\
	switch (cpu) {							\
	case 0:								\
		return read_c0_ ## r ## n();				\
	case 1:								\
		return read_c0_ ## r ## np();				\
	default:							\
		BUG();							\
	}								\
	return 0;							\
}									\
									\
static inline void w_c0_ ## r ## n(unsigned int value)			\
{									\
	unsigned int cpu = smp_processor_id();				\
									\
	switch (cpu) {							\
	case 0:								\
		write_c0_ ## r ## n(value);				\
		return;							\
	case 1:								\
		write_c0_ ## r ## np(value);				\
		return;							\
	default:							\
		BUG();							\
	}								\
	return;								\
}									\

__define_perf_accessors(perfcntr, 0, 2)
__define_perf_accessors(perfcntr, 1, 3)
__define_perf_accessors(perfcntr, 2, 2)
__define_perf_accessors(perfcntr, 3, 2)

__define_perf_accessors(perfctrl, 0, 2)
__define_perf_accessors(perfctrl, 1, 3)
__define_perf_accessors(perfctrl, 2, 2)
__define_perf_accessors(perfctrl, 3, 2)

struct op_mips_model op_model_mipsxx_ops;

static struct mipsxx_register_config {
	unsigned int control[4];
	unsigned int counter[4];
} reg;

/* Compute all of the registers in preparation for enabling profiling.  */

static void mipsxx_reg_setup(struct op_counter_config *ctr)
{
	unsigned int counters = op_model_mipsxx_ops.num_counters;
	int i;

	/* Compute the performance counter control word.  */
	/* For now count kernel and user mode */
	for (i = 0; i < counters; i++) {
		reg.control[i] = 0;
		reg.counter[i] = 0;

		if (!ctr[i].enabled)
			continue;

		reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) |
		                 M_PERFCTL_INTERRUPT_ENABLE;
		if (ctr[i].kernel)
			reg.control[i] |= M_PERFCTL_KERNEL;
		if (ctr[i].user)
			reg.control[i] |= M_PERFCTL_USER;
		if (ctr[i].exl)
			reg.control[i] |= M_PERFCTL_EXL;
		reg.counter[i] = 0x80000000 - ctr[i].count;
	}
}

/* Program all of the registers in preparation for enabling profiling.  */

static void mipsxx_cpu_setup (void *args)
{
	unsigned int counters = op_model_mipsxx_ops.num_counters;

	switch (counters) {
	case 4:
		w_c0_perfctrl3(0);
		w_c0_perfcntr3(reg.counter[3]);
	case 3:
		w_c0_perfctrl2(0);
		w_c0_perfcntr2(reg.counter[2]);
	case 2:
		w_c0_perfctrl1(0);
		w_c0_perfcntr1(reg.counter[1]);
	case 1:
		w_c0_perfctrl0(0);
		w_c0_perfcntr0(reg.counter[0]);
	}
}

/* Start all counters on current CPU */
static void mipsxx_cpu_start(void *args)
{
	unsigned int counters = op_model_mipsxx_ops.num_counters;

	switch (counters) {
	case 4:
		w_c0_perfctrl3(WHAT | reg.control[3]);
	case 3:
		w_c0_perfctrl2(WHAT | reg.control[2]);
	case 2:
		w_c0_perfctrl1(WHAT | reg.control[1]);
	case 1:
		w_c0_perfctrl0(WHAT | reg.control[0]);
	}
}

/* Stop all counters on current CPU */
static void mipsxx_cpu_stop(void *args)
{
	unsigned int counters = op_model_mipsxx_ops.num_counters;

	switch (counters) {
	case 4:
		w_c0_perfctrl3(0);
	case 3:
		w_c0_perfctrl2(0);
	case 2:
		w_c0_perfctrl1(0);
	case 1:
		w_c0_perfctrl0(0);
	}
}

static int mipsxx_perfcount_handler(struct pt_regs *regs)
{
	unsigned int counters = op_model_mipsxx_ops.num_counters;
	unsigned int control;
	unsigned int counter;
	int handled = 0;

	switch (counters) {
#define HANDLE_COUNTER(n)						\
	case n + 1:							\
		control = r_c0_perfctrl ## n();				\
		counter = r_c0_perfcntr ## n();				\
		if ((control & M_PERFCTL_INTERRUPT_ENABLE) &&		\
		    (counter & M_COUNTER_OVERFLOW)) {			\
			oprofile_add_sample(regs, n);			\
			w_c0_perfcntr ## n(reg.counter[n]);		\
			handled = 1;					\
		}
	HANDLE_COUNTER(3)
	HANDLE_COUNTER(2)
	HANDLE_COUNTER(1)
	HANDLE_COUNTER(0)
	}

	return handled;
}

#define M_CONFIG1_PC	(1 << 4)

static inline int __n_counters(void)
{
	if (!(read_c0_config1() & M_CONFIG1_PC))
		return 0;
	if (!(r_c0_perfctrl0() & M_PERFCTL_MORE))
		return 1;
	if (!(r_c0_perfctrl1() & M_PERFCTL_MORE))
		return 2;
	if (!(r_c0_perfctrl2() & M_PERFCTL_MORE))
		return 3;

	return 4;
}

static inline int n_counters(void)
{
	int counters = __n_counters();

#ifndef CONFIG_SMP
	if (current_cpu_data.cputype == CPU_34K)
		return counters >> 1;
#endif

	return counters;
}

static inline void reset_counters(int counters)
{
	switch (counters) {
	case 4:
		w_c0_perfctrl3(0);
		w_c0_perfcntr3(0);
	case 3:
		w_c0_perfctrl2(0);
		w_c0_perfcntr2(0);
	case 2:
		w_c0_perfctrl1(0);
		w_c0_perfcntr1(0);
	case 1:
		w_c0_perfctrl0(0);
		w_c0_perfcntr0(0);
	}
}

static int __init mipsxx_init(void)
{
	int counters;

	counters = n_counters();
	if (counters == 0) {
		printk(KERN_ERR "Oprofile: CPU has no performance counters\n");
		return -ENODEV;
	}

	reset_counters(counters);

	op_model_mipsxx_ops.num_counters = counters;
	switch (current_cpu_data.cputype) {
	case CPU_20KC:
		op_model_mipsxx_ops.cpu_type = "mips/20K";
		break;

	case CPU_24K:
		op_model_mipsxx_ops.cpu_type = "mips/24K";
		break;

	case CPU_25KF:
		op_model_mipsxx_ops.cpu_type = "mips/25K";
		break;

	case CPU_34K:
		op_model_mipsxx_ops.cpu_type = "mips/34K";
		break;

	case CPU_74K:
		op_model_mipsxx_ops.cpu_type = "mips/74K";
		break;

	case CPU_5KC:
		op_model_mipsxx_ops.cpu_type = "mips/5K";
		break;

	case CPU_SB1:
	case CPU_SB1A:
		op_model_mipsxx_ops.cpu_type = "mips/sb1";
		break;

	default:
		printk(KERN_ERR "Profiling unsupported for this CPU\n");

		return -ENODEV;
	}

	perf_irq = mipsxx_perfcount_handler;

	return 0;
}

static void mipsxx_exit(void)
{
	reset_counters(op_model_mipsxx_ops.num_counters);

	perf_irq = null_perf_irq;
}

struct op_mips_model op_model_mipsxx_ops = {
	.reg_setup	= mipsxx_reg_setup,
	.cpu_setup	= mipsxx_cpu_setup,
	.init		= mipsxx_init,
	.exit		= mipsxx_exit,
	.cpu_start	= mipsxx_cpu_start,
	.cpu_stop	= mipsxx_cpu_stop,
};
Commit	Line	Data
54176736 RB	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2004, 2005 by Ralf Baechle
	7	* Copyright (C) 2005 by MIPS Technologies, Inc.
	8	*/
	9	#include <linux/oprofile.h>
	10	#include <linux/interrupt.h>
	11	#include <linux/smp.h>
	12
	13	#include "op_impl.h"
	14
92c7b62f RB	15	#define M_PERFCTL_EXL (1UL << 0)
	16	#define M_PERFCTL_KERNEL (1UL << 1)
	17	#define M_PERFCTL_SUPERVISOR (1UL << 2)
	18	#define M_PERFCTL_USER (1UL << 3)
	19	#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4)
	20	#define M_PERFCTL_EVENT(event) ((event) << 5)
	21	#define M_PERFCTL_VPEID(vpe) ((vpe) << 16)
	22	#define M_PERFCTL_MT_EN(filter) ((filter) << 20)
	23	#define M_TC_EN_ALL M_PERFCTL_MT_EN(0)
	24	#define M_TC_EN_VPE M_PERFCTL_MT_EN(1)
	25	#define M_TC_EN_TC M_PERFCTL_MT_EN(2)
	26	#define M_PERFCTL_TCID(tcid) ((tcid) << 22)
	27	#define M_PERFCTL_WIDE (1UL << 30)
	28	#define M_PERFCTL_MORE (1UL << 31)
	29
	30	#define M_COUNTER_OVERFLOW (1UL << 31)
	31
	32	#ifdef CONFIG_MIPS_MT_SMP
	33	#define WHAT (M_TC_EN_VPE \| M_PERFCTL_VPEID(smp_processor_id()))
	34	#else
	35	#define WHAT 0
	36	#endif
54176736	37
92c7b62f RB	38	#define __define_perf_accessors(r, n, np) \
	39	\
	40	static inline unsigned int r_c0_ ## r ## n(void) \
	41	{ \
	42	unsigned int cpu = smp_processor_id(); \
	43	\
	44	switch (cpu) { \
	45	case 0: \
	46	return read_c0_ ## r ## n(); \
	47	case 1: \
	48	return read_c0_ ## r ## np(); \
	49	default: \
	50	BUG(); \
	51	} \
30f244ae	52	return 0; \
92c7b62f RB	53	} \
	54	\
	55	static inline void w_c0_ ## r ## n(unsigned int value) \
	56	{ \
	57	unsigned int cpu = smp_processor_id(); \
	58	\
	59	switch (cpu) { \
	60	case 0: \
	61	write_c0_ ## r ## n(value); \
	62	return; \
	63	case 1: \
	64	write_c0_ ## r ## np(value); \
	65	return; \
	66	default: \
	67	BUG(); \
	68	} \
30f244ae	69	return; \
92c7b62f RB	70	} \
	71
	72	__define_perf_accessors(perfcntr, 0, 2)
	73	__define_perf_accessors(perfcntr, 1, 3)
	74	__define_perf_accessors(perfcntr, 2, 2)
	75	__define_perf_accessors(perfcntr, 3, 2)
	76
	77	__define_perf_accessors(perfctrl, 0, 2)
	78	__define_perf_accessors(perfctrl, 1, 3)
	79	__define_perf_accessors(perfctrl, 2, 2)
	80	__define_perf_accessors(perfctrl, 3, 2)
54176736	81
1acf1ca7	82	struct op_mips_model op_model_mipsxx_ops;
54176736 RB	83
	84	static struct mipsxx_register_config {
	85	unsigned int control[4];
	86	unsigned int counter[4];
	87	} reg;
	88
	89	/* Compute all of the registers in preparation for enabling profiling. */
	90
	91	static void mipsxx_reg_setup(struct op_counter_config *ctr)
	92	{
1acf1ca7	93	unsigned int counters = op_model_mipsxx_ops.num_counters;
54176736 RB	94	int i;
	95
	96	/* Compute the performance counter control word. */
	97	/* For now count kernel and user mode */
	98	for (i = 0; i < counters; i++) {
	99	reg.control[i] = 0;
	100	reg.counter[i] = 0;
	101
	102	if (!ctr[i].enabled)
	103	continue;
	104
	105	reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) \|
	106	M_PERFCTL_INTERRUPT_ENABLE;
	107	if (ctr[i].kernel)
	108	reg.control[i] \|= M_PERFCTL_KERNEL;
	109	if (ctr[i].user)
	110	reg.control[i] \|= M_PERFCTL_USER;
	111	if (ctr[i].exl)
	112	reg.control[i] \|= M_PERFCTL_EXL;
	113	reg.counter[i] = 0x80000000 - ctr[i].count;
	114	}
	115	}
	116
	117	/* Program all of the registers in preparation for enabling profiling. */
	118
	119	static void mipsxx_cpu_setup (void *args)
	120	{
1acf1ca7	121	unsigned int counters = op_model_mipsxx_ops.num_counters;
54176736 RB	122
	123	switch (counters) {
	124	case 4:
92c7b62f RB	125	w_c0_perfctrl3(0);
92c7b62f RB	126	w_c0_perfcntr3(reg.counter[3]);
54176736	127	case 3:
92c7b62f RB	128	w_c0_perfctrl2(0);
92c7b62f RB	129	w_c0_perfcntr2(reg.counter[2]);
54176736	130	case 2:
92c7b62f RB	131	w_c0_perfctrl1(0);
92c7b62f RB	132	w_c0_perfcntr1(reg.counter[1]);
54176736	133	case 1:
92c7b62f RB	134	w_c0_perfctrl0(0);
92c7b62f RB	135	w_c0_perfcntr0(reg.counter[0]);
54176736 RB	136	}
	137	}
	138
	139	/* Start all counters on current CPU */
	140	static void mipsxx_cpu_start(void *args)
	141	{
1acf1ca7	142	unsigned int counters = op_model_mipsxx_ops.num_counters;
54176736 RB	143
	144	switch (counters) {
	145	case 4:
92c7b62f	146	w_c0_perfctrl3(WHAT \| reg.control[3]);
54176736	147	case 3:
92c7b62f	148	w_c0_perfctrl2(WHAT \| reg.control[2]);
54176736	149	case 2:
92c7b62f	150	w_c0_perfctrl1(WHAT \| reg.control[1]);
54176736	151	case 1:
92c7b62f	152	w_c0_perfctrl0(WHAT \| reg.control[0]);
54176736 RB	153	}
	154	}
	155
	156	/* Stop all counters on current CPU */
	157	static void mipsxx_cpu_stop(void *args)
	158	{
1acf1ca7	159	unsigned int counters = op_model_mipsxx_ops.num_counters;
54176736 RB	160
	161	switch (counters) {
	162	case 4:
92c7b62f	163	w_c0_perfctrl3(0);
54176736	164	case 3:
92c7b62f	165	w_c0_perfctrl2(0);
54176736	166	case 2:
92c7b62f	167	w_c0_perfctrl1(0);
54176736	168	case 1:
92c7b62f	169	w_c0_perfctrl0(0);
54176736 RB	170	}
	171	}
	172
ba339c03	173	static int mipsxx_perfcount_handler(struct pt_regs *regs)
54176736	174	{
1acf1ca7	175	unsigned int counters = op_model_mipsxx_ops.num_counters;
54176736 RB	176	unsigned int control;
54176736 RB	177	unsigned int counter;
ba339c03	178	int handled = 0;
54176736 RB	179
	180	switch (counters) {
	181	#define HANDLE_COUNTER(n) \
	182	case n + 1: \
92c7b62f RB	183	control = r_c0_perfctrl ## n(); \
92c7b62f RB	184	counter = r_c0_perfcntr ## n(); \
54176736 RB	185	if ((control & M_PERFCTL_INTERRUPT_ENABLE) && \
	186	(counter & M_COUNTER_OVERFLOW)) { \
	187	oprofile_add_sample(regs, n); \
92c7b62f	188	w_c0_perfcntr ## n(reg.counter[n]); \
ba339c03	189	handled = 1; \
54176736 RB	190	}
	191	HANDLE_COUNTER(3)
	192	HANDLE_COUNTER(2)
	193	HANDLE_COUNTER(1)
	194	HANDLE_COUNTER(0)
	195	}
ba339c03 RB	196
ba339c03 RB	197	return handled;
54176736 RB	198	}
	199
	200	#define M_CONFIG1_PC (1 << 4)
	201
92c7b62f	202	static inline int __n_counters(void)
54176736 RB	203	{
	204	if (!(read_c0_config1() & M_CONFIG1_PC))
	205	return 0;
92c7b62f	206	if (!(r_c0_perfctrl0() & M_PERFCTL_MORE))
54176736	207	return 1;
92c7b62f	208	if (!(r_c0_perfctrl1() & M_PERFCTL_MORE))
54176736	209	return 2;
92c7b62f	210	if (!(r_c0_perfctrl2() & M_PERFCTL_MORE))
54176736 RB	211	return 3;
	212
	213	return 4;
	214	}
	215
92c7b62f RB	216	static inline int n_counters(void)
	217	{
	218	int counters = __n_counters();
	219
	220	#ifndef CONFIG_SMP
	221	if (current_cpu_data.cputype == CPU_34K)
	222	return counters >> 1;
	223	#endif
	224
	225	return counters;
	226	}
	227
54176736 RB	228	static inline void reset_counters(int counters)
	229	{
	230	switch (counters) {
	231	case 4:
92c7b62f RB	232	w_c0_perfctrl3(0);
92c7b62f RB	233	w_c0_perfcntr3(0);
54176736	234	case 3:
92c7b62f RB	235	w_c0_perfctrl2(0);
92c7b62f RB	236	w_c0_perfcntr2(0);
54176736	237	case 2:
92c7b62f RB	238	w_c0_perfctrl1(0);
92c7b62f RB	239	w_c0_perfcntr1(0);
54176736	240	case 1:
92c7b62f RB	241	w_c0_perfctrl0(0);
92c7b62f RB	242	w_c0_perfcntr0(0);
54176736 RB	243	}
	244	}
	245
	246	static int __init mipsxx_init(void)
	247	{
	248	int counters;
	249
	250	counters = n_counters();
9efeae9a RB	251	if (counters == 0) {
9efeae9a RB	252	printk(KERN_ERR "Oprofile: CPU has no performance counters\n");
54176736	253	return -ENODEV;
9efeae9a	254	}
54176736 RB	255
	256	reset_counters(counters);
	257
1acf1ca7	258	op_model_mipsxx_ops.num_counters = counters;
54176736	259	switch (current_cpu_data.cputype) {
2065988e	260	case CPU_20KC:
1acf1ca7	261	op_model_mipsxx_ops.cpu_type = "mips/20K";
2065988e RB	262	break;
2065988e RB	263
54176736	264	case CPU_24K:
1acf1ca7	265	op_model_mipsxx_ops.cpu_type = "mips/24K";
54176736 RB	266	break;
54176736 RB	267
2065988e	268	case CPU_25KF:
1acf1ca7	269	op_model_mipsxx_ops.cpu_type = "mips/25K";
2065988e RB	270	break;
2065988e RB	271
fcfd980c	272	case CPU_34K:
1acf1ca7	273	op_model_mipsxx_ops.cpu_type = "mips/34K";
fcfd980c	274	break;
c620953c CD	275
c620953c CD	276	case CPU_74K:
1acf1ca7	277	op_model_mipsxx_ops.cpu_type = "mips/74K";
c620953c	278	break;
fcfd980c	279
2065988e	280	case CPU_5KC:
1acf1ca7	281	op_model_mipsxx_ops.cpu_type = "mips/5K";
2065988e RB	282	break;
2065988e RB	283
c03bc121 MM	284	case CPU_SB1:
c03bc121 MM	285	case CPU_SB1A:
1acf1ca7	286	op_model_mipsxx_ops.cpu_type = "mips/sb1";
c03bc121 MM	287	break;
c03bc121 MM	288
54176736 RB	289	default:
	290	printk(KERN_ERR "Profiling unsupported for this CPU\n");
	291
	292	return -ENODEV;
	293	}
	294
	295	perf_irq = mipsxx_perfcount_handler;
	296
	297	return 0;
	298	}
	299
	300	static void mipsxx_exit(void)
	301	{
1acf1ca7	302	reset_counters(op_model_mipsxx_ops.num_counters);
54176736 RB	303
	304	perf_irq = null_perf_irq;
	305	}
	306
1acf1ca7	307	struct op_mips_model op_model_mipsxx_ops = {
54176736 RB	308	.reg_setup = mipsxx_reg_setup,
	309	.cpu_setup = mipsxx_cpu_setup,
	310	.init = mipsxx_init,
	311	.exit = mipsxx_exit,
	312	.cpu_start = mipsxx_cpu_start,
	313	.cpu_stop = mipsxx_cpu_stop,
	314	};