[deliverable/linux.git] / arch / mips / pci / fixup-cobalt.c

/*
 * Cobalt Qube/Raq PCI support
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1995, 1996, 1997, 2002, 2003 by Ralf Baechle
 * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
 */
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>

#include <asm/pci.h>
#include <asm/io.h>
#include <asm/gt64120.h>

#include <cobalt.h>
#include <irq.h>

/*
 * PCI slot numbers
 */
#define COBALT_PCICONF_CPU	0x06
#define COBALT_PCICONF_ETH0	0x07
#define COBALT_PCICONF_RAQSCSI	0x08
#define COBALT_PCICONF_VIA	0x09
#define COBALT_PCICONF_PCISLOT	0x0A
#define COBALT_PCICONF_ETH1	0x0C

/*
 * The Cobalt board ID information.  The boards have an ID number wired
 * into the VIA that is available in the high nibble of register 94.
 */
#define VIA_COBALT_BRD_ID_REG  0x94
#define VIA_COBALT_BRD_REG_to_ID(reg)	((unsigned char)(reg) >> 4)

static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
{
	if (dev->devfn == PCI_DEVFN(0, 0) &&
		(dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) {

		dev->class = (PCI_CLASS_BRIDGE_HOST << 8) | (dev->class & 0xff);

		printk(KERN_INFO "Galileo: fixed bridge class\n");
	}
}

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
	 qube_raq_galileo_early_fixup);

static void __devinit cobalt_legacy_ide_resource_fixup(struct pci_dev *dev,
						       struct resource *res)
{
	struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
	unsigned long offset = hose->io_offset;
	struct resource orig = *res;

	if (!(res->flags & IORESOURCE_IO) ||
	    !(res->flags & IORESOURCE_PCI_FIXED))
		return;

	res->start -= offset;
	res->end -= offset;
	dev_printk(KERN_DEBUG, &dev->dev, "converted legacy %pR to bus %pR\n",
		   &orig, res);
}

static void __devinit cobalt_legacy_ide_fixup(struct pci_dev *dev)
{
	u32 class;
	u8 progif;

	/*
	 * If the IDE controller is in legacy mode, pci_setup_device() fills in
	 * the resources with the legacy addresses that normally appear on the
	 * PCI bus, just as if we had read them from a BAR.
	 *
	 * However, with the GT-64111, those legacy addresses, e.g., 0x1f0,
	 * will never appear on the PCI bus because it converts memory accesses
	 * in the PCI I/O region (which is never at address zero) into I/O port
	 * accesses with no address translation.
	 *
	 * For example, if GT_DEF_PCI0_IO_BASE is 0x10000000, a load or store
	 * to physical address 0x100001f0 will become a PCI access to I/O port
	 * 0x100001f0.  There's no way to generate an access to I/O port 0x1f0,
	 * but the VT82C586 IDE controller does respond at 0x100001f0 because
	 * it only decodes the low 24 bits of the address.
	 *
	 * When this quirk runs, the pci_dev resources should contain bus
	 * addresses, not Linux I/O port numbers, so convert legacy addresses
	 * like 0x1f0 to bus addresses like 0x100001f0.  Later, we'll convert
	 * them back with pcibios_fixup_bus() or pcibios_bus_to_resource().
	 */
	class = dev->class >> 8;
	if (class != PCI_CLASS_STORAGE_IDE)
		return;

	pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
	if ((progif & 1) == 0) {
		cobalt_legacy_ide_resource_fixup(dev, &dev->resource[0]);
		cobalt_legacy_ide_resource_fixup(dev, &dev->resource[1]);
	}
	if ((progif & 4) == 0) {
		cobalt_legacy_ide_resource_fixup(dev, &dev->resource[2]);
		cobalt_legacy_ide_resource_fixup(dev, &dev->resource[3]);
	}
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
	  cobalt_legacy_ide_fixup);

static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
{
	unsigned short cfgword;
	unsigned char lt;

	/* Enable Bus Mastering and fast back to back. */
	pci_read_config_word(dev, PCI_COMMAND, &cfgword);
	cfgword |= (PCI_COMMAND_FAST_BACK | PCI_COMMAND_MASTER);
	pci_write_config_word(dev, PCI_COMMAND, cfgword);

	/* Enable both ide interfaces. ROM only enables primary one.  */
	pci_write_config_byte(dev, 0x40, 0xb);

	/* Set latency timer to reasonable value. */
	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lt);
	if (lt < 64)
		pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
	 qube_raq_via_bmIDE_fixup);

static void qube_raq_galileo_fixup(struct pci_dev *dev)
{
	if (dev->devfn != PCI_DEVFN(0, 0))
		return;

	/* Fix PCI latency-timer and cache-line-size values in Galileo
	 * host bridge.
	 */
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);

	/*
	 * The code described by the comment below has been removed
	 * as it causes bus mastering by the Ethernet controllers
	 * to break under any kind of network load. We always set
	 * the retry timeouts to their maximum.
	 *
	 * --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--
	 *
	 * On all machines prior to Q2, we had the STOP line disconnected
	 * from Galileo to VIA on PCI.  The new Galileo does not function
	 * correctly unless we have it connected.
	 *
	 * Therefore we must set the disconnect/retry cycle values to
	 * something sensible when using the new Galileo.
	 */

 	printk(KERN_INFO "Galileo: revision %u\n", dev->revision);

#if 0
	if (dev->revision >= 0x10) {
		/* New Galileo, assumes PCI stop line to VIA is connected. */
		GT_WRITE(GT_PCI0_TOR_OFS, 0x4020);
	} else if (dev->revision == 0x1 || dev->revision == 0x2)
#endif
	{
		signed int timeo;
		/* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
		timeo = GT_READ(GT_PCI0_TOR_OFS);
		/* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
		GT_WRITE(GT_PCI0_TOR_OFS,
			(0xff << 16) |		/* retry count */
			(0xff << 8) |		/* timeout 1   */
			0xff);			/* timeout 0   */

		/* enable PCI retry exceeded interrupt */
		GT_WRITE(GT_INTRMASK_OFS, GT_INTR_RETRYCTR0_MSK | GT_READ(GT_INTRMASK_OFS));
	}
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
	 qube_raq_galileo_fixup);

int cobalt_board_id;

static void qube_raq_via_board_id_fixup(struct pci_dev *dev)
{
	u8 id;
	int retval;

	retval = pci_read_config_byte(dev, VIA_COBALT_BRD_ID_REG, &id);
	if (retval) {
		panic("Cannot read board ID");
		return;
	}

	cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(id);

	printk(KERN_INFO "Cobalt board ID: %d\n", cobalt_board_id);
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0,
	 qube_raq_via_board_id_fixup);

static char irq_tab_qube1[] __initdata = {
  [COBALT_PCICONF_CPU]     = 0,
  [COBALT_PCICONF_ETH0]    = QUBE1_ETH0_IRQ,
  [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
  [COBALT_PCICONF_VIA]     = 0,
  [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
  [COBALT_PCICONF_ETH1]    = 0
};

static char irq_tab_cobalt[] __initdata = {
  [COBALT_PCICONF_CPU]     = 0,
  [COBALT_PCICONF_ETH0]    = ETH0_IRQ,
  [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
  [COBALT_PCICONF_VIA]     = 0,
  [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
  [COBALT_PCICONF_ETH1]    = ETH1_IRQ
};

static char irq_tab_raq2[] __initdata = {
  [COBALT_PCICONF_CPU]     = 0,
  [COBALT_PCICONF_ETH0]    = ETH0_IRQ,
  [COBALT_PCICONF_RAQSCSI] = RAQ2_SCSI_IRQ,
  [COBALT_PCICONF_VIA]     = 0,
  [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
  [COBALT_PCICONF_ETH1]    = ETH1_IRQ
};

int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	if (cobalt_board_id <= COBALT_BRD_ID_QUBE1)
		return irq_tab_qube1[slot];

	if (cobalt_board_id == COBALT_BRD_ID_RAQ2)
		return irq_tab_raq2[slot];

	return irq_tab_cobalt[slot];
}

/* Do platform specific device initialization at pci_enable_device() time */
int pcibios_plat_dev_init(struct pci_dev *dev)
{
	return 0;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Cobalt Qube/Raq PCI support
	3	*
	4	* This file is subject to the terms and conditions of the GNU General Public
	5	* License. See the file "COPYING" in the main directory of this archive
	6	* for more details.
	7	*
	8	* Copyright (C) 1995, 1996, 1997, 2002, 2003 by Ralf Baechle
	9	* Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
	10	*/
	11	#include <linux/types.h>
	12	#include <linux/pci.h>
	13	#include <linux/kernel.h>
	14	#include <linux/init.h>
	15
	16	#include <asm/pci.h>
	17	#include <asm/io.h>
	18	#include <asm/gt64120.h>
	19
44320f2b	20	#include <cobalt.h>
d5ab1a69	21	#include <irq.h>
1da177e4	22
b4126e86 YY	23	/*
	24	* PCI slot numbers
	25	*/
	26	#define COBALT_PCICONF_CPU 0x06
	27	#define COBALT_PCICONF_ETH0 0x07
	28	#define COBALT_PCICONF_RAQSCSI 0x08
	29	#define COBALT_PCICONF_VIA 0x09
	30	#define COBALT_PCICONF_PCISLOT 0x0A
	31	#define COBALT_PCICONF_ETH1 0x0C
	32
	33	/*
	34	* The Cobalt board ID information. The boards have an ID number wired
	35	* into the VIA that is available in the high nibble of register 94.
	36	*/
	37	#define VIA_COBALT_BRD_ID_REG 0x94
	38	#define VIA_COBALT_BRD_REG_to_ID(reg) ((unsigned char)(reg) >> 4)
	39
c4ed38a0 RB	40	static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
	41	{
	42	if (dev->devfn == PCI_DEVFN(0, 0) &&
	43	(dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) {
	44
	45	dev->class = (PCI_CLASS_BRIDGE_HOST << 8) \| (dev->class & 0xff);
	46
	47	printk(KERN_INFO "Galileo: fixed bridge class\n");
	48	}
	49	}
	50
	51	DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
	52	qube_raq_galileo_early_fixup);
	53
81904710 BH	54	static void __devinit cobalt_legacy_ide_resource_fixup(struct pci_dev *dev,
	55	struct resource *res)
	56	{
	57	struct pci_controller hose = (struct pci_controller )dev->sysdata;
	58	unsigned long offset = hose->io_offset;
	59	struct resource orig = *res;
	60
	61	if (!(res->flags & IORESOURCE_IO) \|\|
	62	!(res->flags & IORESOURCE_PCI_FIXED))
	63	return;
	64
	65	res->start -= offset;
	66	res->end -= offset;
	67	dev_printk(KERN_DEBUG, &dev->dev, "converted legacy %pR to bus %pR\n",
	68	&orig, res);
	69	}
	70
	71	static void __devinit cobalt_legacy_ide_fixup(struct pci_dev *dev)
	72	{
	73	u32 class;
	74	u8 progif;
	75
	76	/*
	77	* If the IDE controller is in legacy mode, pci_setup_device() fills in
	78	* the resources with the legacy addresses that normally appear on the
	79	* PCI bus, just as if we had read them from a BAR.
	80	*
	81	* However, with the GT-64111, those legacy addresses, e.g., 0x1f0,
	82	* will never appear on the PCI bus because it converts memory accesses
	83	* in the PCI I/O region (which is never at address zero) into I/O port
	84	* accesses with no address translation.
	85	*
	86	* For example, if GT_DEF_PCI0_IO_BASE is 0x10000000, a load or store
	87	* to physical address 0x100001f0 will become a PCI access to I/O port
	88	* 0x100001f0. There's no way to generate an access to I/O port 0x1f0,
	89	* but the VT82C586 IDE controller does respond at 0x100001f0 because
	90	* it only decodes the low 24 bits of the address.
	91	*
	92	* When this quirk runs, the pci_dev resources should contain bus
	93	* addresses, not Linux I/O port numbers, so convert legacy addresses
	94	* like 0x1f0 to bus addresses like 0x100001f0. Later, we'll convert
	95	* them back with pcibios_fixup_bus() or pcibios_bus_to_resource().
	96	*/
	97	class = dev->class >> 8;
	98	if (class != PCI_CLASS_STORAGE_IDE)
	99	return;
	100
	101	pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
	102	if ((progif & 1) == 0) {
	103	cobalt_legacy_ide_resource_fixup(dev, &dev->resource[0]);
	104	cobalt_legacy_ide_resource_fixup(dev, &dev->resource[1]);
	105	}
	106	if ((progif & 4) == 0) {
	107	cobalt_legacy_ide_resource_fixup(dev, &dev->resource[2]);
	108	cobalt_legacy_ide_resource_fixup(dev, &dev->resource[3]);
	109	}
	110	}
	111
	112	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
	113	cobalt_legacy_ide_fixup);
	114
1da177e4 LT	115	static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
	116	{
	117	unsigned short cfgword;
	118	unsigned char lt;
	119
	120	/* Enable Bus Mastering and fast back to back. */
	121	pci_read_config_word(dev, PCI_COMMAND, &cfgword);
	122	cfgword \|= (PCI_COMMAND_FAST_BACK \| PCI_COMMAND_MASTER);
	123	pci_write_config_word(dev, PCI_COMMAND, cfgword);
	124
	125	/* Enable both ide interfaces. ROM only enables primary one. */
	126	pci_write_config_byte(dev, 0x40, 0xb);
	127
	128	/* Set latency timer to reasonable value. */
	129	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lt);
	130	if (lt < 64)
	131	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
52378445	132	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
1da177e4 LT	133	}
	134
	135	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
	136	qube_raq_via_bmIDE_fixup);
	137
	138	static void qube_raq_galileo_fixup(struct pci_dev *dev)
	139	{
c4ed38a0 RB	140	if (dev->devfn != PCI_DEVFN(0, 0))
	141	return;
	142
1da177e4 LT	143	/* Fix PCI latency-timer and cache-line-size values in Galileo
	144	* host bridge.
	145	*/
	146	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
52378445	147	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
1da177e4 LT	148
1da177e4 LT	149	/*
c4ed38a0 RB	150	* The code described by the comment below has been removed
	151	* as it causes bus mastering by the Ethernet controllers
	152	* to break under any kind of network load. We always set
	153	* the retry timeouts to their maximum.
	154	*
	155	* --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--
	156	*
1da177e4 LT	157	* On all machines prior to Q2, we had the STOP line disconnected
	158	* from Galileo to VIA on PCI. The new Galileo does not function
	159	* correctly unless we have it connected.
	160	*
	161	* Therefore we must set the disconnect/retry cycle values to
	162	* something sensible when using the new Galileo.
	163	*/
c4ed38a0	164
44c10138	165	printk(KERN_INFO "Galileo: revision %u\n", dev->revision);
c4ed38a0 RB	166
c4ed38a0 RB	167	#if 0
44c10138	168	if (dev->revision >= 0x10) {
1da177e4	169	/* New Galileo, assumes PCI stop line to VIA is connected. */
56ae5833	170	GT_WRITE(GT_PCI0_TOR_OFS, 0x4020);
44c10138	171	} else if (dev->revision == 0x1 \|\| dev->revision == 0x2)
c4ed38a0 RB	172	#endif
c4ed38a0 RB	173	{
1da177e4 LT	174	signed int timeo;
1da177e4 LT	175	/* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
56ae5833	176	timeo = GT_READ(GT_PCI0_TOR_OFS);
1da177e4	177	/* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
56ae5833	178	GT_WRITE(GT_PCI0_TOR_OFS,
c4ed38a0 RB	179	(0xff << 16) \| /* retry count */
c4ed38a0 RB	180	(0xff << 8) \| /* timeout 1 */
56ae5833	181	0xff); /* timeout 0 */
c4ed38a0 RB	182
c4ed38a0 RB	183	/* enable PCI retry exceeded interrupt */
56ae5833	184	GT_WRITE(GT_INTRMASK_OFS, GT_INTR_RETRYCTR0_MSK \| GT_READ(GT_INTRMASK_OFS));
1da177e4 LT	185	}
	186	}
	187
c4ed38a0	188	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
1da177e4 LT	189	qube_raq_galileo_fixup);
1da177e4 LT	190
3f2d560e YY	191	int cobalt_board_id;
	192
	193	static void qube_raq_via_board_id_fixup(struct pci_dev *dev)
	194	{
	195	u8 id;
	196	int retval;
	197
	198	retval = pci_read_config_byte(dev, VIA_COBALT_BRD_ID_REG, &id);
	199	if (retval) {
	200	panic("Cannot read board ID");
	201	return;
	202	}
	203
	204	cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(id);
	205
	206	printk(KERN_INFO "Cobalt board ID: %d\n", cobalt_board_id);
	207	}
	208
	209	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0,
	210	qube_raq_via_board_id_fixup);
	211
c4ed38a0 RB	212	static char irq_tab_qube1[] __initdata = {
c4ed38a0 RB	213	[COBALT_PCICONF_CPU] = 0,
d5ab1a69 YY	214	[COBALT_PCICONF_ETH0] = QUBE1_ETH0_IRQ,
d5ab1a69 YY	215	[COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
c4ed38a0	216	[COBALT_PCICONF_VIA] = 0,
d5ab1a69	217	[COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
c4ed38a0 RB	218	[COBALT_PCICONF_ETH1] = 0
	219	};
	220
1da177e4 LT	221	static char irq_tab_cobalt[] __initdata = {
1da177e4 LT	222	[COBALT_PCICONF_CPU] = 0,
d5ab1a69 YY	223	[COBALT_PCICONF_ETH0] = ETH0_IRQ,
d5ab1a69 YY	224	[COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
1da177e4	225	[COBALT_PCICONF_VIA] = 0,
d5ab1a69 YY	226	[COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
d5ab1a69 YY	227	[COBALT_PCICONF_ETH1] = ETH1_IRQ
1da177e4 LT	228	};
	229
	230	static char irq_tab_raq2[] __initdata = {
	231	[COBALT_PCICONF_CPU] = 0,
d5ab1a69 YY	232	[COBALT_PCICONF_ETH0] = ETH0_IRQ,
d5ab1a69 YY	233	[COBALT_PCICONF_RAQSCSI] = RAQ2_SCSI_IRQ,
1da177e4	234	[COBALT_PCICONF_VIA] = 0,
d5ab1a69 YY	235	[COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
d5ab1a69 YY	236	[COBALT_PCICONF_ETH1] = ETH1_IRQ
1da177e4 LT	237	};
1da177e4 LT	238
19df0d11	239	int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
1da177e4	240	{
f6c0f32e	241	if (cobalt_board_id <= COBALT_BRD_ID_QUBE1)
c4ed38a0 RB	242	return irq_tab_qube1[slot];
c4ed38a0 RB	243
1da177e4 LT	244	if (cobalt_board_id == COBALT_BRD_ID_RAQ2)
	245	return irq_tab_raq2[slot];
	246
	247	return irq_tab_cobalt[slot];
	248	}
	249
	250	/* Do platform specific device initialization at pci_enable_device() time */
	251	int pcibios_plat_dev_init(struct pci_dev *dev)
	252	{
	253	return 0;
	254	}