Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Cobalt Qube/Raq PCI support | |
3 | * | |
4 | * This file is subject to the terms and conditions of the GNU General Public | |
5 | * License. See the file "COPYING" in the main directory of this archive | |
6 | * for more details. | |
7 | * | |
8 | * Copyright (C) 1995, 1996, 1997, 2002, 2003 by Ralf Baechle | |
9 | * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv) | |
10 | */ | |
11 | #include <linux/types.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/init.h> | |
15 | ||
1da177e4 LT |
16 | #include <asm/io.h> |
17 | #include <asm/gt64120.h> | |
18 | ||
44320f2b | 19 | #include <cobalt.h> |
d5ab1a69 | 20 | #include <irq.h> |
1da177e4 | 21 | |
b4126e86 YY |
22 | /* |
23 | * PCI slot numbers | |
24 | */ | |
25 | #define COBALT_PCICONF_CPU 0x06 | |
26 | #define COBALT_PCICONF_ETH0 0x07 | |
27 | #define COBALT_PCICONF_RAQSCSI 0x08 | |
28 | #define COBALT_PCICONF_VIA 0x09 | |
29 | #define COBALT_PCICONF_PCISLOT 0x0A | |
30 | #define COBALT_PCICONF_ETH1 0x0C | |
31 | ||
32 | /* | |
33 | * The Cobalt board ID information. The boards have an ID number wired | |
34 | * into the VIA that is available in the high nibble of register 94. | |
35 | */ | |
36 | #define VIA_COBALT_BRD_ID_REG 0x94 | |
37 | #define VIA_COBALT_BRD_REG_to_ID(reg) ((unsigned char)(reg) >> 4) | |
38 | ||
28eb0e46 | 39 | static void qube_raq_galileo_early_fixup(struct pci_dev *dev) |
c4ed38a0 RB |
40 | { |
41 | if (dev->devfn == PCI_DEVFN(0, 0) && | |
42 | (dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) { | |
43 | ||
44 | dev->class = (PCI_CLASS_BRIDGE_HOST << 8) | (dev->class & 0xff); | |
45 | ||
46 | printk(KERN_INFO "Galileo: fixed bridge class\n"); | |
47 | } | |
48 | } | |
49 | ||
50 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111, | |
51 | qube_raq_galileo_early_fixup); | |
52 | ||
28eb0e46 | 53 | static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev) |
1da177e4 LT |
54 | { |
55 | unsigned short cfgword; | |
56 | unsigned char lt; | |
57 | ||
58 | /* Enable Bus Mastering and fast back to back. */ | |
59 | pci_read_config_word(dev, PCI_COMMAND, &cfgword); | |
60 | cfgword |= (PCI_COMMAND_FAST_BACK | PCI_COMMAND_MASTER); | |
61 | pci_write_config_word(dev, PCI_COMMAND, cfgword); | |
62 | ||
63 | /* Enable both ide interfaces. ROM only enables primary one. */ | |
64 | pci_write_config_byte(dev, 0x40, 0xb); | |
65 | ||
66 | /* Set latency timer to reasonable value. */ | |
67 | pci_read_config_byte(dev, PCI_LATENCY_TIMER, <); | |
68 | if (lt < 64) | |
69 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); | |
52378445 | 70 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8); |
1da177e4 LT |
71 | } |
72 | ||
73 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, | |
74 | qube_raq_via_bmIDE_fixup); | |
75 | ||
28eb0e46 | 76 | static void qube_raq_galileo_fixup(struct pci_dev *dev) |
1da177e4 | 77 | { |
c4ed38a0 RB |
78 | if (dev->devfn != PCI_DEVFN(0, 0)) |
79 | return; | |
80 | ||
1da177e4 LT |
81 | /* Fix PCI latency-timer and cache-line-size values in Galileo |
82 | * host bridge. | |
83 | */ | |
84 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); | |
52378445 | 85 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8); |
1da177e4 LT |
86 | |
87 | /* | |
c4ed38a0 RB |
88 | * The code described by the comment below has been removed |
89 | * as it causes bus mastering by the Ethernet controllers | |
90 | * to break under any kind of network load. We always set | |
91 | * the retry timeouts to their maximum. | |
92 | * | |
93 | * --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x-- | |
94 | * | |
1da177e4 | 95 | * On all machines prior to Q2, we had the STOP line disconnected |
70342287 | 96 | * from Galileo to VIA on PCI. The new Galileo does not function |
1da177e4 LT |
97 | * correctly unless we have it connected. |
98 | * | |
99 | * Therefore we must set the disconnect/retry cycle values to | |
100 | * something sensible when using the new Galileo. | |
101 | */ | |
c4ed38a0 | 102 | |
70342287 | 103 | printk(KERN_INFO "Galileo: revision %u\n", dev->revision); |
c4ed38a0 RB |
104 | |
105 | #if 0 | |
44c10138 | 106 | if (dev->revision >= 0x10) { |
1da177e4 | 107 | /* New Galileo, assumes PCI stop line to VIA is connected. */ |
56ae5833 | 108 | GT_WRITE(GT_PCI0_TOR_OFS, 0x4020); |
44c10138 | 109 | } else if (dev->revision == 0x1 || dev->revision == 0x2) |
c4ed38a0 RB |
110 | #endif |
111 | { | |
1da177e4 LT |
112 | signed int timeo; |
113 | /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */ | |
56ae5833 | 114 | timeo = GT_READ(GT_PCI0_TOR_OFS); |
1da177e4 | 115 | /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */ |
56ae5833 | 116 | GT_WRITE(GT_PCI0_TOR_OFS, |
c4ed38a0 RB |
117 | (0xff << 16) | /* retry count */ |
118 | (0xff << 8) | /* timeout 1 */ | |
56ae5833 | 119 | 0xff); /* timeout 0 */ |
c4ed38a0 RB |
120 | |
121 | /* enable PCI retry exceeded interrupt */ | |
56ae5833 | 122 | GT_WRITE(GT_INTRMASK_OFS, GT_INTR_RETRYCTR0_MSK | GT_READ(GT_INTRMASK_OFS)); |
1da177e4 LT |
123 | } |
124 | } | |
125 | ||
c4ed38a0 | 126 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111, |
1da177e4 LT |
127 | qube_raq_galileo_fixup); |
128 | ||
3f2d560e YY |
129 | int cobalt_board_id; |
130 | ||
28eb0e46 | 131 | static void qube_raq_via_board_id_fixup(struct pci_dev *dev) |
3f2d560e YY |
132 | { |
133 | u8 id; | |
134 | int retval; | |
135 | ||
136 | retval = pci_read_config_byte(dev, VIA_COBALT_BRD_ID_REG, &id); | |
137 | if (retval) { | |
138 | panic("Cannot read board ID"); | |
139 | return; | |
140 | } | |
141 | ||
142 | cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(id); | |
143 | ||
144 | printk(KERN_INFO "Cobalt board ID: %d\n", cobalt_board_id); | |
145 | } | |
146 | ||
147 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, | |
148 | qube_raq_via_board_id_fixup); | |
149 | ||
c4ed38a0 | 150 | static char irq_tab_qube1[] __initdata = { |
70342287 RB |
151 | [COBALT_PCICONF_CPU] = 0, |
152 | [COBALT_PCICONF_ETH0] = QUBE1_ETH0_IRQ, | |
d5ab1a69 | 153 | [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ, |
70342287 | 154 | [COBALT_PCICONF_VIA] = 0, |
d5ab1a69 | 155 | [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ, |
70342287 | 156 | [COBALT_PCICONF_ETH1] = 0 |
c4ed38a0 RB |
157 | }; |
158 | ||
1da177e4 | 159 | static char irq_tab_cobalt[] __initdata = { |
70342287 RB |
160 | [COBALT_PCICONF_CPU] = 0, |
161 | [COBALT_PCICONF_ETH0] = ETH0_IRQ, | |
d5ab1a69 | 162 | [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ, |
70342287 | 163 | [COBALT_PCICONF_VIA] = 0, |
d5ab1a69 | 164 | [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ, |
70342287 | 165 | [COBALT_PCICONF_ETH1] = ETH1_IRQ |
1da177e4 LT |
166 | }; |
167 | ||
168 | static char irq_tab_raq2[] __initdata = { | |
70342287 RB |
169 | [COBALT_PCICONF_CPU] = 0, |
170 | [COBALT_PCICONF_ETH0] = ETH0_IRQ, | |
d5ab1a69 | 171 | [COBALT_PCICONF_RAQSCSI] = RAQ2_SCSI_IRQ, |
70342287 | 172 | [COBALT_PCICONF_VIA] = 0, |
d5ab1a69 | 173 | [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ, |
70342287 | 174 | [COBALT_PCICONF_ETH1] = ETH1_IRQ |
1da177e4 LT |
175 | }; |
176 | ||
19df0d11 | 177 | int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
1da177e4 | 178 | { |
f6c0f32e | 179 | if (cobalt_board_id <= COBALT_BRD_ID_QUBE1) |
c4ed38a0 RB |
180 | return irq_tab_qube1[slot]; |
181 | ||
1da177e4 LT |
182 | if (cobalt_board_id == COBALT_BRD_ID_RAQ2) |
183 | return irq_tab_raq2[slot]; | |
184 | ||
185 | return irq_tab_cobalt[slot]; | |
186 | } | |
187 | ||
188 | /* Do platform specific device initialization at pci_enable_device() time */ | |
189 | int pcibios_plat_dev_init(struct pci_dev *dev) | |
190 | { | |
191 | return 0; | |
192 | } |