Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | #include <linux/init.h> |
2 | #include <linux/pci.h> | |
3 | ||
4 | /* PCI interrupt pins */ | |
5 | #define PCIA 1 | |
6 | #define PCIB 2 | |
7 | #define PCIC 3 | |
8 | #define PCID 4 | |
9 | ||
10 | /* This table is filled in by interrogating the PIIX4 chip */ | |
28eb0e46 | 11 | static char pci_irq[5] = { |
2eaaac50 | 12 | }; |
1da177e4 LT |
13 | |
14 | static char irq_tab[][5] __initdata = { | |
70342287 | 15 | /* INTA INTB INTC INTD */ |
1da177e4 LT |
16 | {0, 0, 0, 0, 0 }, /* 0: GT64120 PCI bridge */ |
17 | {0, 0, 0, 0, 0 }, /* 1: Unused */ | |
18 | {0, 0, 0, 0, 0 }, /* 2: Unused */ | |
19 | {0, 0, 0, 0, 0 }, /* 3: Unused */ | |
20 | {0, 0, 0, 0, 0 }, /* 4: Unused */ | |
21 | {0, 0, 0, 0, 0 }, /* 5: Unused */ | |
22 | {0, 0, 0, 0, 0 }, /* 6: Unused */ | |
23 | {0, 0, 0, 0, 0 }, /* 7: Unused */ | |
24 | {0, 0, 0, 0, 0 }, /* 8: Unused */ | |
25 | {0, 0, 0, 0, 0 }, /* 9: Unused */ | |
70342287 | 26 | {0, 0, 0, 0, PCID }, /* 10: PIIX4 USB */ |
1da177e4 LT |
27 | {0, PCIB, 0, 0, 0 }, /* 11: AMD 79C973 Ethernet */ |
28 | {0, PCIC, 0, 0, 0 }, /* 12: Crystal 4281 Sound */ | |
29 | {0, 0, 0, 0, 0 }, /* 13: Unused */ | |
30 | {0, 0, 0, 0, 0 }, /* 14: Unused */ | |
31 | {0, 0, 0, 0, 0 }, /* 15: Unused */ | |
32 | {0, 0, 0, 0, 0 }, /* 16: Unused */ | |
33 | {0, 0, 0, 0, 0 }, /* 17: Bonito/SOC-it PCI Bridge*/ | |
70342287 RB |
34 | {0, PCIA, PCIB, PCIC, PCID }, /* 18: PCI Slot 1 */ |
35 | {0, PCIB, PCIC, PCID, PCIA }, /* 19: PCI Slot 2 */ | |
36 | {0, PCIC, PCID, PCIA, PCIB }, /* 20: PCI Slot 3 */ | |
1da177e4 LT |
37 | {0, PCID, PCIA, PCIB, PCIC } /* 21: PCI Slot 4 */ |
38 | }; | |
39 | ||
19df0d11 | 40 | int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
1da177e4 LT |
41 | { |
42 | int virq; | |
43 | virq = irq_tab[slot][pin]; | |
44 | return pci_irq[virq]; | |
45 | } | |
46 | ||
47 | /* Do platform specific device initialization at pci_enable_device() time */ | |
48 | int pcibios_plat_dev_init(struct pci_dev *dev) | |
49 | { | |
50 | return 0; | |
51 | } | |
52 | ||
28eb0e46 | 53 | static void malta_piix_func0_fixup(struct pci_dev *pdev) |
1da177e4 LT |
54 | { |
55 | unsigned char reg_val; | |
28eb0e46 | 56 | static int piixirqmap[16] = { /* PIIX PIRQC[A:D] irq mappings */ |
70342287 RB |
57 | 0, 0, 0, 3, |
58 | 4, 5, 6, 7, | |
1da177e4 | 59 | 0, 9, 10, 11, |
42a3b4f2 | 60 | 12, 0, 14, 15 |
1da177e4 LT |
61 | }; |
62 | int i; | |
63 | ||
64 | /* Interrogate PIIX4 to get PCI IRQ mapping */ | |
65 | for (i = 0; i <= 3; i++) { | |
66 | pci_read_config_byte(pdev, 0x60+i, ®_val); | |
67 | if (reg_val & 0x80) | |
68 | pci_irq[PCIA+i] = 0; /* Disabled */ | |
69 | else | |
70 | pci_irq[PCIA+i] = piixirqmap[reg_val & 15]; | |
71 | } | |
72 | ||
73 | /* Done by YAMON 2.00 onwards */ | |
74 | if (PCI_SLOT(pdev->devfn) == 10) { | |
75 | /* | |
76 | * Set top of main memory accessible by ISA or DMA | |
77 | * devices to 16 Mb. | |
78 | */ | |
79 | pci_read_config_byte(pdev, 0x69, ®_val); | |
80 | pci_write_config_byte(pdev, 0x69, reg_val | 0xf0); | |
81 | } | |
82 | } | |
83 | ||
84 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, | |
85 | malta_piix_func0_fixup); | |
86 | ||
28eb0e46 | 87 | static void malta_piix_func1_fixup(struct pci_dev *pdev) |
1da177e4 LT |
88 | { |
89 | unsigned char reg_val; | |
90 | ||
91 | /* Done by YAMON 2.02 onwards */ | |
92 | if (PCI_SLOT(pdev->devfn) == 10) { | |
93 | /* | |
94 | * IDE Decode enable. | |
95 | */ | |
96 | pci_read_config_byte(pdev, 0x41, ®_val); | |
97 | pci_write_config_byte(pdev, 0x41, reg_val|0x80); | |
98 | pci_read_config_byte(pdev, 0x43, ®_val); | |
99 | pci_write_config_byte(pdev, 0x43, reg_val|0x80); | |
100 | } | |
101 | } | |
102 | ||
103 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB, | |
104 | malta_piix_func1_fixup); | |
497e5ff0 RB |
105 | |
106 | /* Enable PCI 2.1 compatibility in PIIX4 */ | |
28eb0e46 | 107 | static void quirk_dlcsetup(struct pci_dev *dev) |
497e5ff0 RB |
108 | { |
109 | u8 odlc, ndlc; | |
110 | ||
111 | (void) pci_read_config_byte(dev, 0x82, &odlc); | |
112 | /* Enable passive releases and delayed transaction */ | |
113 | ndlc = odlc | 7; | |
114 | (void) pci_write_config_byte(dev, 0x82, ndlc); | |
115 | } | |
116 | ||
117 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, | |
118 | quirk_dlcsetup); |