[deliverable/linux.git] / arch / mips / pci / ops-lantiq.c

/*
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License version 2 as published
 *  by the Free Software Foundation.
 *
 *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 */

#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/mm.h>
#include <asm/addrspace.h>
#include <linux/vmalloc.h>

#include <lantiq_soc.h>

#include "pci-lantiq.h"

#define LTQ_PCI_CFG_BUSNUM_SHF 16
#define LTQ_PCI_CFG_DEVNUM_SHF 11
#define LTQ_PCI_CFG_FUNNUM_SHF 8

#define PCI_ACCESS_READ	 0
#define PCI_ACCESS_WRITE 1

static int ltq_pci_config_access(unsigned char access_type, struct pci_bus *bus,
	unsigned int devfn, unsigned int where, u32 *data)
{
	unsigned long cfg_base;
	unsigned long flags;
	u32 temp;

	/* we support slot from 0 to 15 dev_fn & 0x68 (AD29) is the
	   SoC itself */
	if ((bus->number != 0) || ((devfn & 0xf8) > 0x78)
		|| ((devfn & 0xf8) == 0) || ((devfn & 0xf8) == 0x68))
		return 1;

	spin_lock_irqsave(&ebu_lock, flags);

	cfg_base = (unsigned long) ltq_pci_mapped_cfg;
	cfg_base |= (bus->number << LTQ_PCI_CFG_BUSNUM_SHF) | (devfn <<
			LTQ_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);

	/* Perform access */
	if (access_type == PCI_ACCESS_WRITE) {
		ltq_w32(swab32(*data), ((u32 *)cfg_base));
	} else {
		*data = ltq_r32(((u32 *)(cfg_base)));
		*data = swab32(*data);
	}
	wmb();

	/* clean possible Master abort */
	cfg_base = (unsigned long) ltq_pci_mapped_cfg;
	cfg_base |= (0x0 << LTQ_PCI_CFG_FUNNUM_SHF) + 4;
	temp = ltq_r32(((u32 *)(cfg_base)));
	temp = swab32(temp);
	cfg_base = (unsigned long) ltq_pci_mapped_cfg;
	cfg_base |= (0x68 << LTQ_PCI_CFG_FUNNUM_SHF) + 4;
	ltq_w32(temp, ((u32 *)cfg_base));

	spin_unlock_irqrestore(&ebu_lock, flags);

	if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ))
		return 1;

	return 0;
}

int ltq_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn,
	int where, int size, u32 *val)
{
	u32 data = 0;

	if (ltq_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
		return PCIBIOS_DEVICE_NOT_FOUND;

	if (size == 1)
		*val = (data >> ((where & 3) << 3)) & 0xff;
	else if (size == 2)
		*val = (data >> ((where & 3) << 3)) & 0xffff;
	else
		*val = data;

	return PCIBIOS_SUCCESSFUL;
}

int ltq_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn,
	int where, int size, u32 val)
{
	u32 data = 0;

	if (size == 4) {
		data = val;
	} else {
		if (ltq_pci_config_access(PCI_ACCESS_READ, bus,
				devfn, where, &data))
			return PCIBIOS_DEVICE_NOT_FOUND;

		if (size == 1)
			data = (data & ~(0xff << ((where & 3) << 3))) |
				(val << ((where & 3) << 3));
		else if (size == 2)
			data = (data & ~(0xffff << ((where & 3) << 3))) |
				(val << ((where & 3) << 3));
	}

	if (ltq_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
		return PCIBIOS_DEVICE_NOT_FOUND;

	return PCIBIOS_SUCCESSFUL;
}
Commit	Line	Data
e47d4889 JC	1	/*
	2	* This program is free software; you can redistribute it and/or modify it
	3	* under the terms of the GNU General Public License version 2 as published
	4	* by the Free Software Foundation.
	5	*
	6	* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
	7	*/
	8
	9	#include <linux/types.h>
	10	#include <linux/pci.h>
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/delay.h>
	14	#include <linux/mm.h>
	15	#include <asm/addrspace.h>
	16	#include <linux/vmalloc.h>
	17
	18	#include <lantiq_soc.h>
	19
	20	#include "pci-lantiq.h"
	21
	22	#define LTQ_PCI_CFG_BUSNUM_SHF 16
	23	#define LTQ_PCI_CFG_DEVNUM_SHF 11
	24	#define LTQ_PCI_CFG_FUNNUM_SHF 8
	25
70342287	26	#define PCI_ACCESS_READ 0
e47d4889 JC	27	#define PCI_ACCESS_WRITE 1
	28
	29	static int ltq_pci_config_access(unsigned char access_type, struct pci_bus *bus,
	30	unsigned int devfn, unsigned int where, u32 *data)
	31	{
	32	unsigned long cfg_base;
	33	unsigned long flags;
	34	u32 temp;
	35
	36	/* we support slot from 0 to 15 dev_fn & 0x68 (AD29) is the
	37	SoC itself */
	38	if ((bus->number != 0) \|\| ((devfn & 0xf8) > 0x78)
	39	\|\| ((devfn & 0xf8) == 0) \|\| ((devfn & 0xf8) == 0x68))
	40	return 1;
	41
	42	spin_lock_irqsave(&ebu_lock, flags);
	43
	44	cfg_base = (unsigned long) ltq_pci_mapped_cfg;
	45	cfg_base \|= (bus->number << LTQ_PCI_CFG_BUSNUM_SHF) \| (devfn <<
	46	LTQ_PCI_CFG_FUNNUM_SHF) \| (where & ~0x3);
	47
	48	/* Perform access */
	49	if (access_type == PCI_ACCESS_WRITE) {
	50	ltq_w32(swab32(data), ((u32 )cfg_base));
	51	} else {
	52	data = ltq_r32(((u32 )(cfg_base)));
	53	data = swab32(data);
	54	}
	55	wmb();
	56
	57	/* clean possible Master abort */
	58	cfg_base = (unsigned long) ltq_pci_mapped_cfg;
	59	cfg_base \|= (0x0 << LTQ_PCI_CFG_FUNNUM_SHF) + 4;
	60	temp = ltq_r32(((u32 *)(cfg_base)));
	61	temp = swab32(temp);
	62	cfg_base = (unsigned long) ltq_pci_mapped_cfg;
	63	cfg_base \|= (0x68 << LTQ_PCI_CFG_FUNNUM_SHF) + 4;
	64	ltq_w32(temp, ((u32 *)cfg_base));
	65
	66	spin_unlock_irqrestore(&ebu_lock, flags);
	67
	68	if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ))
	69	return 1;
	70
	71	return 0;
	72	}
	73
	74	int ltq_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn,
	75	int where, int size, u32 *val)
	76	{
	77	u32 data = 0;
	78
	79	if (ltq_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
	80	return PCIBIOS_DEVICE_NOT_FOUND;
	81
	82	if (size == 1)
	83	*val = (data >> ((where & 3) << 3)) & 0xff;
	84	else if (size == 2)
	85	*val = (data >> ((where & 3) << 3)) & 0xffff;
	86	else
	87	*val = data;
	88
	89	return PCIBIOS_SUCCESSFUL;
	90	}
91
92	int ltq_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn,
93	int where, int size, u32 val)
94	{
95	u32 data = 0;
96
97	if (size == 4) {
98	data = val;
99	} else {
100	if (ltq_pci_config_access(PCI_ACCESS_READ, bus,
101	devfn, where, &data))
102	return PCIBIOS_DEVICE_NOT_FOUND;
103
104	if (size == 1)
105	data = (data & ~(0xff << ((where & 3) << 3))) \|
106	(val << ((where & 3) << 3));
107	else if (size == 2)
108	data = (data & ~(0xffff << ((where & 3) << 3))) \|
109	(val << ((where & 3) << 3));
110	}
111
112	if (ltq_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
113	return PCIBIOS_DEVICE_NOT_FOUND;
114
115	return PCIBIOS_SUCCESSFUL;
116	}