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dc41f94f AI |
1 | /* |
2 | * Copyright (C) 2001,2002,2005 Broadcom Corporation | |
3 | * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
18 | */ | |
19 | ||
20 | /* | |
21 | * BCM1x80/1x55-specific PCI support | |
22 | * | |
23 | * This module provides the glue between Linux's PCI subsystem | |
24 | * and the hardware. We basically provide glue for accessing | |
25 | * configuration space, and set up the translation for I/O | |
26 | * space accesses. | |
27 | * | |
28 | * To access configuration space, we use ioremap. In the 32-bit | |
29 | * kernel, this consumes either 4 or 8 page table pages, and 16MB of | |
30 | * kernel mapped memory. Hopefully neither of these should be a huge | |
31 | * problem. | |
32 | * | |
33 | * XXX: AT THIS TIME, ONLY the NATIVE PCI-X INTERFACE IS SUPPORTED. | |
34 | */ | |
dc41f94f AI |
35 | #include <linux/types.h> |
36 | #include <linux/pci.h> | |
37 | #include <linux/kernel.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/mm.h> | |
40 | #include <linux/console.h> | |
41 | #include <linux/tty.h> | |
88f02518 | 42 | #include <linux/vt.h> |
dc41f94f AI |
43 | |
44 | #include <asm/sibyte/bcm1480_regs.h> | |
45 | #include <asm/sibyte/bcm1480_scd.h> | |
46 | #include <asm/sibyte/board.h> | |
47 | #include <asm/io.h> | |
48 | ||
49 | /* | |
50 | * Macros for calculating offsets into config space given a device | |
51 | * structure or dev/fun/reg | |
52 | */ | |
21a151d8 RB |
53 | #define CFGOFFSET(bus, devfn, where) (((bus)<<16)+((devfn)<<8)+(where)) |
54 | #define CFGADDR(bus, devfn, where) CFGOFFSET((bus)->number, (devfn), where) | |
dc41f94f AI |
55 | |
56 | static void *cfg_space; | |
57 | ||
70342287 RB |
58 | #define PCI_BUS_ENABLED 1 |
59 | #define PCI_DEVICE_MODE 2 | |
dc41f94f | 60 | |
982f6ffe | 61 | static int bcm1480_bus_status; |
dc41f94f AI |
62 | |
63 | #define PCI_BRIDGE_DEVICE 0 | |
dc41f94f AI |
64 | |
65 | /* | |
66 | * Read/write 32-bit values in config space. | |
67 | */ | |
68 | static inline u32 READCFG32(u32 addr) | |
69 | { | |
70 | return *(u32 *)(cfg_space + (addr&~3)); | |
71 | } | |
72 | ||
73 | static inline void WRITECFG32(u32 addr, u32 data) | |
74 | { | |
75 | *(u32 *)(cfg_space + (addr & ~3)) = data; | |
76 | } | |
77 | ||
19df0d11 | 78 | int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
dc41f94f | 79 | { |
f435a91e RB |
80 | if (pin == 0) |
81 | return -1; | |
82 | ||
83 | return K_BCM1480_INT_PCI_INTA - 1 + pin; | |
dc41f94f AI |
84 | } |
85 | ||
86 | /* Do platform specific device initialization at pci_enable_device() time */ | |
87 | int pcibios_plat_dev_init(struct pci_dev *dev) | |
88 | { | |
89 | return 0; | |
90 | } | |
91 | ||
92 | /* | |
93 | * Some checks before doing config cycles: | |
94 | * In PCI Device Mode, hide everything on bus 0 except the LDT host | |
95 | * bridge. Otherwise, access is controlled by bridge MasterEn bits. | |
96 | */ | |
97 | static int bcm1480_pci_can_access(struct pci_bus *bus, int devfn) | |
98 | { | |
8a1417de AI |
99 | u32 devno; |
100 | ||
dc41f94f AI |
101 | if (!(bcm1480_bus_status & (PCI_BUS_ENABLED | PCI_DEVICE_MODE))) |
102 | return 0; | |
103 | ||
104 | if (bus->number == 0) { | |
8a1417de | 105 | devno = PCI_SLOT(devfn); |
a3dddd56 | 106 | if (bcm1480_bus_status & PCI_DEVICE_MODE) |
dc41f94f AI |
107 | return 0; |
108 | else | |
109 | return 1; | |
110 | } else | |
111 | return 1; | |
112 | } | |
113 | ||
114 | /* | |
115 | * Read/write access functions for various sizes of values | |
116 | * in config space. Return all 1's for disallowed accesses | |
117 | * for a kludgy but adequate simulation of master aborts. | |
118 | */ | |
119 | ||
120 | static int bcm1480_pcibios_read(struct pci_bus *bus, unsigned int devfn, | |
121 | int where, int size, u32 * val) | |
122 | { | |
123 | u32 data = 0; | |
124 | ||
125 | if ((size == 2) && (where & 1)) | |
126 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
127 | else if ((size == 4) && (where & 3)) | |
128 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
129 | ||
130 | if (bcm1480_pci_can_access(bus, devfn)) | |
131 | data = READCFG32(CFGADDR(bus, devfn, where)); | |
132 | else | |
133 | data = 0xFFFFFFFF; | |
134 | ||
135 | if (size == 1) | |
136 | *val = (data >> ((where & 3) << 3)) & 0xff; | |
137 | else if (size == 2) | |
138 | *val = (data >> ((where & 3) << 3)) & 0xffff; | |
139 | else | |
140 | *val = data; | |
141 | ||
142 | return PCIBIOS_SUCCESSFUL; | |
143 | } | |
144 | ||
145 | static int bcm1480_pcibios_write(struct pci_bus *bus, unsigned int devfn, | |
146 | int where, int size, u32 val) | |
147 | { | |
148 | u32 cfgaddr = CFGADDR(bus, devfn, where); | |
149 | u32 data = 0; | |
150 | ||
151 | if ((size == 2) && (where & 1)) | |
152 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
153 | else if ((size == 4) && (where & 3)) | |
154 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
155 | ||
156 | if (!bcm1480_pci_can_access(bus, devfn)) | |
157 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
158 | ||
159 | data = READCFG32(cfgaddr); | |
160 | ||
161 | if (size == 1) | |
162 | data = (data & ~(0xff << ((where & 3) << 3))) | | |
163 | (val << ((where & 3) << 3)); | |
164 | else if (size == 2) | |
165 | data = (data & ~(0xffff << ((where & 3) << 3))) | | |
166 | (val << ((where & 3) << 3)); | |
167 | else | |
168 | data = val; | |
169 | ||
170 | WRITECFG32(cfgaddr, data); | |
171 | ||
172 | return PCIBIOS_SUCCESSFUL; | |
173 | } | |
174 | ||
175 | struct pci_ops bcm1480_pci_ops = { | |
7b09777c RH |
176 | .read = bcm1480_pcibios_read, |
177 | .write = bcm1480_pcibios_write, | |
dc41f94f AI |
178 | }; |
179 | ||
180 | static struct resource bcm1480_mem_resource = { | |
181 | .name = "BCM1480 PCI MEM", | |
07c019bc RB |
182 | .start = A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES, |
183 | .end = A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES + 0xfffffffUL, | |
dc41f94f AI |
184 | .flags = IORESOURCE_MEM, |
185 | }; | |
186 | ||
187 | static struct resource bcm1480_io_resource = { | |
188 | .name = "BCM1480 PCI I/O", | |
cf7b7e0b TB |
189 | .start = A_BCM1480_PHYS_PCI_IO_MATCH_BYTES, |
190 | .end = A_BCM1480_PHYS_PCI_IO_MATCH_BYTES + 0x1ffffffUL, | |
dc41f94f AI |
191 | .flags = IORESOURCE_IO, |
192 | }; | |
193 | ||
194 | struct pci_controller bcm1480_controller = { | |
195 | .pci_ops = &bcm1480_pci_ops, | |
196 | .mem_resource = &bcm1480_mem_resource, | |
197 | .io_resource = &bcm1480_io_resource, | |
70342287 | 198 | .io_offset = A_BCM1480_PHYS_PCI_IO_MATCH_BYTES, |
dc41f94f AI |
199 | }; |
200 | ||
201 | ||
202 | static int __init bcm1480_pcibios_init(void) | |
203 | { | |
204 | uint32_t cmdreg; | |
205 | uint64_t reg; | |
dc41f94f AI |
206 | |
207 | /* CFE will assign PCI resources */ | |
29090606 | 208 | pci_set_flags(PCI_PROBE_ONLY); |
dc41f94f AI |
209 | |
210 | /* Avoid ISA compat ranges. */ | |
211 | PCIBIOS_MIN_IO = 0x00008000UL; | |
212 | PCIBIOS_MIN_MEM = 0x01000000UL; | |
213 | ||
25985edc | 214 | /* Set I/O resource limits. - unlimited for now to accommodate HT */ |
8a1417de AI |
215 | ioport_resource.end = 0xffffffffUL; |
216 | iomem_resource.end = 0xffffffffUL; | |
dc41f94f AI |
217 | |
218 | cfg_space = ioremap(A_BCM1480_PHYS_PCI_CFG_MATCH_BITS, 16*1024*1024); | |
219 | ||
220 | /* | |
221 | * See if the PCI bus has been configured by the firmware. | |
222 | */ | |
8fb303c7 | 223 | reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG)); |
dc41f94f AI |
224 | if (!(reg & M_BCM1480_SYS_PCI_HOST)) { |
225 | bcm1480_bus_status |= PCI_DEVICE_MODE; | |
226 | } else { | |
227 | cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), | |
228 | PCI_COMMAND)); | |
229 | if (!(cmdreg & PCI_COMMAND_MASTER)) { | |
230 | printk | |
70342287 | 231 | ("PCI: Skipping PCI probe. Bus is not initialized.\n"); |
dc41f94f AI |
232 | iounmap(cfg_space); |
233 | return 1; /* XXX */ | |
234 | } | |
235 | bcm1480_bus_status |= PCI_BUS_ENABLED; | |
236 | } | |
237 | ||
cb426248 AI |
238 | /* turn on ExpMemEn */ |
239 | cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40)); | |
cb426248 AI |
240 | WRITECFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40), |
241 | cmdreg | 0x10); | |
242 | cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40)); | |
cb426248 | 243 | |
dc41f94f AI |
244 | /* |
245 | * Establish mappings in KSEG2 (kernel virtual) to PCI I/O | |
246 | * space. Use "match bytes" policy to make everything look | |
247 | * little-endian. So, you need to also set | |
248 | * CONFIG_SWAP_IO_SPACE, but this is the combination that | |
249 | * works correctly with most of Linux's drivers. | |
250 | * XXX ehs: Should this happen in PCI Device mode? | |
251 | */ | |
252 | ||
e790a464 TB |
253 | bcm1480_controller.io_map_base = (unsigned long) |
254 | ioremap(A_BCM1480_PHYS_PCI_IO_MATCH_BYTES, 65536); | |
cf7b7e0b | 255 | bcm1480_controller.io_map_base -= bcm1480_controller.io_offset; |
e790a464 | 256 | set_io_port_base(bcm1480_controller.io_map_base); |
dc41f94f AI |
257 | |
258 | register_pci_controller(&bcm1480_controller); | |
259 | ||
260 | #ifdef CONFIG_VGA_CONSOLE | |
155957f5 WY |
261 | console_lock(); |
262 | do_take_over_console(&vga_con, 0, MAX_NR_CONSOLES-1, 1); | |
263 | console_unlock(); | |
dc41f94f AI |
264 | #endif |
265 | return 0; | |
266 | } | |
267 | ||
268 | arch_initcall(bcm1480_pcibios_init); |