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1 | /* |
2 | * Copyright (C) 2004 by Basler Vision Technologies AG | |
3 | * Author: Thomas Koeller <thomas.koeller@baslerweb.com> | |
4 | * Based on the PMC-Sierra Yosemite board support by Ralf Baechle. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | #include <linux/init.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/types.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/bitops.h> | |
25 | #include <asm/rm9k-ocd.h> | |
26 | #include <excite.h> | |
27 | ||
28 | ||
29 | extern struct pci_ops titan_pci_ops; | |
30 | ||
31 | ||
32 | static struct resource | |
33 | mem_resource = { | |
34 | .name = "PCI memory", | |
35 | .start = EXCITE_PHYS_PCI_MEM, | |
36 | .end = EXCITE_PHYS_PCI_MEM + EXCITE_SIZE_PCI_MEM - 1, | |
37 | .flags = IORESOURCE_MEM | |
38 | }, | |
39 | io_resource = { | |
40 | .name = "PCI I/O", | |
41 | .start = EXCITE_PHYS_PCI_IO, | |
42 | .end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1, | |
43 | .flags = IORESOURCE_IO | |
44 | }; | |
45 | ||
46 | ||
47 | static struct pci_controller bx_controller = { | |
48 | .pci_ops = &titan_pci_ops, | |
49 | .mem_resource = &mem_resource, | |
50 | .mem_offset = 0x00000000UL, | |
51 | .io_resource = &io_resource, | |
52 | .io_offset = 0x00000000UL | |
53 | }; | |
54 | ||
55 | ||
56 | static char | |
57 | iopage_failed[] __initdata = "Cannot allocate PCI I/O page", | |
58 | modebits_no_pci[] __initdata = "PCI is not configured in mode bits"; | |
59 | ||
60 | #define RM9000x2_OCD_HTSC 0x0604 | |
61 | #define RM9000x2_OCD_HTBHL 0x060c | |
62 | #define RM9000x2_OCD_PCIHRST 0x078c | |
63 | ||
64 | #define RM9K_OCD_MODEBIT1 0x00d4 /* (MODEBIT1) Mode Bit 1 */ | |
65 | #define RM9K_OCD_CPHDCR 0x00f4 /* CPU-PCI/HT Data Control. */ | |
66 | ||
67 | #define PCISC_FB2B 0x00000200 | |
68 | #define PCISC_MWICG 0x00000010 | |
69 | #define PCISC_EMC 0x00000004 | |
70 | #define PCISC_ERMA 0x00000002 | |
71 | ||
72 | ||
73 | ||
74 | static int __init basler_excite_pci_setup(void) | |
75 | { | |
76 | const unsigned int fullbars = memsize / (256 << 20); | |
77 | unsigned int i; | |
78 | ||
79 | /* Check modebits to see if PCI is really enabled. */ | |
80 | if (!((ocd_readl(RM9K_OCD_MODEBIT1) >> (47-32)) & 0x1)) | |
81 | panic(modebits_no_pci); | |
82 | ||
83 | if (NULL == request_mem_region(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO, | |
84 | "Memory-mapped PCI I/O page")) | |
85 | panic(iopage_failed); | |
86 | ||
87 | /* Enable PCI 0 as master for config cycles */ | |
88 | ocd_writel(PCISC_EMC | PCISC_ERMA, RM9000x2_OCD_HTSC); | |
89 | ||
90 | ||
91 | /* Set up latency timer */ | |
92 | ocd_writel(0x8008, RM9000x2_OCD_HTBHL); | |
93 | ||
94 | /* Setup host IO and Memory space */ | |
95 | ocd_writel((EXCITE_PHYS_PCI_IO >> 4) | 1, LKB7); | |
96 | ocd_writel(((EXCITE_SIZE_PCI_IO >> 4) & 0x7fffff00) - 0x100, LKM7); | |
97 | ocd_writel((EXCITE_PHYS_PCI_MEM >> 4) | 1, LKB8); | |
98 | ocd_writel(((EXCITE_SIZE_PCI_MEM >> 4) & 0x7fffff00) - 0x100, LKM8); | |
99 | ||
100 | /* Set up PCI BARs to map all installed memory */ | |
101 | for (i = 0; i < 6; i++) { | |
102 | const unsigned int bar = 0x610 + i * 4; | |
103 | ||
104 | if (i < fullbars) { | |
105 | ocd_writel(0x10000000 * i, bar); | |
106 | ocd_writel(0x01000000 * i, bar + 0x140); | |
107 | ocd_writel(0x0ffff029, bar + 0x100); | |
108 | continue; | |
109 | } | |
110 | ||
111 | if (i == fullbars) { | |
112 | int o; | |
113 | u32 mask; | |
114 | ||
115 | const unsigned long rem = memsize - i * 0x10000000; | |
116 | if (!rem) { | |
117 | ocd_writel(0x00000000, bar + 0x100); | |
118 | continue; | |
119 | } | |
120 | ||
121 | o = ffs(rem) - 1; | |
122 | if (rem & ~(0x1 << o)) | |
123 | o++; | |
124 | mask = ((0x1 << o) & 0x0ffff000) - 0x1000; | |
125 | ocd_writel(0x10000000 * i, bar); | |
126 | ocd_writel(0x01000000 * i, bar + 0x140); | |
127 | ocd_writel(0x00000029 | mask, bar + 0x100); | |
128 | continue; | |
129 | } | |
130 | ||
131 | ocd_writel(0x00000000, bar + 0x100); | |
132 | } | |
133 | ||
3a4fa0a2 | 134 | /* Finally, enable the PCI interrupt */ |
35189fad RB |
135 | #if USB_IRQ > 7 |
136 | set_c0_intcontrol(1 << USB_IRQ); | |
137 | #else | |
138 | set_c0_status(1 << (USB_IRQ + 8)); | |
139 | #endif | |
140 | ||
141 | ioport_resource.start = EXCITE_PHYS_PCI_IO; | |
142 | ioport_resource.end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1; | |
143 | set_io_port_base((unsigned long) ioremap_nocache(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO)); | |
144 | register_pci_controller(&bx_controller); | |
145 | return 0; | |
146 | } | |
147 | ||
148 | ||
149 | arch_initcall(basler_excite_pci_setup); |