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e47d4889 JC |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify it | |
3 | * under the terms of the GNU General Public License version 2 as published | |
4 | * by the Free Software Foundation. | |
5 | * | |
97b92108 | 6 | * Copyright (C) 2010 John Crispin <john@phrozen.org> |
e47d4889 JC |
7 | */ |
8 | ||
9 | #include <linux/types.h> | |
10 | #include <linux/pci.h> | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/mm.h> | |
15 | #include <linux/vmalloc.h> | |
57c8cb8f JC |
16 | #include <linux/module.h> |
17 | #include <linux/clk.h> | |
18 | #include <linux/of_platform.h> | |
19 | #include <linux/of_gpio.h> | |
20 | #include <linux/of_irq.h> | |
21 | #include <linux/of_pci.h> | |
e47d4889 | 22 | |
e47d4889 JC |
23 | #include <asm/addrspace.h> |
24 | ||
25 | #include <lantiq_soc.h> | |
26 | #include <lantiq_irq.h> | |
e47d4889 JC |
27 | |
28 | #include "pci-lantiq.h" | |
29 | ||
e47d4889 JC |
30 | #define PCI_CR_FCI_ADDR_MAP0 0x00C0 |
31 | #define PCI_CR_FCI_ADDR_MAP1 0x00C4 | |
32 | #define PCI_CR_FCI_ADDR_MAP2 0x00C8 | |
33 | #define PCI_CR_FCI_ADDR_MAP3 0x00CC | |
34 | #define PCI_CR_FCI_ADDR_MAP4 0x00D0 | |
35 | #define PCI_CR_FCI_ADDR_MAP5 0x00D4 | |
36 | #define PCI_CR_FCI_ADDR_MAP6 0x00D8 | |
37 | #define PCI_CR_FCI_ADDR_MAP7 0x00DC | |
38 | #define PCI_CR_CLK_CTRL 0x0000 | |
39 | #define PCI_CR_PCI_MOD 0x0030 | |
40 | #define PCI_CR_PC_ARB 0x0080 | |
41 | #define PCI_CR_FCI_ADDR_MAP11hg 0x00E4 | |
42 | #define PCI_CR_BAR11MASK 0x0044 | |
43 | #define PCI_CR_BAR12MASK 0x0048 | |
44 | #define PCI_CR_BAR13MASK 0x004C | |
45 | #define PCI_CS_BASE_ADDR1 0x0010 | |
46 | #define PCI_CR_PCI_ADDR_MAP11 0x0064 | |
47 | #define PCI_CR_FCI_BURST_LENGTH 0x00E8 | |
48 | #define PCI_CR_PCI_EOI 0x002C | |
49 | #define PCI_CS_STS_CMD 0x0004 | |
50 | ||
51 | #define PCI_MASTER0_REQ_MASK_2BITS 8 | |
52 | #define PCI_MASTER1_REQ_MASK_2BITS 10 | |
53 | #define PCI_MASTER2_REQ_MASK_2BITS 12 | |
54 | #define INTERNAL_ARB_ENABLE_BIT 0 | |
55 | ||
56 | #define LTQ_CGU_IFCCR 0x0018 | |
57 | #define LTQ_CGU_PCICR 0x0034 | |
58 | ||
59 | #define ltq_pci_w32(x, y) ltq_w32((x), ltq_pci_membase + (y)) | |
60 | #define ltq_pci_r32(x) ltq_r32(ltq_pci_membase + (x)) | |
61 | ||
62 | #define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y)) | |
63 | #define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x)) | |
64 | ||
e47d4889 JC |
65 | __iomem void *ltq_pci_mapped_cfg; |
66 | static __iomem void *ltq_pci_membase; | |
67 | ||
57c8cb8f JC |
68 | static int reset_gpio; |
69 | static struct clk *clk_pci, *clk_external; | |
70 | static struct resource pci_io_resource; | |
71 | static struct resource pci_mem_resource; | |
72 | static struct pci_ops pci_ops = { | |
e47d4889 JC |
73 | .read = ltq_pci_read_config_dword, |
74 | .write = ltq_pci_write_config_dword | |
75 | }; | |
76 | ||
57c8cb8f JC |
77 | static struct pci_controller pci_controller = { |
78 | .pci_ops = &pci_ops, | |
e47d4889 JC |
79 | .mem_resource = &pci_mem_resource, |
80 | .mem_offset = 0x00000000UL, | |
81 | .io_resource = &pci_io_resource, | |
82 | .io_offset = 0x00000000UL, | |
83 | }; | |
84 | ||
57c8cb8f | 85 | static inline u32 ltq_calc_bar11mask(void) |
e47d4889 JC |
86 | { |
87 | u32 mem, bar11mask; | |
88 | ||
89 | /* BAR11MASK value depends on available memory on system. */ | |
1132137e | 90 | mem = get_num_physpages() * PAGE_SIZE; |
e47d4889 JC |
91 | bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8; |
92 | ||
93 | return bar11mask; | |
94 | } | |
95 | ||
28eb0e46 | 96 | static int ltq_pci_startup(struct platform_device *pdev) |
e47d4889 | 97 | { |
57c8cb8f JC |
98 | struct device_node *node = pdev->dev.of_node; |
99 | const __be32 *req_mask, *bus_clk; | |
e47d4889 JC |
100 | u32 temp_buffer; |
101 | ||
57c8cb8f JC |
102 | /* get our clocks */ |
103 | clk_pci = clk_get(&pdev->dev, NULL); | |
104 | if (IS_ERR(clk_pci)) { | |
105 | dev_err(&pdev->dev, "failed to get pci clock\n"); | |
106 | return PTR_ERR(clk_pci); | |
05969546 | 107 | } |
e47d4889 | 108 | |
57c8cb8f JC |
109 | clk_external = clk_get(&pdev->dev, "external"); |
110 | if (IS_ERR(clk_external)) { | |
111 | clk_put(clk_pci); | |
112 | dev_err(&pdev->dev, "failed to get external pci clock\n"); | |
113 | return PTR_ERR(clk_external); | |
e47d4889 JC |
114 | } |
115 | ||
57c8cb8f JC |
116 | /* read the bus speed that we want */ |
117 | bus_clk = of_get_property(node, "lantiq,bus-clock", NULL); | |
118 | if (bus_clk) | |
119 | clk_set_rate(clk_pci, *bus_clk); | |
120 | ||
121 | /* and enable the clocks */ | |
122 | clk_enable(clk_pci); | |
123 | if (of_find_property(node, "lantiq,external-clock", NULL)) | |
124 | clk_enable(clk_external); | |
125 | else | |
126 | clk_disable(clk_external); | |
127 | ||
128 | /* setup reset gpio used by pci */ | |
129 | reset_gpio = of_get_named_gpio(node, "gpio-reset", 0); | |
bae696a2 JC |
130 | if (gpio_is_valid(reset_gpio)) { |
131 | int ret = devm_gpio_request(&pdev->dev, | |
132 | reset_gpio, "pci-reset"); | |
133 | if (ret) { | |
134 | dev_err(&pdev->dev, | |
135 | "failed to request gpio %d\n", reset_gpio); | |
136 | return ret; | |
137 | } | |
138 | gpio_direction_output(reset_gpio, 1); | |
139 | } | |
e47d4889 JC |
140 | |
141 | /* enable auto-switching between PCI and EBU */ | |
142 | ltq_pci_w32(0xa, PCI_CR_CLK_CTRL); | |
143 | ||
144 | /* busy, i.e. configuration is not done, PCI access has to be retried */ | |
145 | ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD); | |
146 | wmb(); | |
147 | /* BUS Master/IO/MEM access */ | |
148 | ltq_pci_cfg_w32(ltq_pci_cfg_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD); | |
149 | ||
150 | /* enable external 2 PCI masters */ | |
151 | temp_buffer = ltq_pci_r32(PCI_CR_PC_ARB); | |
57c8cb8f JC |
152 | /* setup the request mask */ |
153 | req_mask = of_get_property(node, "req-mask", NULL); | |
154 | if (req_mask) | |
155 | temp_buffer &= ~((*req_mask & 0xf) << 16); | |
156 | else | |
157 | temp_buffer &= ~0xf0000; | |
e47d4889 JC |
158 | /* enable internal arbiter */ |
159 | temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT); | |
160 | /* enable internal PCI master reqest */ | |
161 | temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS)); | |
162 | ||
163 | /* enable EBU request */ | |
164 | temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS)); | |
165 | ||
166 | /* enable all external masters request */ | |
167 | temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS)); | |
168 | ltq_pci_w32(temp_buffer, PCI_CR_PC_ARB); | |
169 | wmb(); | |
170 | ||
171 | /* setup BAR memory regions */ | |
172 | ltq_pci_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0); | |
173 | ltq_pci_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1); | |
174 | ltq_pci_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2); | |
175 | ltq_pci_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3); | |
176 | ltq_pci_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4); | |
177 | ltq_pci_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5); | |
178 | ltq_pci_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6); | |
179 | ltq_pci_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7); | |
180 | ltq_pci_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg); | |
181 | ltq_pci_w32(ltq_calc_bar11mask(), PCI_CR_BAR11MASK); | |
182 | ltq_pci_w32(0, PCI_CR_PCI_ADDR_MAP11); | |
183 | ltq_pci_w32(0, PCI_CS_BASE_ADDR1); | |
184 | /* both TX and RX endian swap are enabled */ | |
185 | ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI); | |
186 | wmb(); | |
187 | ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR12MASK) | 0x80000000, | |
188 | PCI_CR_BAR12MASK); | |
189 | ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR13MASK) | 0x80000000, | |
190 | PCI_CR_BAR13MASK); | |
191 | /*use 8 dw burst length */ | |
192 | ltq_pci_w32(0x303, PCI_CR_FCI_BURST_LENGTH); | |
193 | ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD); | |
194 | wmb(); | |
195 | ||
196 | /* setup irq line */ | |
197 | ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_CON) | 0xc, LTQ_EBU_PCC_CON); | |
198 | ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_IEN) | 0x10, LTQ_EBU_PCC_IEN); | |
199 | ||
200 | /* toggle reset pin */ | |
42b14cb0 | 201 | if (gpio_is_valid(reset_gpio)) { |
57c8cb8f JC |
202 | __gpio_set_value(reset_gpio, 0); |
203 | wmb(); | |
204 | mdelay(1); | |
205 | __gpio_set_value(reset_gpio, 1); | |
206 | } | |
e47d4889 JC |
207 | return 0; |
208 | } | |
209 | ||
28eb0e46 | 210 | static int ltq_pci_probe(struct platform_device *pdev) |
e47d4889 | 211 | { |
57c8cb8f | 212 | struct resource *res_cfg, *res_bridge; |
29090606 BH |
213 | |
214 | pci_clear_flags(PCI_PROBE_ONLY); | |
e47d4889 | 215 | |
57c8cb8f | 216 | res_bridge = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
7c390a7e TR |
217 | ltq_pci_membase = devm_ioremap_resource(&pdev->dev, res_bridge); |
218 | if (IS_ERR(ltq_pci_membase)) | |
219 | return PTR_ERR(ltq_pci_membase); | |
57c8cb8f | 220 | |
5a1e73ff | 221 | res_cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
7c390a7e TR |
222 | ltq_pci_mapped_cfg = devm_ioremap_resource(&pdev->dev, res_cfg); |
223 | if (IS_ERR(ltq_pci_mapped_cfg)) | |
224 | return PTR_ERR(ltq_pci_mapped_cfg); | |
57c8cb8f JC |
225 | |
226 | ltq_pci_startup(pdev); | |
227 | ||
228 | pci_load_of_ranges(&pci_controller, pdev->dev.of_node); | |
229 | register_pci_controller(&pci_controller); | |
e47d4889 JC |
230 | return 0; |
231 | } | |
232 | ||
57c8cb8f JC |
233 | static const struct of_device_id ltq_pci_match[] = { |
234 | { .compatible = "lantiq,pci-xway" }, | |
235 | {}, | |
236 | }; | |
237 | MODULE_DEVICE_TABLE(of, ltq_pci_match); | |
238 | ||
239 | static struct platform_driver ltq_pci_driver = { | |
e47d4889 JC |
240 | .probe = ltq_pci_probe, |
241 | .driver = { | |
57c8cb8f | 242 | .name = "pci-xway", |
57c8cb8f | 243 | .of_match_table = ltq_pci_match, |
e47d4889 JC |
244 | }, |
245 | }; | |
246 | ||
247 | int __init pcibios_init(void) | |
248 | { | |
249 | int ret = platform_driver_register(<q_pci_driver); | |
250 | if (ret) | |
57c8cb8f | 251 | pr_info("pci-xway: Error registering platform driver!"); |
e47d4889 JC |
252 | return ret; |
253 | } | |
254 | ||
255 | arch_initcall(pcibios_init); |