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MIPS: Alchemy: Remove unneeded cast removing const
[deliverable/linux.git] / arch / mips / pci / pci-rt3883.c
CommitLineData
12d14e0e
GJ		 1/*
2 * Ralink RT3662/RT3883 SoC PCI support
3 *
4 * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * Parts of this file are based on Ralink's 2.6.21 BSP
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
11 */
12
13#include <linux/types.h>
14#include <linux/pci.h>
15#include <linux/io.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/of_irq.h>
22#include <linux/of_pci.h>
23#include <linux/platform_device.h>
24
25#include <asm/mach-ralink/rt3883.h>
26#include <asm/mach-ralink/ralink_regs.h>
27
28#define RT3883_MEMORY_BASE 0x00000000
29#define RT3883_MEMORY_SIZE 0x02000000
30
31#define RT3883_PCI_REG_PCICFG 0x00
32#define RT3883_PCICFG_P2P_BR_DEVNUM_M 0xf
33#define RT3883_PCICFG_P2P_BR_DEVNUM_S 16
34#define RT3883_PCICFG_PCIRST BIT(1)
35#define RT3883_PCI_REG_PCIRAW 0x04
36#define RT3883_PCI_REG_PCIINT 0x08
37#define RT3883_PCI_REG_PCIENA 0x0c
38
39#define RT3883_PCI_REG_CFGADDR 0x20
40#define RT3883_PCI_REG_CFGDATA 0x24
41#define RT3883_PCI_REG_MEMBASE 0x28
42#define RT3883_PCI_REG_IOBASE 0x2c
43#define RT3883_PCI_REG_ARBCTL 0x80
44
45#define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000)
46#define RT3883_PCI_REG_BAR0SETUP(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10)
47#define RT3883_PCI_REG_IMBASEBAR0(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18)
48#define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30)
49#define RT3883_PCI_REG_CLASS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x34)
50#define RT3883_PCI_REG_SUBID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x38)
51#define RT3883_PCI_REG_STATUS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x50)
52
53#define RT3883_PCI_MODE_NONE 0
54#define RT3883_PCI_MODE_PCI BIT(0)
55#define RT3883_PCI_MODE_PCIE BIT(1)
56#define RT3883_PCI_MODE_BOTH (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE)
57
58#define RT3883_PCI_IRQ_COUNT 32
59
60#define RT3883_P2P_BR_DEVNUM 1
61
62struct rt3883_pci_controller {
63 void __iomem *base;
12d14e0e
GJ		 64
65 struct device_node *intc_of_node;
66 struct irq_domain *irq_domain;
67
68 struct pci_controller pci_controller;
69 struct resource io_res;
70 struct resource mem_res;
71
72 bool pcie_ready;
73};
74
75static inline struct rt3883_pci_controller *
76pci_bus_to_rt3883_controller(struct pci_bus *bus)
77{
78 struct pci_controller *hose;
79
80 hose = (struct pci_controller *) bus->sysdata;
81 return container_of(hose, struct rt3883_pci_controller, pci_controller);
82}
83
84static inline u32 rt3883_pci_r32(struct rt3883_pci_controller *rpc,
85 unsigned reg)
86{
87 return ioread32(rpc->base + reg);
88}
89
90static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc,
91 u32 val, unsigned reg)
92{
93 iowrite32(val, rpc->base + reg);
94}
95
96static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
97 unsigned int func, unsigned int where)
98{
99 return (bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
100 0x80000000;
101}
102
103static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc,
104 unsigned bus, unsigned slot,
105 unsigned func, unsigned reg)
106{
107 unsigned long flags;
108 u32 address;
109 u32 ret;
110
111 address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
112
12d14e0e
GJ		 113 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
114 ret = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
12d14e0e
GJ		 115
116 return ret;
117}
118
119static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc,
120 unsigned bus, unsigned slot,
121 unsigned func, unsigned reg, u32 val)
122{
123 unsigned long flags;
124 u32 address;
125
126 address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
127
12d14e0e
GJ		 128 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
129 rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA);
12d14e0e
GJ		 130}
131
132static void rt3883_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
133{
134 struct rt3883_pci_controller *rpc;
135 u32 pending;
136
137 rpc = irq_get_handler_data(irq);
138
139 pending = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIINT) &
140 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
141
142 if (!pending) {
143 spurious_interrupt();
144 return;
145 }
146
147 while (pending) {
148 unsigned bit = __ffs(pending);
149
150 irq = irq_find_mapping(rpc->irq_domain, bit);
151 generic_handle_irq(irq);
152
153 pending &= ~BIT(bit);
154 }
155}
156
157static void rt3883_pci_irq_unmask(struct irq_data *d)
158{
159 struct rt3883_pci_controller *rpc;
160 u32 t;
161
162 rpc = irq_data_get_irq_chip_data(d);
163
164 t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
165 rt3883_pci_w32(rpc, t | BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
166 /* flush write */
167 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
168}
169
170static void rt3883_pci_irq_mask(struct irq_data *d)
171{
172 struct rt3883_pci_controller *rpc;
173 u32 t;
174
175 rpc = irq_data_get_irq_chip_data(d);
176
177 t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
178 rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
179 /* flush write */
180 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
181}
182
183static struct irq_chip rt3883_pci_irq_chip = {
184 .name = "RT3883 PCI",
185 .irq_mask = rt3883_pci_irq_mask,
186 .irq_unmask = rt3883_pci_irq_unmask,
187 .irq_mask_ack = rt3883_pci_irq_mask,
188};
189
190static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq,
191 irq_hw_number_t hw)
192{
193 irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq);
194 irq_set_chip_data(irq, d->host_data);
195
196 return 0;
197}
198
199static const struct irq_domain_ops rt3883_pci_irq_domain_ops = {
200 .map = rt3883_pci_irq_map,
201 .xlate = irq_domain_xlate_onecell,
202};
203
204static int rt3883_pci_irq_init(struct device *dev,
205 struct rt3883_pci_controller *rpc)
206{
207 int irq;
208
209 irq = irq_of_parse_and_map(rpc->intc_of_node, 0);
210 if (irq == 0) {
211 dev_err(dev, "%s has no IRQ",
212 of_node_full_name(rpc->intc_of_node));
213 return -EINVAL;
214 }
215
216 /* disable all interrupts */
217 rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA);
218
219 rpc->irq_domain =
220 irq_domain_add_linear(rpc->intc_of_node, RT3883_PCI_IRQ_COUNT,
221 &rt3883_pci_irq_domain_ops,
222 rpc);
223 if (!rpc->irq_domain) {
224 dev_err(dev, "unable to add IRQ domain\n");
225 return -ENODEV;
226 }
227
228 irq_set_handler_data(irq, rpc);
229 irq_set_chained_handler(irq, rt3883_pci_irq_handler);
230
231 return 0;
232}
233
234static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
235 int where, int size, u32 *val)
236{
237 struct rt3883_pci_controller *rpc;
238 unsigned long flags;
239 u32 address;
240 u32 data;
241
242 rpc = pci_bus_to_rt3883_controller(bus);
243
244 if (!rpc->pcie_ready && bus->number == 1)
245 return PCIBIOS_DEVICE_NOT_FOUND;
246
247 address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
248 PCI_FUNC(devfn), where);
249
12d14e0e
GJ		 250 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
251 data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
12d14e0e
GJ		 252
253 switch (size) {
254 case 1:
255 *val = (data >> ((where & 3) << 3)) & 0xff;
256 break;
257 case 2:
258 *val = (data >> ((where & 3) << 3)) & 0xffff;
259 break;
260 case 4:
261 *val = data;
262 break;
263 }
264
265 return PCIBIOS_SUCCESSFUL;
266}
267
268static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
269 int where, int size, u32 val)
270{
271 struct rt3883_pci_controller *rpc;
272 unsigned long flags;
273 u32 address;
274 u32 data;
275
276 rpc = pci_bus_to_rt3883_controller(bus);
277
278 if (!rpc->pcie_ready && bus->number == 1)
279 return PCIBIOS_DEVICE_NOT_FOUND;
280
281 address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
282 PCI_FUNC(devfn), where);
283
12d14e0e
GJ		 284 rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
285 data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
286
287 switch (size) {
288 case 1:
289 data = (data & ~(0xff << ((where & 3) << 3))) |
290 (val << ((where & 3) << 3));
291 break;
292 case 2:
293 data = (data & ~(0xffff << ((where & 3) << 3))) |
294 (val << ((where & 3) << 3));
295 break;
296 case 4:
297 data = val;
298 break;
299 }
300
301 rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA);
12d14e0e
GJ		 302
303 return PCIBIOS_SUCCESSFUL;
304}
305
306static struct pci_ops rt3883_pci_ops = {
307 .read = rt3883_pci_config_read,
308 .write = rt3883_pci_config_write,
309};
310
311static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode)
312{
313 u32 syscfg1;
314 u32 rstctrl;
315 u32 clkcfg1;
316 u32 t;
317
318 rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
319 syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
320 clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
321
322 if (mode & RT3883_PCI_MODE_PCIE) {
323 rstctrl |= RT3883_RSTCTRL_PCIE;
324 rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
325
326 /* setup PCI PAD drive mode */
327 syscfg1 &= ~(0x30);
328 syscfg1 |= (2 << 4);
329 rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
330
331 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
332 t &= ~BIT(31);
333 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
334
335 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
336 t &= 0x80ffffff;
337 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
338
339 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
340 t |= 0xa << 24;
341 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
342
343 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
344 t |= BIT(31);
345 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
346
347 msleep(50);
348
349 rstctrl &= ~RT3883_RSTCTRL_PCIE;
350 rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
351 }
352
353 syscfg1 |= (RT3883_SYSCFG1_PCIE_RC_MODE | RT3883_SYSCFG1_PCI_HOST_MODE);
354
355 clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | RT3883_CLKCFG1_PCIE_CLK_EN);
356
357 if (mode & RT3883_PCI_MODE_PCI) {
358 clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN;
359 rstctrl &= ~RT3883_RSTCTRL_PCI;
360 }
361
362 if (mode & RT3883_PCI_MODE_PCIE) {
363 clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN;
364 rstctrl &= ~RT3883_RSTCTRL_PCIE;
365 }
366
367 rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
368 rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
369 rt_sysc_w32(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
370
371 msleep(500);
372
373 /*
374 * setup the device number of the P2P bridge
375 * and de-assert the reset line
376 */
377 t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S);
378 rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG);
379
380 /* flush write */
381 rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG);
382 msleep(500);
383
384 if (mode & RT3883_PCI_MODE_PCIE) {
385 msleep(500);
386
387 t = rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(1));
388
389 rpc->pcie_ready = t & BIT(0);
390
391 if (!rpc->pcie_ready) {
392 /* reset the PCIe block */
393 t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
394 t |= RT3883_RSTCTRL_PCIE;
395 rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
396 t &= ~RT3883_RSTCTRL_PCIE;
397 rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
398
399 /* turn off PCIe clock */
400 t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
401 t &= ~RT3883_CLKCFG1_PCIE_CLK_EN;
402 rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1);
403
404 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
405 t &= ~0xf000c080;
406 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
407 }
408 }
409
410 /* enable PCI arbiter */
411 rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL);
412}
413
414static int rt3883_pci_probe(struct platform_device *pdev)
415{
416 struct rt3883_pci_controller *rpc;
417 struct device *dev = &pdev->dev;
418 struct device_node *np = dev->of_node;
419 struct resource *res;
420 struct device_node *child;
421 u32 val;
422 int err;
423 int mode;
424
425 rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL);
426 if (!rpc)
427 return -ENOMEM;
428
429 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
12d14e0e
GJ		 430 rpc->base = devm_ioremap_resource(dev, res);
431 if (IS_ERR(rpc->base))
432 return PTR_ERR(rpc->base);
433
434 /* find the interrupt controller child node */
435 for_each_child_of_node(np, child) {
436 if (of_get_property(child, "interrupt-controller", NULL) &&
437 of_node_get(child)) {
438 rpc->intc_of_node = child;
439 break;
440 }
441 }
442
443 if (!rpc->intc_of_node) {
444 dev_err(dev, "%s has no %s child node",
445 of_node_full_name(rpc->intc_of_node),
446 "interrupt controller");
447 return -EINVAL;
448 }
449
450 /* find the PCI host bridge child node */
451 for_each_child_of_node(np, child) {
452 if (child->type &&
453 of_node_cmp(child->type, "pci") == 0 &&
454 of_node_get(child)) {
455 rpc->pci_controller.of_node = child;
456 break;
457 }
458 }
459
460 if (!rpc->pci_controller.of_node) {
461 dev_err(dev, "%s has no %s child node",
462 of_node_full_name(rpc->intc_of_node),
463 "PCI host bridge");
464 err = -EINVAL;
465 goto err_put_intc_node;
466 }
467
468 mode = RT3883_PCI_MODE_NONE;
469 for_each_available_child_of_node(rpc->pci_controller.of_node, child) {
470 int devfn;
471
472 if (!child->type ||
473 of_node_cmp(child->type, "pci") != 0)
474 continue;
475
476 devfn = of_pci_get_devfn(child);
477 if (devfn < 0)
478 continue;
479
480 switch (PCI_SLOT(devfn)) {
481 case 1:
482 mode |= RT3883_PCI_MODE_PCIE;
483 break;
484
485 case 17:
486 case 18:
487 mode |= RT3883_PCI_MODE_PCI;
488 break;
489 }
490 }
491
492 if (mode == RT3883_PCI_MODE_NONE) {
493 dev_err(dev, "unable to determine PCI mode\n");
494 err = -EINVAL;
495 goto err_put_hb_node;
496 }
497
498 dev_info(dev, "mode:%s%s\n",
499 (mode & RT3883_PCI_MODE_PCI) ? " PCI" : "",
500 (mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : "");
501
502 rt3883_pci_preinit(rpc, mode);
503
504 rpc->pci_controller.pci_ops = &rt3883_pci_ops;
505 rpc->pci_controller.io_resource = &rpc->io_res;
506 rpc->pci_controller.mem_resource = &rpc->mem_res;
507
508 /* Load PCI I/O and memory resources from DT */
509 pci_load_of_ranges(&rpc->pci_controller,
510 rpc->pci_controller.of_node);
511
512 rt3883_pci_w32(rpc, rpc->mem_res.start, RT3883_PCI_REG_MEMBASE);
513 rt3883_pci_w32(rpc, rpc->io_res.start, RT3883_PCI_REG_IOBASE);
514
515 ioport_resource.start = rpc->io_res.start;
516 ioport_resource.end = rpc->io_res.end;
517
518 /* PCI */
519 rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0));
520 rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0));
521 rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0));
522 rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0));
523 rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0));
524
525 /* PCIe */
526 rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1));
527 rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1));
528 rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1));
529 rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1));
530 rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(1));
531
532 err = rt3883_pci_irq_init(dev, rpc);
533 if (err)
534 goto err_put_hb_node;
535
536 /* PCIe */
537 val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND);
538 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
539 rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val);
540
541 /* PCI */
542 val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND);
543 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
544 rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val);
545
546 if (mode == RT3883_PCI_MODE_PCIE) {
547 rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0));
548 rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1));
549
550 rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
551 PCI_BASE_ADDRESS_0,
552 RT3883_MEMORY_BASE);
553 /* flush write */
554 rt3883_pci_read_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
555 PCI_BASE_ADDRESS_0);
556 } else {
557 rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
558 PCI_IO_BASE, 0x00000101);
559 }
560
561 register_pci_controller(&rpc->pci_controller);
562
563 return 0;
564
565err_put_hb_node:
566 of_node_put(rpc->pci_controller.of_node);
567err_put_intc_node:
568 of_node_put(rpc->intc_of_node);
569 return err;
570}
571
572int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
573{
16b84e5a 574 return of_irq_parse_and_map_pci(dev, slot, pin);
12d14e0e
GJ		 575}
576
577int pcibios_plat_dev_init(struct pci_dev *dev)
578{
579 return 0;
580}
581
582static const struct of_device_id rt3883_pci_ids[] = {
583 { .compatible = "ralink,rt3883-pci" },
584 {},
585};
586MODULE_DEVICE_TABLE(of, rt3883_pci_ids);
587
588static struct platform_driver rt3883_pci_driver = {
589 .probe = rt3883_pci_probe,
590 .driver = {
591 .name = "rt3883-pci",
12d14e0e
GJ		 592 .of_match_table = of_match_ptr(rt3883_pci_ids),
593 },
594};
595
596static int __init rt3883_pci_init(void)
597{
598 return platform_driver_register(&rt3883_pci_driver);
599}
600
601postcore_initcall(rt3883_pci_init);
Linux kernel - Deliverables
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