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12d14e0e GJ |
1 | /* |
2 | * Ralink RT3662/RT3883 SoC PCI support | |
3 | * | |
4 | * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org> | |
5 | * | |
6 | * Parts of this file are based on Ralink's 2.6.21 BSP | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License version 2 as published | |
10 | * by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/types.h> | |
14 | #include <linux/pci.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/of.h> | |
21 | #include <linux/of_irq.h> | |
22 | #include <linux/of_pci.h> | |
23 | #include <linux/platform_device.h> | |
24 | ||
25 | #include <asm/mach-ralink/rt3883.h> | |
26 | #include <asm/mach-ralink/ralink_regs.h> | |
27 | ||
28 | #define RT3883_MEMORY_BASE 0x00000000 | |
29 | #define RT3883_MEMORY_SIZE 0x02000000 | |
30 | ||
31 | #define RT3883_PCI_REG_PCICFG 0x00 | |
32 | #define RT3883_PCICFG_P2P_BR_DEVNUM_M 0xf | |
33 | #define RT3883_PCICFG_P2P_BR_DEVNUM_S 16 | |
34 | #define RT3883_PCICFG_PCIRST BIT(1) | |
35 | #define RT3883_PCI_REG_PCIRAW 0x04 | |
36 | #define RT3883_PCI_REG_PCIINT 0x08 | |
37 | #define RT3883_PCI_REG_PCIENA 0x0c | |
38 | ||
39 | #define RT3883_PCI_REG_CFGADDR 0x20 | |
40 | #define RT3883_PCI_REG_CFGDATA 0x24 | |
41 | #define RT3883_PCI_REG_MEMBASE 0x28 | |
42 | #define RT3883_PCI_REG_IOBASE 0x2c | |
43 | #define RT3883_PCI_REG_ARBCTL 0x80 | |
44 | ||
45 | #define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000) | |
46 | #define RT3883_PCI_REG_BAR0SETUP(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10) | |
47 | #define RT3883_PCI_REG_IMBASEBAR0(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18) | |
48 | #define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30) | |
49 | #define RT3883_PCI_REG_CLASS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x34) | |
50 | #define RT3883_PCI_REG_SUBID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x38) | |
51 | #define RT3883_PCI_REG_STATUS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x50) | |
52 | ||
53 | #define RT3883_PCI_MODE_NONE 0 | |
54 | #define RT3883_PCI_MODE_PCI BIT(0) | |
55 | #define RT3883_PCI_MODE_PCIE BIT(1) | |
56 | #define RT3883_PCI_MODE_BOTH (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE) | |
57 | ||
58 | #define RT3883_PCI_IRQ_COUNT 32 | |
59 | ||
60 | #define RT3883_P2P_BR_DEVNUM 1 | |
61 | ||
62 | struct rt3883_pci_controller { | |
63 | void __iomem *base; | |
12d14e0e GJ |
64 | |
65 | struct device_node *intc_of_node; | |
66 | struct irq_domain *irq_domain; | |
67 | ||
68 | struct pci_controller pci_controller; | |
69 | struct resource io_res; | |
70 | struct resource mem_res; | |
71 | ||
72 | bool pcie_ready; | |
73 | }; | |
74 | ||
75 | static inline struct rt3883_pci_controller * | |
76 | pci_bus_to_rt3883_controller(struct pci_bus *bus) | |
77 | { | |
78 | struct pci_controller *hose; | |
79 | ||
80 | hose = (struct pci_controller *) bus->sysdata; | |
81 | return container_of(hose, struct rt3883_pci_controller, pci_controller); | |
82 | } | |
83 | ||
84 | static inline u32 rt3883_pci_r32(struct rt3883_pci_controller *rpc, | |
85 | unsigned reg) | |
86 | { | |
87 | return ioread32(rpc->base + reg); | |
88 | } | |
89 | ||
90 | static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc, | |
91 | u32 val, unsigned reg) | |
92 | { | |
93 | iowrite32(val, rpc->base + reg); | |
94 | } | |
95 | ||
96 | static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot, | |
97 | unsigned int func, unsigned int where) | |
98 | { | |
99 | return (bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | | |
100 | 0x80000000; | |
101 | } | |
102 | ||
103 | static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc, | |
104 | unsigned bus, unsigned slot, | |
105 | unsigned func, unsigned reg) | |
106 | { | |
107 | unsigned long flags; | |
108 | u32 address; | |
109 | u32 ret; | |
110 | ||
111 | address = rt3883_pci_get_cfgaddr(bus, slot, func, reg); | |
112 | ||
12d14e0e GJ |
113 | rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); |
114 | ret = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA); | |
12d14e0e GJ |
115 | |
116 | return ret; | |
117 | } | |
118 | ||
119 | static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc, | |
120 | unsigned bus, unsigned slot, | |
121 | unsigned func, unsigned reg, u32 val) | |
122 | { | |
123 | unsigned long flags; | |
124 | u32 address; | |
125 | ||
126 | address = rt3883_pci_get_cfgaddr(bus, slot, func, reg); | |
127 | ||
12d14e0e GJ |
128 | rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); |
129 | rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA); | |
12d14e0e GJ |
130 | } |
131 | ||
132 | static void rt3883_pci_irq_handler(unsigned int irq, struct irq_desc *desc) | |
133 | { | |
134 | struct rt3883_pci_controller *rpc; | |
135 | u32 pending; | |
136 | ||
25aae561 | 137 | rpc = irq_desc_get_handler_data(desc); |
12d14e0e GJ |
138 | |
139 | pending = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIINT) & | |
140 | rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); | |
141 | ||
142 | if (!pending) { | |
143 | spurious_interrupt(); | |
144 | return; | |
145 | } | |
146 | ||
147 | while (pending) { | |
148 | unsigned bit = __ffs(pending); | |
149 | ||
150 | irq = irq_find_mapping(rpc->irq_domain, bit); | |
151 | generic_handle_irq(irq); | |
152 | ||
153 | pending &= ~BIT(bit); | |
154 | } | |
155 | } | |
156 | ||
157 | static void rt3883_pci_irq_unmask(struct irq_data *d) | |
158 | { | |
159 | struct rt3883_pci_controller *rpc; | |
160 | u32 t; | |
161 | ||
162 | rpc = irq_data_get_irq_chip_data(d); | |
163 | ||
164 | t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); | |
165 | rt3883_pci_w32(rpc, t | BIT(d->hwirq), RT3883_PCI_REG_PCIENA); | |
166 | /* flush write */ | |
167 | rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); | |
168 | } | |
169 | ||
170 | static void rt3883_pci_irq_mask(struct irq_data *d) | |
171 | { | |
172 | struct rt3883_pci_controller *rpc; | |
173 | u32 t; | |
174 | ||
175 | rpc = irq_data_get_irq_chip_data(d); | |
176 | ||
177 | t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); | |
178 | rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA); | |
179 | /* flush write */ | |
180 | rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA); | |
181 | } | |
182 | ||
183 | static struct irq_chip rt3883_pci_irq_chip = { | |
184 | .name = "RT3883 PCI", | |
185 | .irq_mask = rt3883_pci_irq_mask, | |
186 | .irq_unmask = rt3883_pci_irq_unmask, | |
187 | .irq_mask_ack = rt3883_pci_irq_mask, | |
188 | }; | |
189 | ||
190 | static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq, | |
191 | irq_hw_number_t hw) | |
192 | { | |
193 | irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq); | |
194 | irq_set_chip_data(irq, d->host_data); | |
195 | ||
196 | return 0; | |
197 | } | |
198 | ||
199 | static const struct irq_domain_ops rt3883_pci_irq_domain_ops = { | |
200 | .map = rt3883_pci_irq_map, | |
201 | .xlate = irq_domain_xlate_onecell, | |
202 | }; | |
203 | ||
204 | static int rt3883_pci_irq_init(struct device *dev, | |
205 | struct rt3883_pci_controller *rpc) | |
206 | { | |
207 | int irq; | |
208 | ||
209 | irq = irq_of_parse_and_map(rpc->intc_of_node, 0); | |
210 | if (irq == 0) { | |
211 | dev_err(dev, "%s has no IRQ", | |
212 | of_node_full_name(rpc->intc_of_node)); | |
213 | return -EINVAL; | |
214 | } | |
215 | ||
216 | /* disable all interrupts */ | |
217 | rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA); | |
218 | ||
219 | rpc->irq_domain = | |
220 | irq_domain_add_linear(rpc->intc_of_node, RT3883_PCI_IRQ_COUNT, | |
221 | &rt3883_pci_irq_domain_ops, | |
222 | rpc); | |
223 | if (!rpc->irq_domain) { | |
224 | dev_err(dev, "unable to add IRQ domain\n"); | |
225 | return -ENODEV; | |
226 | } | |
227 | ||
586134a8 | 228 | irq_set_chained_handler_and_data(irq, rt3883_pci_irq_handler, rpc); |
12d14e0e GJ |
229 | |
230 | return 0; | |
231 | } | |
232 | ||
233 | static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn, | |
234 | int where, int size, u32 *val) | |
235 | { | |
236 | struct rt3883_pci_controller *rpc; | |
237 | unsigned long flags; | |
238 | u32 address; | |
239 | u32 data; | |
240 | ||
241 | rpc = pci_bus_to_rt3883_controller(bus); | |
242 | ||
243 | if (!rpc->pcie_ready && bus->number == 1) | |
244 | return PCIBIOS_DEVICE_NOT_FOUND; | |
245 | ||
246 | address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), | |
247 | PCI_FUNC(devfn), where); | |
248 | ||
12d14e0e GJ |
249 | rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); |
250 | data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA); | |
12d14e0e GJ |
251 | |
252 | switch (size) { | |
253 | case 1: | |
254 | *val = (data >> ((where & 3) << 3)) & 0xff; | |
255 | break; | |
256 | case 2: | |
257 | *val = (data >> ((where & 3) << 3)) & 0xffff; | |
258 | break; | |
259 | case 4: | |
260 | *val = data; | |
261 | break; | |
262 | } | |
263 | ||
264 | return PCIBIOS_SUCCESSFUL; | |
265 | } | |
266 | ||
267 | static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn, | |
268 | int where, int size, u32 val) | |
269 | { | |
270 | struct rt3883_pci_controller *rpc; | |
271 | unsigned long flags; | |
272 | u32 address; | |
273 | u32 data; | |
274 | ||
275 | rpc = pci_bus_to_rt3883_controller(bus); | |
276 | ||
277 | if (!rpc->pcie_ready && bus->number == 1) | |
278 | return PCIBIOS_DEVICE_NOT_FOUND; | |
279 | ||
280 | address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), | |
281 | PCI_FUNC(devfn), where); | |
282 | ||
12d14e0e GJ |
283 | rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR); |
284 | data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA); | |
285 | ||
286 | switch (size) { | |
287 | case 1: | |
288 | data = (data & ~(0xff << ((where & 3) << 3))) | | |
289 | (val << ((where & 3) << 3)); | |
290 | break; | |
291 | case 2: | |
292 | data = (data & ~(0xffff << ((where & 3) << 3))) | | |
293 | (val << ((where & 3) << 3)); | |
294 | break; | |
295 | case 4: | |
296 | data = val; | |
297 | break; | |
298 | } | |
299 | ||
300 | rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA); | |
12d14e0e GJ |
301 | |
302 | return PCIBIOS_SUCCESSFUL; | |
303 | } | |
304 | ||
305 | static struct pci_ops rt3883_pci_ops = { | |
306 | .read = rt3883_pci_config_read, | |
307 | .write = rt3883_pci_config_write, | |
308 | }; | |
309 | ||
310 | static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode) | |
311 | { | |
312 | u32 syscfg1; | |
313 | u32 rstctrl; | |
314 | u32 clkcfg1; | |
315 | u32 t; | |
316 | ||
317 | rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL); | |
318 | syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1); | |
319 | clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1); | |
320 | ||
321 | if (mode & RT3883_PCI_MODE_PCIE) { | |
322 | rstctrl |= RT3883_RSTCTRL_PCIE; | |
323 | rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL); | |
324 | ||
325 | /* setup PCI PAD drive mode */ | |
326 | syscfg1 &= ~(0x30); | |
327 | syscfg1 |= (2 << 4); | |
328 | rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1); | |
329 | ||
330 | t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); | |
331 | t &= ~BIT(31); | |
332 | rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0); | |
333 | ||
334 | t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1); | |
335 | t &= 0x80ffffff; | |
336 | rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1); | |
337 | ||
338 | t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1); | |
339 | t |= 0xa << 24; | |
340 | rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1); | |
341 | ||
342 | t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); | |
343 | t |= BIT(31); | |
344 | rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0); | |
345 | ||
346 | msleep(50); | |
347 | ||
348 | rstctrl &= ~RT3883_RSTCTRL_PCIE; | |
349 | rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL); | |
350 | } | |
351 | ||
352 | syscfg1 |= (RT3883_SYSCFG1_PCIE_RC_MODE | RT3883_SYSCFG1_PCI_HOST_MODE); | |
353 | ||
354 | clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | RT3883_CLKCFG1_PCIE_CLK_EN); | |
355 | ||
356 | if (mode & RT3883_PCI_MODE_PCI) { | |
357 | clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN; | |
358 | rstctrl &= ~RT3883_RSTCTRL_PCI; | |
359 | } | |
360 | ||
361 | if (mode & RT3883_PCI_MODE_PCIE) { | |
362 | clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN; | |
363 | rstctrl &= ~RT3883_RSTCTRL_PCIE; | |
364 | } | |
365 | ||
366 | rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1); | |
367 | rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL); | |
368 | rt_sysc_w32(clkcfg1, RT3883_SYSC_REG_CLKCFG1); | |
369 | ||
370 | msleep(500); | |
371 | ||
372 | /* | |
373 | * setup the device number of the P2P bridge | |
374 | * and de-assert the reset line | |
375 | */ | |
376 | t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S); | |
377 | rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG); | |
378 | ||
379 | /* flush write */ | |
380 | rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG); | |
381 | msleep(500); | |
382 | ||
383 | if (mode & RT3883_PCI_MODE_PCIE) { | |
384 | msleep(500); | |
385 | ||
386 | t = rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(1)); | |
387 | ||
388 | rpc->pcie_ready = t & BIT(0); | |
389 | ||
390 | if (!rpc->pcie_ready) { | |
391 | /* reset the PCIe block */ | |
392 | t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL); | |
393 | t |= RT3883_RSTCTRL_PCIE; | |
394 | rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL); | |
395 | t &= ~RT3883_RSTCTRL_PCIE; | |
396 | rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL); | |
397 | ||
398 | /* turn off PCIe clock */ | |
399 | t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1); | |
400 | t &= ~RT3883_CLKCFG1_PCIE_CLK_EN; | |
401 | rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1); | |
402 | ||
403 | t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0); | |
404 | t &= ~0xf000c080; | |
405 | rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0); | |
406 | } | |
407 | } | |
408 | ||
409 | /* enable PCI arbiter */ | |
410 | rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL); | |
411 | } | |
412 | ||
413 | static int rt3883_pci_probe(struct platform_device *pdev) | |
414 | { | |
415 | struct rt3883_pci_controller *rpc; | |
416 | struct device *dev = &pdev->dev; | |
417 | struct device_node *np = dev->of_node; | |
418 | struct resource *res; | |
419 | struct device_node *child; | |
420 | u32 val; | |
421 | int err; | |
422 | int mode; | |
423 | ||
424 | rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL); | |
425 | if (!rpc) | |
426 | return -ENOMEM; | |
427 | ||
428 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
12d14e0e GJ |
429 | rpc->base = devm_ioremap_resource(dev, res); |
430 | if (IS_ERR(rpc->base)) | |
431 | return PTR_ERR(rpc->base); | |
432 | ||
433 | /* find the interrupt controller child node */ | |
434 | for_each_child_of_node(np, child) { | |
435 | if (of_get_property(child, "interrupt-controller", NULL) && | |
436 | of_node_get(child)) { | |
437 | rpc->intc_of_node = child; | |
438 | break; | |
439 | } | |
440 | } | |
441 | ||
442 | if (!rpc->intc_of_node) { | |
443 | dev_err(dev, "%s has no %s child node", | |
444 | of_node_full_name(rpc->intc_of_node), | |
445 | "interrupt controller"); | |
446 | return -EINVAL; | |
447 | } | |
448 | ||
449 | /* find the PCI host bridge child node */ | |
450 | for_each_child_of_node(np, child) { | |
451 | if (child->type && | |
452 | of_node_cmp(child->type, "pci") == 0 && | |
453 | of_node_get(child)) { | |
454 | rpc->pci_controller.of_node = child; | |
455 | break; | |
456 | } | |
457 | } | |
458 | ||
459 | if (!rpc->pci_controller.of_node) { | |
460 | dev_err(dev, "%s has no %s child node", | |
461 | of_node_full_name(rpc->intc_of_node), | |
462 | "PCI host bridge"); | |
463 | err = -EINVAL; | |
464 | goto err_put_intc_node; | |
465 | } | |
466 | ||
467 | mode = RT3883_PCI_MODE_NONE; | |
468 | for_each_available_child_of_node(rpc->pci_controller.of_node, child) { | |
469 | int devfn; | |
470 | ||
471 | if (!child->type || | |
472 | of_node_cmp(child->type, "pci") != 0) | |
473 | continue; | |
474 | ||
475 | devfn = of_pci_get_devfn(child); | |
476 | if (devfn < 0) | |
477 | continue; | |
478 | ||
479 | switch (PCI_SLOT(devfn)) { | |
480 | case 1: | |
481 | mode |= RT3883_PCI_MODE_PCIE; | |
482 | break; | |
483 | ||
484 | case 17: | |
485 | case 18: | |
486 | mode |= RT3883_PCI_MODE_PCI; | |
487 | break; | |
488 | } | |
489 | } | |
490 | ||
491 | if (mode == RT3883_PCI_MODE_NONE) { | |
492 | dev_err(dev, "unable to determine PCI mode\n"); | |
493 | err = -EINVAL; | |
494 | goto err_put_hb_node; | |
495 | } | |
496 | ||
497 | dev_info(dev, "mode:%s%s\n", | |
498 | (mode & RT3883_PCI_MODE_PCI) ? " PCI" : "", | |
499 | (mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : ""); | |
500 | ||
501 | rt3883_pci_preinit(rpc, mode); | |
502 | ||
503 | rpc->pci_controller.pci_ops = &rt3883_pci_ops; | |
504 | rpc->pci_controller.io_resource = &rpc->io_res; | |
505 | rpc->pci_controller.mem_resource = &rpc->mem_res; | |
506 | ||
507 | /* Load PCI I/O and memory resources from DT */ | |
508 | pci_load_of_ranges(&rpc->pci_controller, | |
509 | rpc->pci_controller.of_node); | |
510 | ||
511 | rt3883_pci_w32(rpc, rpc->mem_res.start, RT3883_PCI_REG_MEMBASE); | |
512 | rt3883_pci_w32(rpc, rpc->io_res.start, RT3883_PCI_REG_IOBASE); | |
513 | ||
514 | ioport_resource.start = rpc->io_res.start; | |
515 | ioport_resource.end = rpc->io_res.end; | |
516 | ||
517 | /* PCI */ | |
518 | rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0)); | |
519 | rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0)); | |
520 | rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0)); | |
521 | rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0)); | |
522 | rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0)); | |
523 | ||
524 | /* PCIe */ | |
525 | rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1)); | |
526 | rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1)); | |
527 | rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1)); | |
528 | rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1)); | |
529 | rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(1)); | |
530 | ||
531 | err = rt3883_pci_irq_init(dev, rpc); | |
532 | if (err) | |
533 | goto err_put_hb_node; | |
534 | ||
535 | /* PCIe */ | |
536 | val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND); | |
537 | val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; | |
538 | rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val); | |
539 | ||
540 | /* PCI */ | |
541 | val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND); | |
542 | val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; | |
543 | rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val); | |
544 | ||
545 | if (mode == RT3883_PCI_MODE_PCIE) { | |
546 | rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0)); | |
547 | rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1)); | |
548 | ||
549 | rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0, | |
550 | PCI_BASE_ADDRESS_0, | |
551 | RT3883_MEMORY_BASE); | |
552 | /* flush write */ | |
553 | rt3883_pci_read_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0, | |
554 | PCI_BASE_ADDRESS_0); | |
555 | } else { | |
556 | rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0, | |
557 | PCI_IO_BASE, 0x00000101); | |
558 | } | |
559 | ||
560 | register_pci_controller(&rpc->pci_controller); | |
561 | ||
562 | return 0; | |
563 | ||
564 | err_put_hb_node: | |
565 | of_node_put(rpc->pci_controller.of_node); | |
566 | err_put_intc_node: | |
567 | of_node_put(rpc->intc_of_node); | |
568 | return err; | |
569 | } | |
570 | ||
571 | int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) | |
572 | { | |
16b84e5a | 573 | return of_irq_parse_and_map_pci(dev, slot, pin); |
12d14e0e GJ |
574 | } |
575 | ||
576 | int pcibios_plat_dev_init(struct pci_dev *dev) | |
577 | { | |
578 | return 0; | |
579 | } | |
580 | ||
581 | static const struct of_device_id rt3883_pci_ids[] = { | |
582 | { .compatible = "ralink,rt3883-pci" }, | |
583 | {}, | |
584 | }; | |
585 | MODULE_DEVICE_TABLE(of, rt3883_pci_ids); | |
586 | ||
587 | static struct platform_driver rt3883_pci_driver = { | |
588 | .probe = rt3883_pci_probe, | |
589 | .driver = { | |
590 | .name = "rt3883-pci", | |
12d14e0e GJ |
591 | .of_match_table = of_match_ptr(rt3883_pci_ids), |
592 | }, | |
593 | }; | |
594 | ||
595 | static int __init rt3883_pci_init(void) | |
596 | { | |
597 | return platform_driver_register(&rt3883_pci_driver); | |
598 | } | |
599 | ||
600 | postcore_initcall(rt3883_pci_init); |