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9bac624b GR |
1 | /* |
2 | * Copyright (c) 2003-2012 Broadcom Corporation | |
3 | * All Rights Reserved | |
4 | * | |
5 | * This software is available to you under a choice of one of two | |
6 | * licenses. You may choose to be licensed under the terms of the GNU | |
7 | * General Public License (GPL) Version 2, available from the file | |
8 | * COPYING in the main directory of this source tree, or the Broadcom | |
9 | * license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or without | |
12 | * modification, are permitted provided that the following conditions | |
13 | * are met: | |
14 | * | |
15 | * 1. Redistributions of source code must retain the above copyright | |
16 | * notice, this list of conditions and the following disclaimer. | |
17 | * 2. Redistributions in binary form must reproduce the above copyright | |
18 | * notice, this list of conditions and the following disclaimer in | |
19 | * the documentation and/or other materials provided with the | |
20 | * distribution. | |
21 | * | |
22 | * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR | |
23 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | |
24 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
25 | * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE | |
26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
28 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | |
29 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | |
30 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | |
31 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | |
32 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
33 | */ | |
34 | ||
35 | #include <linux/types.h> | |
36 | #include <linux/pci.h> | |
37 | #include <linux/kernel.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/msi.h> | |
40 | #include <linux/mm.h> | |
41 | #include <linux/irq.h> | |
42 | #include <linux/irqdesc.h> | |
43 | #include <linux/console.h> | |
44 | ||
45 | #include <asm/io.h> | |
46 | ||
47 | #include <asm/netlogic/interrupt.h> | |
48 | #include <asm/netlogic/haldefs.h> | |
49 | ||
50 | #include <asm/netlogic/xlp-hal/iomap.h> | |
51 | #include <asm/netlogic/xlp-hal/pic.h> | |
52 | #include <asm/netlogic/xlp-hal/xlp.h> | |
53 | #include <asm/netlogic/xlp-hal/pcibus.h> | |
54 | #include <asm/netlogic/xlp-hal/bridge.h> | |
55 | ||
56 | static void *pci_config_base; | |
57 | ||
58 | #define pci_cfg_addr(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off)) | |
59 | ||
60 | /* PCI ops */ | |
61 | static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn, | |
62 | int where) | |
63 | { | |
64 | u32 data; | |
65 | u32 *cfgaddr; | |
66 | ||
67 | cfgaddr = (u32 *)(pci_config_base + | |
68 | pci_cfg_addr(bus->number, devfn, where & ~3)); | |
69 | data = *cfgaddr; | |
70 | return data; | |
71 | } | |
72 | ||
73 | static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn, | |
74 | int where, u32 data) | |
75 | { | |
76 | u32 *cfgaddr; | |
77 | ||
78 | cfgaddr = (u32 *)(pci_config_base + | |
79 | pci_cfg_addr(bus->number, devfn, where & ~3)); | |
80 | *cfgaddr = data; | |
81 | } | |
82 | ||
83 | static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn, | |
84 | int where, int size, u32 *val) | |
85 | { | |
86 | u32 data; | |
87 | ||
88 | if ((size == 2) && (where & 1)) | |
89 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
90 | else if ((size == 4) && (where & 3)) | |
91 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
92 | ||
93 | data = pci_cfg_read_32bit(bus, devfn, where); | |
94 | ||
95 | if (size == 1) | |
96 | *val = (data >> ((where & 3) << 3)) & 0xff; | |
97 | else if (size == 2) | |
98 | *val = (data >> ((where & 3) << 3)) & 0xffff; | |
99 | else | |
100 | *val = data; | |
101 | ||
102 | return PCIBIOS_SUCCESSFUL; | |
103 | } | |
104 | ||
105 | ||
106 | static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn, | |
107 | int where, int size, u32 val) | |
108 | { | |
109 | u32 data; | |
110 | ||
111 | if ((size == 2) && (where & 1)) | |
112 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
113 | else if ((size == 4) && (where & 3)) | |
114 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
115 | ||
116 | data = pci_cfg_read_32bit(bus, devfn, where); | |
117 | ||
118 | if (size == 1) | |
119 | data = (data & ~(0xff << ((where & 3) << 3))) | | |
120 | (val << ((where & 3) << 3)); | |
121 | else if (size == 2) | |
122 | data = (data & ~(0xffff << ((where & 3) << 3))) | | |
123 | (val << ((where & 3) << 3)); | |
124 | else | |
125 | data = val; | |
126 | ||
127 | pci_cfg_write_32bit(bus, devfn, where, data); | |
128 | ||
129 | return PCIBIOS_SUCCESSFUL; | |
130 | } | |
131 | ||
132 | struct pci_ops nlm_pci_ops = { | |
133 | .read = nlm_pcibios_read, | |
134 | .write = nlm_pcibios_write | |
135 | }; | |
136 | ||
137 | static struct resource nlm_pci_mem_resource = { | |
138 | .name = "XLP PCI MEM", | |
139 | .start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */ | |
140 | .end = 0xdfffffffUL, | |
141 | .flags = IORESOURCE_MEM, | |
142 | }; | |
143 | ||
144 | static struct resource nlm_pci_io_resource = { | |
145 | .name = "XLP IO MEM", | |
146 | .start = 0x14000000UL, /* 64MB PCI IO @ 0x1000_0000 */ | |
147 | .end = 0x17ffffffUL, | |
148 | .flags = IORESOURCE_IO, | |
149 | }; | |
150 | ||
151 | struct pci_controller nlm_pci_controller = { | |
152 | .index = 0, | |
153 | .pci_ops = &nlm_pci_ops, | |
154 | .mem_resource = &nlm_pci_mem_resource, | |
155 | .mem_offset = 0x00000000UL, | |
156 | .io_resource = &nlm_pci_io_resource, | |
157 | .io_offset = 0x00000000UL, | |
158 | }; | |
159 | ||
160 | static int get_irq_vector(const struct pci_dev *dev) | |
161 | { | |
162 | /* | |
163 | * For XLP PCIe, there is an IRQ per Link, find out which | |
164 | * link the device is on to assign interrupts | |
165 | */ | |
166 | if (dev->bus->self == NULL) | |
167 | return 0; | |
168 | ||
169 | switch (dev->bus->self->devfn) { | |
170 | case 0x8: | |
171 | return PIC_PCIE_LINK_0_IRQ; | |
172 | case 0x9: | |
173 | return PIC_PCIE_LINK_1_IRQ; | |
174 | case 0xa: | |
175 | return PIC_PCIE_LINK_2_IRQ; | |
176 | case 0xb: | |
177 | return PIC_PCIE_LINK_3_IRQ; | |
178 | } | |
179 | WARN(1, "Unexpected devfn %d\n", dev->bus->self->devfn); | |
180 | return 0; | |
181 | } | |
182 | ||
183 | int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) | |
184 | { | |
185 | return get_irq_vector(dev); | |
186 | } | |
187 | ||
188 | /* Do platform specific device initialization at pci_enable_device() time */ | |
189 | int pcibios_plat_dev_init(struct pci_dev *dev) | |
190 | { | |
191 | return 0; | |
192 | } | |
193 | ||
a264b5e8 J |
194 | /* |
195 | * If big-endian, enable hardware byteswap on the PCIe bridges. | |
196 | * This will make both the SoC and PCIe devices behave consistently with | |
197 | * readl/writel. | |
198 | */ | |
199 | #ifdef __BIG_ENDIAN | |
200 | static void xlp_config_pci_bswap(void) | |
9bac624b GR |
201 | { |
202 | uint64_t pciebase, sysbase; | |
203 | int node, i; | |
204 | u32 reg; | |
205 | ||
206 | /* Chip-0 so node set to 0 */ | |
207 | node = 0; | |
208 | sysbase = nlm_get_bridge_regbase(node); | |
209 | /* | |
210 | * Enable byte swap in hardware. Program each link's PCIe SWAP regions | |
211 | * from the link's address ranges. | |
212 | */ | |
213 | for (i = 0; i < 4; i++) { | |
214 | pciebase = nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, i)); | |
215 | if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff) | |
216 | continue; | |
217 | ||
218 | reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_BASE0 + i); | |
219 | nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_BASE, reg); | |
220 | ||
221 | reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_LIMIT0 + i); | |
222 | nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_LIM, | |
223 | reg | 0xfff); | |
224 | ||
225 | reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_BASE0 + i); | |
226 | nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_BASE, reg); | |
227 | ||
228 | reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_LIMIT0 + i); | |
229 | nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff); | |
230 | } | |
9bac624b | 231 | } |
a264b5e8 J |
232 | #else |
233 | /* Swap configuration not needed in little-endian mode */ | |
234 | static inline void xlp_config_pci_bswap(void) {} | |
235 | #endif /* __BIG_ENDIAN */ | |
9bac624b GR |
236 | |
237 | static int __init pcibios_init(void) | |
238 | { | |
239 | /* Firmware assigns PCI resources */ | |
240 | pci_set_flags(PCI_PROBE_ONLY); | |
241 | pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20); | |
242 | ||
243 | /* Extend IO port for memory mapped io */ | |
244 | ioport_resource.start = 0; | |
245 | ioport_resource.end = ~0; | |
246 | ||
a264b5e8 | 247 | xlp_config_pci_bswap(); |
9bac624b GR |
248 | set_io_port_base(CKSEG1); |
249 | nlm_pci_controller.io_map_base = CKSEG1; | |
250 | ||
251 | register_pci_controller(&nlm_pci_controller); | |
252 | pr_info("XLP PCIe Controller %pR%pR.\n", &nlm_pci_io_resource, | |
253 | &nlm_pci_mem_resource); | |
254 | ||
255 | return 0; | |
256 | } | |
257 | arch_initcall(pcibios_init); |