[deliverable/linux.git] / arch / mips / pci / pci-xlp.c

/*
 * Copyright (c) 2003-2012 Broadcom Corporation
 * All Rights Reserved
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the Broadcom
 * license below:
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/msi.h>
#include <linux/mm.h>
#include <linux/irq.h>
#include <linux/irqdesc.h>
#include <linux/console.h>

#include <asm/io.h>

#include <asm/netlogic/interrupt.h>
#include <asm/netlogic/haldefs.h>
#include <asm/netlogic/common.h>
#include <asm/netlogic/mips-extns.h>

#include <asm/netlogic/xlp-hal/iomap.h>
#include <asm/netlogic/xlp-hal/pic.h>
#include <asm/netlogic/xlp-hal/xlp.h>
#include <asm/netlogic/xlp-hal/pcibus.h>
#include <asm/netlogic/xlp-hal/bridge.h>

static void *pci_config_base;

#define pci_cfg_addr(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off))

/* PCI ops */
static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,
	int where)
{
	u32 data;
	u32 *cfgaddr;

	where &= ~3;
	if (bus->number == 0 && PCI_SLOT(devfn) == 1 && where == 0x954)
		return 0xffffffff;

	cfgaddr = (u32 *)(pci_config_base +
			pci_cfg_addr(bus->number, devfn, where));
	data = *cfgaddr;
	return data;
}

static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn,
	int where, u32 data)
{
	u32 *cfgaddr;

	cfgaddr = (u32 *)(pci_config_base +
			pci_cfg_addr(bus->number, devfn, where & ~3));
	*cfgaddr = data;
}

static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn,
	int where, int size, u32 *val)
{
	u32 data;

	if ((size == 2) && (where & 1))
		return PCIBIOS_BAD_REGISTER_NUMBER;
	else if ((size == 4) && (where & 3))
		return PCIBIOS_BAD_REGISTER_NUMBER;

	data = pci_cfg_read_32bit(bus, devfn, where);

	if (size == 1)
		*val = (data >> ((where & 3) << 3)) & 0xff;
	else if (size == 2)
		*val = (data >> ((where & 3) << 3)) & 0xffff;
	else
		*val = data;

	return PCIBIOS_SUCCESSFUL;
}


static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn,
		int where, int size, u32 val)
{
	u32 data;

	if ((size == 2) && (where & 1))
		return PCIBIOS_BAD_REGISTER_NUMBER;
	else if ((size == 4) && (where & 3))
		return PCIBIOS_BAD_REGISTER_NUMBER;

	data = pci_cfg_read_32bit(bus, devfn, where);

	if (size == 1)
		data = (data & ~(0xff << ((where & 3) << 3))) |
			(val << ((where & 3) << 3));
	else if (size == 2)
		data = (data & ~(0xffff << ((where & 3) << 3))) |
			(val << ((where & 3) << 3));
	else
		data = val;

	pci_cfg_write_32bit(bus, devfn, where, data);

	return PCIBIOS_SUCCESSFUL;
}

struct pci_ops nlm_pci_ops = {
	.read  = nlm_pcibios_read,
	.write = nlm_pcibios_write
};

static struct resource nlm_pci_mem_resource = {
	.name		= "XLP PCI MEM",
	.start		= 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */
	.end		= 0xdfffffffUL,
	.flags		= IORESOURCE_MEM,
};

static struct resource nlm_pci_io_resource = {
	.name		= "XLP IO MEM",
	.start		= 0x14000000UL, /* 64MB PCI IO @ 0x1000_0000 */
	.end		= 0x17ffffffUL,
	.flags		= IORESOURCE_IO,
};

struct pci_controller nlm_pci_controller = {
	.index		= 0,
	.pci_ops	= &nlm_pci_ops,
	.mem_resource	= &nlm_pci_mem_resource,
	.mem_offset	= 0x00000000UL,
	.io_resource	= &nlm_pci_io_resource,
	.io_offset	= 0x00000000UL,
};

struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev)
{
	struct pci_bus *bus, *p;

	/* Find the bridge on bus 0 */
	bus = dev->bus;
	for (p = bus->parent; p && p->number != 0; p = p->parent)
		bus = p;

	return p ? bus->self : NULL;
}

int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	struct pci_dev *lnkdev;
	int lnkslot, lnkfunc;

	/*
	 * For XLP PCIe, there is an IRQ per Link, find out which
	 * link the device is on to assign interrupts
	*/
	lnkdev = xlp_get_pcie_link(dev);
	if (lnkdev == NULL)
		return 0;
	lnkfunc = PCI_FUNC(lnkdev->devfn);
	lnkslot = PCI_SLOT(lnkdev->devfn);
	return nlm_irq_to_xirq(lnkslot / 8, PIC_PCIE_LINK_LEGACY_IRQ(lnkfunc));
}

/* Do platform specific device initialization at pci_enable_device() time */
int pcibios_plat_dev_init(struct pci_dev *dev)
{
	return 0;
}

/*
 * If big-endian, enable hardware byteswap on the PCIe bridges.
 * This will make both the SoC and PCIe devices behave consistently with
 * readl/writel.
 */
#ifdef __BIG_ENDIAN
static void xlp_config_pci_bswap(int node, int link)
{
	uint64_t nbubase, lnkbase;
	u32 reg;

	nbubase = nlm_get_bridge_regbase(node);
	lnkbase = nlm_get_pcie_base(node, link);

	/*
	 *  Enable byte swap in hardware. Program each link's PCIe SWAP regions
	 * from the link's address ranges.
	 */
	reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_BASE0 + link);
	nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_BASE, reg);

	reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_LIMIT0 + link);
	nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_LIM, reg | 0xfff);

	reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_BASE0 + link);
	nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_BASE, reg);

	reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_LIMIT0 + link);
	nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff);
}
#else
/* Swap configuration not needed in little-endian mode */
static inline void xlp_config_pci_bswap(int node, int link) {}
#endif /* __BIG_ENDIAN */

static int __init pcibios_init(void)
{
	uint64_t pciebase;
	int link, n;
	u32 reg;

	/* Firmware assigns PCI resources */
	pci_set_flags(PCI_PROBE_ONLY);
	pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20);

	/* Extend IO port for memory mapped io */
	ioport_resource.start =	 0;
	ioport_resource.end   = ~0;

	for (n = 0; n < NLM_NR_NODES; n++) {
		if (!nlm_node_present(n))
			continue;

		for (link = 0; link < PCIE_NLINKS; link++) {
			pciebase = nlm_get_pcie_base(n, link);
			if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff)
				continue;
			xlp_config_pci_bswap(n, link);
			xlp_init_node_msi_irqs(n, link);

			/* put in intpin and irq - u-boot does not */
			reg = nlm_read_pci_reg(pciebase, 0xf);
			reg &= ~0x1fu;
			reg |= (1 << 8) | PIC_PCIE_LINK_LEGACY_IRQ(link);
			nlm_write_pci_reg(pciebase, 0xf, reg);
			pr_info("XLP PCIe: Link %d-%d initialized.\n", n, link);
		}
	}

	set_io_port_base(CKSEG1);
	nlm_pci_controller.io_map_base = CKSEG1;

	register_pci_controller(&nlm_pci_controller);
	pr_info("XLP PCIe Controller %pR%pR.\n", &nlm_pci_io_resource,
		&nlm_pci_mem_resource);

	return 0;
}
arch_initcall(pcibios_init);
Commit	Line	Data
9bac624b GR	1	/*
	2	* Copyright (c) 2003-2012 Broadcom Corporation
	3	* All Rights Reserved
	4	*
	5	* This software is available to you under a choice of one of two
	6	* licenses. You may choose to be licensed under the terms of the GNU
	7	* General Public License (GPL) Version 2, available from the file
	8	* COPYING in the main directory of this source tree, or the Broadcom
	9	* license below:
	10	*
	11	* Redistribution and use in source and binary forms, with or without
	12	* modification, are permitted provided that the following conditions
	13	* are met:
	14	*
	15	* 1. Redistributions of source code must retain the above copyright
	16	* notice, this list of conditions and the following disclaimer.
	17	* 2. Redistributions in binary form must reproduce the above copyright
	18	* notice, this list of conditions and the following disclaimer in
	19	* the documentation and/or other materials provided with the
	20	* distribution.
	21	*
	22	* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
	23	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	24	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	25	* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	27	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	28	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
	29	* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
	30	* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
	31	* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
	32	* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	33	*/
	34
	35	#include <linux/types.h>
	36	#include <linux/pci.h>
	37	#include <linux/kernel.h>
	38	#include <linux/init.h>
	39	#include <linux/msi.h>
	40	#include <linux/mm.h>
	41	#include <linux/irq.h>
	42	#include <linux/irqdesc.h>
	43	#include <linux/console.h>
	44
	45	#include <asm/io.h>
	46
	47	#include <asm/netlogic/interrupt.h>
	48	#include <asm/netlogic/haldefs.h>
7b53eb4d	49	#include <asm/netlogic/common.h>
c24a8a7a	50	#include <asm/netlogic/mips-extns.h>
9bac624b GR	51
	52	#include <asm/netlogic/xlp-hal/iomap.h>
	53	#include <asm/netlogic/xlp-hal/pic.h>
	54	#include <asm/netlogic/xlp-hal/xlp.h>
	55	#include <asm/netlogic/xlp-hal/pcibus.h>
	56	#include <asm/netlogic/xlp-hal/bridge.h>
	57
	58	static void *pci_config_base;
	59
70342287	60	#define pci_cfg_addr(bus, devfn, off) (((bus) << 20) \| ((devfn) << 12) \| (off))
9bac624b GR	61
	62	/* PCI ops */
	63	static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,
	64	int where)
	65	{
	66	u32 data;
	67	u32 *cfgaddr;
	68
8cd3d64c J	69	where &= ~3;
	70	if (bus->number == 0 && PCI_SLOT(devfn) == 1 && where == 0x954)
	71	return 0xffffffff;
	72
9bac624b	73	cfgaddr = (u32 *)(pci_config_base +
8cd3d64c	74	pci_cfg_addr(bus->number, devfn, where));
9bac624b GR	75	data = *cfgaddr;
	76	return data;
	77	}
	78
	79	static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn,
	80	int where, u32 data)
	81	{
	82	u32 *cfgaddr;
	83
	84	cfgaddr = (u32 *)(pci_config_base +
	85	pci_cfg_addr(bus->number, devfn, where & ~3));
	86	*cfgaddr = data;
	87	}
	88
	89	static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn,
	90	int where, int size, u32 *val)
	91	{
	92	u32 data;
	93
	94	if ((size == 2) && (where & 1))
	95	return PCIBIOS_BAD_REGISTER_NUMBER;
	96	else if ((size == 4) && (where & 3))
	97	return PCIBIOS_BAD_REGISTER_NUMBER;
	98
	99	data = pci_cfg_read_32bit(bus, devfn, where);
	100
	101	if (size == 1)
	102	*val = (data >> ((where & 3) << 3)) & 0xff;
	103	else if (size == 2)
	104	*val = (data >> ((where & 3) << 3)) & 0xffff;
	105	else
	106	*val = data;
	107
	108	return PCIBIOS_SUCCESSFUL;
	109	}
	110
	111
	112	static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn,
	113	int where, int size, u32 val)
	114	{
	115	u32 data;
	116
	117	if ((size == 2) && (where & 1))
	118	return PCIBIOS_BAD_REGISTER_NUMBER;
	119	else if ((size == 4) && (where & 3))
	120	return PCIBIOS_BAD_REGISTER_NUMBER;
	121
	122	data = pci_cfg_read_32bit(bus, devfn, where);
	123
	124	if (size == 1)
	125	data = (data & ~(0xff << ((where & 3) << 3))) \|
	126	(val << ((where & 3) << 3));
	127	else if (size == 2)
	128	data = (data & ~(0xffff << ((where & 3) << 3))) \|
	129	(val << ((where & 3) << 3));
	130	else
	131	data = val;
	132
	133	pci_cfg_write_32bit(bus, devfn, where, data);
	134
	135	return PCIBIOS_SUCCESSFUL;
	136	}
	137
	138	struct pci_ops nlm_pci_ops = {
139	.read = nlm_pcibios_read,
140	.write = nlm_pcibios_write
141	};
142
143	static struct resource nlm_pci_mem_resource = {
70342287 RB	144	.name = "XLP PCI MEM",
	145	.start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */
	146	.end = 0xdfffffffUL,
	147	.flags = IORESOURCE_MEM,
9bac624b GR	148	};
	149
	150	static struct resource nlm_pci_io_resource = {
70342287 RB	151	.name = "XLP IO MEM",
	152	.start = 0x14000000UL, /* 64MB PCI IO @ 0x1000_0000 */
	153	.end = 0x17ffffffUL,
	154	.flags = IORESOURCE_IO,
9bac624b GR	155	};
	156
	157	struct pci_controller nlm_pci_controller = {
70342287 RB	158	.index = 0,
	159	.pci_ops = &nlm_pci_ops,
	160	.mem_resource = &nlm_pci_mem_resource,
	161	.mem_offset = 0x00000000UL,
	162	.io_resource = &nlm_pci_io_resource,
	163	.io_offset = 0x00000000UL,
9bac624b GR	164	};
9bac624b GR	165
c24a8a7a	166	struct pci_dev xlp_get_pcie_link(const struct pci_dev dev)
9bac624b	167	{
7b53eb4d	168	struct pci_bus bus, p;
9bac624b	169
7b53eb4d J	170	/* Find the bridge on bus 0 */
	171	bus = dev->bus;
	172	for (p = bus->parent; p && p->number != 0; p = p->parent)
	173	bus = p;
	174
	175	return p ? bus->self : NULL;
	176	}
	177
9bac624b GR	178	int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
9bac624b GR	179	{
7b53eb4d J	180	struct pci_dev *lnkdev;
	181	int lnkslot, lnkfunc;
	182
	183	/*
	184	* For XLP PCIe, there is an IRQ per Link, find out which
	185	* link the device is on to assign interrupts
	186	*/
	187	lnkdev = xlp_get_pcie_link(dev);
	188	if (lnkdev == NULL)
	189	return 0;
	190	lnkfunc = PCI_FUNC(lnkdev->devfn);
	191	lnkslot = PCI_SLOT(lnkdev->devfn);
c24a8a7a	192	return nlm_irq_to_xirq(lnkslot / 8, PIC_PCIE_LINK_LEGACY_IRQ(lnkfunc));
9bac624b GR	193	}
	194
	195	/* Do platform specific device initialization at pci_enable_device() time */
	196	int pcibios_plat_dev_init(struct pci_dev *dev)
	197	{
	198	return 0;
	199	}
	200
a264b5e8 J	201	/*
	202	* If big-endian, enable hardware byteswap on the PCIe bridges.
	203	* This will make both the SoC and PCIe devices behave consistently with
	204	* readl/writel.
	205	*/
	206	#ifdef __BIG_ENDIAN
7b53eb4d	207	static void xlp_config_pci_bswap(int node, int link)
9bac624b	208	{
7b53eb4d	209	uint64_t nbubase, lnkbase;
9bac624b GR	210	u32 reg;
9bac624b GR	211
7b53eb4d J	212	nbubase = nlm_get_bridge_regbase(node);
	213	lnkbase = nlm_get_pcie_base(node, link);
	214
9bac624b GR	215	/*
	216	* Enable byte swap in hardware. Program each link's PCIe SWAP regions
	217	* from the link's address ranges.
	218	*/
7b53eb4d J	219	reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_BASE0 + link);
7b53eb4d J	220	nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_BASE, reg);
9bac624b	221
7b53eb4d J	222	reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_LIMIT0 + link);
7b53eb4d J	223	nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_LIM, reg \| 0xfff);
9bac624b	224
7b53eb4d J	225	reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_BASE0 + link);
7b53eb4d J	226	nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_BASE, reg);
9bac624b	227
7b53eb4d J	228	reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_LIMIT0 + link);
7b53eb4d J	229	nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_LIM, reg \| 0xfff);
9bac624b	230	}
a264b5e8 J	231	#else
a264b5e8 J	232	/* Swap configuration not needed in little-endian mode */
7b53eb4d	233	static inline void xlp_config_pci_bswap(int node, int link) {}
a264b5e8	234	#endif /* __BIG_ENDIAN */
9bac624b GR	235
	236	static int __init pcibios_init(void)
	237	{
7b53eb4d J	238	uint64_t pciebase;
	239	int link, n;
	240	u32 reg;
	241
9bac624b GR	242	/* Firmware assigns PCI resources */
	243	pci_set_flags(PCI_PROBE_ONLY);
	244	pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20);
	245
	246	/* Extend IO port for memory mapped io */
70342287	247	ioport_resource.start = 0;
9bac624b GR	248	ioport_resource.end = ~0;
9bac624b GR	249
7b53eb4d	250	for (n = 0; n < NLM_NR_NODES; n++) {
cfec4c63 J	251	if (!nlm_node_present(n))
cfec4c63 J	252	continue;
7b53eb4d	253
c24a8a7a	254	for (link = 0; link < PCIE_NLINKS; link++) {
7b53eb4d J	255	pciebase = nlm_get_pcie_base(n, link);
	256	if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff)
	257	continue;
	258	xlp_config_pci_bswap(n, link);
c24a8a7a	259	xlp_init_node_msi_irqs(n, link);
7b53eb4d J	260
	261	/* put in intpin and irq - u-boot does not */
	262	reg = nlm_read_pci_reg(pciebase, 0xf);
	263	reg &= ~0x1fu;
c24a8a7a	264	reg \|= (1 << 8) \| PIC_PCIE_LINK_LEGACY_IRQ(link);
7b53eb4d J	265	nlm_write_pci_reg(pciebase, 0xf, reg);
	266	pr_info("XLP PCIe: Link %d-%d initialized.\n", n, link);
	267	}
	268	}
	269
9bac624b GR	270	set_io_port_base(CKSEG1);
	271	nlm_pci_controller.io_map_base = CKSEG1;
	272
	273	register_pci_controller(&nlm_pci_controller);
	274	pr_info("XLP PCIe Controller %pR%pR.\n", &nlm_pci_io_resource,
	275	&nlm_pci_mem_resource);
	276
	277	return 0;
	278	}
	279	arch_initcall(pcibios_init);