[deliverable/linux.git] / arch / mips / pci / pci.c

/*
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
 */
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/bootmem.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/pci.h>

/*
 * Indicate whether we respect the PCI setup left by the firmware.
 *
 * Make this long-lived  so that we know when shutting down
 * whether we probed only or not.
 */
int pci_probe_only;

#define PCI_ASSIGN_ALL_BUSSES	1

unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES;

/*
 * The PCI controller list.
 */

static struct pci_controller *hose_head, **hose_tail = &hose_head;

unsigned long PCIBIOS_MIN_IO;
unsigned long PCIBIOS_MIN_MEM;

static int pci_initialized;

/*
 * We need to avoid collisions with `mirrored' VGA ports
 * and other strange ISA hardware, so we always want the
 * addresses to be allocated in the 0x000-0x0ff region
 * modulo 0x400.
 *
 * Why? Because some silly external IO cards only decode
 * the low 10 bits of the IO address. The 0x00-0xff region
 * is reserved for motherboard devices that decode all 16
 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
 * but we want to try to avoid allocating at 0x2900-0x2bff
 * which might have be mirrored at 0x0100-0x03ff..
 */
resource_size_t
pcibios_align_resource(void *data, const struct resource *res,
		       resource_size_t size, resource_size_t align)
{
	struct pci_dev *dev = data;
	struct pci_controller *hose = dev->sysdata;
	resource_size_t start = res->start;

	if (res->flags & IORESOURCE_IO) {
		/* Make sure we start at our min on all hoses */
		if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
			start = PCIBIOS_MIN_IO + hose->io_resource->start;

		/*
		 * Put everything into 0x00-0xff region modulo 0x400
		 */
		if (start & 0x300)
			start = (start + 0x3ff) & ~0x3ff;
	} else if (res->flags & IORESOURCE_MEM) {
		/* Make sure we start at our min on all hoses */
		if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
			start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
	}

	return start;
}

static void __devinit pcibios_scanbus(struct pci_controller *hose)
{
	static int next_busno;
	static int need_domain_info;
	struct pci_bus *bus;

	if (!hose->iommu)
		PCI_DMA_BUS_IS_PHYS = 1;

	if (hose->get_busno && pci_probe_only)
		next_busno = (*hose->get_busno)();

	bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
	hose->bus = bus;

	need_domain_info = need_domain_info || hose->index;
	hose->need_domain_info = need_domain_info;
	if (bus) {
		next_busno = bus->subordinate + 1;
		/* Don't allow 8-bit bus number overflow inside the hose -
		   reserve some space for bridges. */
		if (next_busno > 224) {
			next_busno = 0;
			need_domain_info = 1;
		}

		if (!pci_probe_only) {
			pci_bus_size_bridges(bus);
			pci_bus_assign_resources(bus);
			pci_enable_bridges(bus);
		}
	}
}

static DEFINE_MUTEX(pci_scan_mutex);

void __devinit register_pci_controller(struct pci_controller *hose)
{
	if (request_resource(&iomem_resource, hose->mem_resource) < 0)
		goto out;
	if (request_resource(&ioport_resource, hose->io_resource) < 0) {
		release_resource(hose->mem_resource);
		goto out;
	}

	*hose_tail = hose;
	hose_tail = &hose->next;

	/*
	 * Do not panic here but later - this might happen before console init.
	 */
	if (!hose->io_map_base) {
		printk(KERN_WARNING
		       "registering PCI controller with io_map_base unset\n");
	}

	/*
	 * Scan the bus if it is register after the PCI subsystem
	 * initialization.
	 */
	if (pci_initialized) {
		mutex_lock(&pci_scan_mutex);
		pcibios_scanbus(hose);
		mutex_unlock(&pci_scan_mutex);
	}

	return;

out:
	printk(KERN_WARNING
	       "Skipping PCI bus scan due to resource conflict\n");
}

static int __init pcibios_init(void)
{
	struct pci_controller *hose;

	/* Scan all of the recorded PCI controllers.  */
	for (hose = hose_head; hose; hose = hose->next)
		pcibios_scanbus(hose);

	pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq);

	pci_initialized = 1;

	return 0;
}

subsys_initcall(pcibios_init);

static int pcibios_enable_resources(struct pci_dev *dev, int mask)
{
	u16 cmd, old_cmd;
	int idx;
	struct resource *r;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	old_cmd = cmd;
	for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
		/* Only set up the requested stuff */
		if (!(mask & (1<<idx)))
			continue;

		r = &dev->resource[idx];
		if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
			continue;
		if ((idx == PCI_ROM_RESOURCE) &&
				(!(r->flags & IORESOURCE_ROM_ENABLE)))
			continue;
		if (!r->start && r->end) {
			printk(KERN_ERR "PCI: Device %s not available "
			       "because of resource collisions\n",
			       pci_name(dev));
			return -EINVAL;
		}
		if (r->flags & IORESOURCE_IO)
			cmd |= PCI_COMMAND_IO;
		if (r->flags & IORESOURCE_MEM)
			cmd |= PCI_COMMAND_MEMORY;
	}
	if (cmd != old_cmd) {
		printk("PCI: Enabling device %s (%04x -> %04x)\n",
		       pci_name(dev), old_cmd, cmd);
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
	return 0;
}

void pcibios_set_master(struct pci_dev *dev)
{
	u8 lat;
	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	if (lat < 16)
		lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
	else if (lat > pcibios_max_latency)
		lat = pcibios_max_latency;
	else
		return;
	printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
	       pci_name(dev), lat);
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
}

unsigned int pcibios_assign_all_busses(void)
{
	return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
}

int pcibios_enable_device(struct pci_dev *dev, int mask)
{
	int err;

	if ((err = pcibios_enable_resources(dev, mask)) < 0)
		return err;

	return pcibios_plat_dev_init(dev);
}

static void pcibios_fixup_device_resources(struct pci_dev *dev,
	struct pci_bus *bus)
{
	/* Update device resources.  */
	struct pci_controller *hose = (struct pci_controller *)bus->sysdata;
	unsigned long offset = 0;
	int i;

	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
		if (!dev->resource[i].start)
			continue;
		if (dev->resource[i].flags & IORESOURCE_IO)
			offset = hose->io_offset;
		else if (dev->resource[i].flags & IORESOURCE_MEM)
			offset = hose->mem_offset;

		dev->resource[i].start += offset;
		dev->resource[i].end += offset;
	}
}

void __devinit pcibios_fixup_bus(struct pci_bus *bus)
{
	/* Propagate hose info into the subordinate devices.  */

	struct pci_controller *hose = bus->sysdata;
	struct list_head *ln;
	struct pci_dev *dev = bus->self;

	if (!dev) {
		bus->resource[0] = hose->io_resource;
		bus->resource[1] = hose->mem_resource;
	} else if (pci_probe_only &&
		   (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
		pci_read_bridge_bases(bus);
		pcibios_fixup_device_resources(dev, bus);
	}

	for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
		dev = pci_dev_b(ln);

		if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
			pcibios_fixup_device_resources(dev, bus);
	}
}

void __init
pcibios_update_irq(struct pci_dev *dev, int irq)
{
	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
}

void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
			 struct resource *res)
{
	struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
	unsigned long offset = 0;

	if (res->flags & IORESOURCE_IO)
		offset = hose->io_offset;
	else if (res->flags & IORESOURCE_MEM)
		offset = hose->mem_offset;

	region->start = res->start - offset;
	region->end = res->end - offset;
}

void __devinit
pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
			struct pci_bus_region *region)
{
	struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
	unsigned long offset = 0;

	if (res->flags & IORESOURCE_IO)
		offset = hose->io_offset;
	else if (res->flags & IORESOURCE_MEM)
		offset = hose->mem_offset;

	res->start = region->start + offset;
	res->end = region->end + offset;
}

#ifdef CONFIG_HOTPLUG
EXPORT_SYMBOL(pcibios_resource_to_bus);
EXPORT_SYMBOL(pcibios_bus_to_resource);
EXPORT_SYMBOL(PCIBIOS_MIN_IO);
EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
#endif

int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
			enum pci_mmap_state mmap_state, int write_combine)
{
	unsigned long prot;

	/*
	 * I/O space can be accessed via normal processor loads and stores on
	 * this platform but for now we elect not to do this and portable
	 * drivers should not do this anyway.
	 */
	if (mmap_state == pci_mmap_io)
		return -EINVAL;

	/*
	 * Ignore write-combine; for now only return uncached mappings.
	 */
	prot = pgprot_val(vma->vm_page_prot);
	prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
	vma->vm_page_prot = __pgprot(prot);

	return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
		vma->vm_end - vma->vm_start, vma->vm_page_prot);
}

char * (*pcibios_plat_setup)(char *str) __devinitdata;

char *__devinit pcibios_setup(char *str)
{
	if (pcibios_plat_setup)
		return pcibios_plat_setup(str);
	return str;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This program is free software; you can redistribute it and/or modify it
	3	* under the terms of the GNU General Public License as published by the
	4	* Free Software Foundation; either version 2 of the License, or (at your
	5	* option) any later version.
	6	*
	7	* Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
	8	*/
1da177e4 LT	9	#include <linux/kernel.h>
	10	#include <linux/mm.h>
	11	#include <linux/bootmem.h>
cae39d13	12	#include <linux/export.h>
1da177e4 LT	13	#include <linux/init.h>
	14	#include <linux/types.h>
	15	#include <linux/pci.h>
	16
	17	/*
	18	* Indicate whether we respect the PCI setup left by the firmware.
	19	*
	20	* Make this long-lived so that we know when shutting down
	21	* whether we probed only or not.
	22	*/
	23	int pci_probe_only;
	24
	25	#define PCI_ASSIGN_ALL_BUSSES 1
	26
	27	unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES;
	28
	29	/*
	30	* The PCI controller list.
	31	*/
	32
d58eaab5	33	static struct pci_controller hose_head, *hose_tail = &hose_head;
1da177e4	34
982f6ffe RB	35	unsigned long PCIBIOS_MIN_IO;
982f6ffe RB	36	unsigned long PCIBIOS_MIN_MEM;
1da177e4	37
540799e3 AJ	38	static int pci_initialized;
540799e3 AJ	39
1da177e4 LT	40	/*
	41	* We need to avoid collisions with `mirrored' VGA ports
	42	* and other strange ISA hardware, so we always want the
	43	* addresses to be allocated in the 0x000-0x0ff region
	44	* modulo 0x400.
	45	*
	46	* Why? Because some silly external IO cards only decode
	47	* the low 10 bits of the IO address. The 0x00-0xff region
	48	* is reserved for motherboard devices that decode all 16
	49	* bits, so it's ok to allocate at, say, 0x2800-0x28ff,
	50	* but we want to try to avoid allocating at 0x2900-0x2bff
	51	* which might have be mirrored at 0x0100-0x03ff..
	52	*/
b26b2d49	53	resource_size_t
3b7a17fc	54	pcibios_align_resource(void data, const struct resource res,
e31dd6e4	55	resource_size_t size, resource_size_t align)
1da177e4 LT	56	{
	57	struct pci_dev *dev = data;
	58	struct pci_controller *hose = dev->sysdata;
e31dd6e4	59	resource_size_t start = res->start;
1da177e4 LT	60
	61	if (res->flags & IORESOURCE_IO) {
	62	/* Make sure we start at our min on all hoses */
	63	if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
	64	start = PCIBIOS_MIN_IO + hose->io_resource->start;
	65
	66	/*
	67	* Put everything into 0x00-0xff region modulo 0x400
	68	*/
	69	if (start & 0x300)
	70	start = (start + 0x3ff) & ~0x3ff;
	71	} else if (res->flags & IORESOURCE_MEM) {
	72	/* Make sure we start at our min on all hoses */
	73	if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
	74	start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
	75	}
	76
b26b2d49	77	return start;
1da177e4 LT	78	}
1da177e4 LT	79
540799e3 AJ	80	static void __devinit pcibios_scanbus(struct pci_controller *hose)
	81	{
	82	static int next_busno;
	83	static int need_domain_info;
	84	struct pci_bus *bus;
	85
	86	if (!hose->iommu)
	87	PCI_DMA_BUS_IS_PHYS = 1;
	88
	89	if (hose->get_busno && pci_probe_only)
	90	next_busno = (*hose->get_busno)();
	91
	92	bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
	93	hose->bus = bus;
	94
	95	need_domain_info = need_domain_info \|\| hose->index;
	96	hose->need_domain_info = need_domain_info;
	97	if (bus) {
	98	next_busno = bus->subordinate + 1;
	99	/* Don't allow 8-bit bus number overflow inside the hose -
	100	reserve some space for bridges. */
	101	if (next_busno > 224) {
	102	next_busno = 0;
	103	need_domain_info = 1;
	104	}
	105
	106	if (!pci_probe_only) {
	107	pci_bus_size_bridges(bus);
	108	pci_bus_assign_resources(bus);
	109	pci_enable_bridges(bus);
	110	}
	111	}
	112	}
	113
	114	static DEFINE_MUTEX(pci_scan_mutex);
	115
606bf782	116	void __devinit register_pci_controller(struct pci_controller *hose)
1da177e4	117	{
639702bd TB	118	if (request_resource(&iomem_resource, hose->mem_resource) < 0)
	119	goto out;
	120	if (request_resource(&ioport_resource, hose->io_resource) < 0) {
	121	release_resource(hose->mem_resource);
	122	goto out;
	123	}
	124
1da177e4 LT	125	*hose_tail = hose;
1da177e4 LT	126	hose_tail = &hose->next;
140c1729 RB	127
140c1729 RB	128	/*
25985edc	129	* Do not panic here but later - this might happen before console init.
140c1729 RB	130	*/
	131	if (!hose->io_map_base) {
	132	printk(KERN_WARNING
	133	"registering PCI controller with io_map_base unset\n");
	134	}
540799e3 AJ	135
	136	/*
	137	* Scan the bus if it is register after the PCI subsystem
	138	* initialization.
	139	*/
	140	if (pci_initialized) {
	141	mutex_lock(&pci_scan_mutex);
	142	pcibios_scanbus(hose);
	143	mutex_unlock(&pci_scan_mutex);
	144	}
	145
639702bd TB	146	return;
	147
	148	out:
	149	printk(KERN_WARNING
	150	"Skipping PCI bus scan due to resource conflict\n");
1da177e4 LT	151	}
1da177e4 LT	152
1da177e4 LT	153	static int __init pcibios_init(void)
	154	{
	155	struct pci_controller *hose;
1da177e4 LT	156
1da177e4 LT	157	/* Scan all of the recorded PCI controllers. */
540799e3 AJ	158	for (hose = hose_head; hose; hose = hose->next)
540799e3 AJ	159	pcibios_scanbus(hose);
1da177e4	160
67eed580	161	pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq);
1da177e4	162
540799e3 AJ	163	pci_initialized = 1;
540799e3 AJ	164
1da177e4 LT	165	return 0;
	166	}
	167
	168	subsys_initcall(pcibios_init);
	169
	170	static int pcibios_enable_resources(struct pci_dev *dev, int mask)
	171	{
	172	u16 cmd, old_cmd;
	173	int idx;
	174	struct resource *r;
	175
	176	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	177	old_cmd = cmd;
e5de3b46	178	for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
1da177e4 LT	179	/* Only set up the requested stuff */
	180	if (!(mask & (1<<idx)))
	181	continue;
	182
	183	r = &dev->resource[idx];
986c9485 RB	184	if (!(r->flags & (IORESOURCE_IO \| IORESOURCE_MEM)))
	185	continue;
	186	if ((idx == PCI_ROM_RESOURCE) &&
	187	(!(r->flags & IORESOURCE_ROM_ENABLE)))
	188	continue;
1da177e4	189	if (!r->start && r->end) {
40d7c1aa RB	190	printk(KERN_ERR "PCI: Device %s not available "
	191	"because of resource collisions\n",
	192	pci_name(dev));
1da177e4 LT	193	return -EINVAL;
	194	}
	195	if (r->flags & IORESOURCE_IO)
	196	cmd \|= PCI_COMMAND_IO;
	197	if (r->flags & IORESOURCE_MEM)
	198	cmd \|= PCI_COMMAND_MEMORY;
	199	}
1da177e4	200	if (cmd != old_cmd) {
40d7c1aa RB	201	printk("PCI: Enabling device %s (%04x -> %04x)\n",
40d7c1aa RB	202	pci_name(dev), old_cmd, cmd);
1da177e4 LT	203	pci_write_config_word(dev, PCI_COMMAND, cmd);
	204	}
	205	return 0;
	206	}
	207
1da177e4 LT	208	void pcibios_set_master(struct pci_dev *dev)
	209	{
	210	u8 lat;
	211	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	212	if (lat < 16)
	213	lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
	214	else if (lat > pcibios_max_latency)
	215	lat = pcibios_max_latency;
	216	else
	217	return;
	218	printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
	219	pci_name(dev), lat);
	220	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
	221	}
	222
	223	unsigned int pcibios_assign_all_busses(void)
	224	{
	225	return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
	226	}
	227
	228	int pcibios_enable_device(struct pci_dev *dev, int mask)
	229	{
	230	int err;
	231
	232	if ((err = pcibios_enable_resources(dev, mask)) < 0)
	233	return err;
	234
	235	return pcibios_plat_dev_init(dev);
	236	}
	237
c4aa2563	238	static void pcibios_fixup_device_resources(struct pci_dev *dev,
1da177e4 LT	239	struct pci_bus *bus)
	240	{
	241	/* Update device resources. */
	242	struct pci_controller hose = (struct pci_controller )bus->sysdata;
	243	unsigned long offset = 0;
	244	int i;
	245
	246	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	247	if (!dev->resource[i].start)
	248	continue;
	249	if (dev->resource[i].flags & IORESOURCE_IO)
	250	offset = hose->io_offset;
	251	else if (dev->resource[i].flags & IORESOURCE_MEM)
	252	offset = hose->mem_offset;
	253
	254	dev->resource[i].start += offset;
	255	dev->resource[i].end += offset;
	256	}
	257	}
	258
234fcd14	259	void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1da177e4 LT	260	{
	261	/* Propagate hose info into the subordinate devices. */
	262
	263	struct pci_controller *hose = bus->sysdata;
	264	struct list_head *ln;
	265	struct pci_dev *dev = bus->self;
	266
	267	if (!dev) {
	268	bus->resource[0] = hose->io_resource;
	269	bus->resource[1] = hose->mem_resource;
	270	} else if (pci_probe_only &&
	271	(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
	272	pci_read_bridge_bases(bus);
	273	pcibios_fixup_device_resources(dev, bus);
42a3b4f2	274	}
1da177e4 LT	275
1da177e4 LT	276	for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
8ed07a1c	277	dev = pci_dev_b(ln);
1da177e4 LT	278
	279	if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
	280	pcibios_fixup_device_resources(dev, bus);
	281	}
	282	}
	283
	284	void __init
	285	pcibios_update_irq(struct pci_dev *dev, int irq)
	286	{
	287	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
	288	}
	289
c4aa2563	290	void pcibios_resource_to_bus(struct pci_dev dev, struct pci_bus_region region,
1da177e4 LT	291	struct resource *res)
	292	{
	293	struct pci_controller hose = (struct pci_controller )dev->sysdata;
	294	unsigned long offset = 0;
	295
	296	if (res->flags & IORESOURCE_IO)
	297	offset = hose->io_offset;
	298	else if (res->flags & IORESOURCE_MEM)
	299	offset = hose->mem_offset;
	300
	301	region->start = res->start - offset;
	302	region->end = res->end - offset;
	303	}
	304
e63ea56f YY	305	void __devinit
	306	pcibios_bus_to_resource(struct pci_dev dev, struct resource res,
	307	struct pci_bus_region *region)
	308	{
	309	struct pci_controller hose = (struct pci_controller )dev->sysdata;
	310	unsigned long offset = 0;
	311
	312	if (res->flags & IORESOURCE_IO)
	313	offset = hose->io_offset;
	314	else if (res->flags & IORESOURCE_MEM)
	315	offset = hose->mem_offset;
	316
	317	res->start = region->start + offset;
	318	res->end = region->end + offset;
	319	}
	320
1da177e4 LT	321	#ifdef CONFIG_HOTPLUG
1da177e4 LT	322	EXPORT_SYMBOL(pcibios_resource_to_bus);
e63ea56f	323	EXPORT_SYMBOL(pcibios_bus_to_resource);
1da177e4 LT	324	EXPORT_SYMBOL(PCIBIOS_MIN_IO);
	325	EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
	326	#endif
	327
98873f53 RB	328	int pci_mmap_page_range(struct pci_dev dev, struct vm_area_struct vma,
	329	enum pci_mmap_state mmap_state, int write_combine)
	330	{
	331	unsigned long prot;
	332
	333	/*
	334	* I/O space can be accessed via normal processor loads and stores on
	335	* this platform but for now we elect not to do this and portable
	336	* drivers should not do this anyway.
	337	*/
	338	if (mmap_state == pci_mmap_io)
	339	return -EINVAL;
	340
	341	/*
	342	* Ignore write-combine; for now only return uncached mappings.
	343	*/
	344	prot = pgprot_val(vma->vm_page_prot);
	345	prot = (prot & ~_CACHE_MASK) \| _CACHE_UNCACHED;
	346	vma->vm_page_prot = __pgprot(prot);
	347
	348	return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
	349	vma->vm_end - vma->vm_start, vma->vm_page_prot);
	350	}
	351
47a5c976 AN	352	char * (pcibios_plat_setup)(char str) __devinitdata;
	353
	354	char __devinit pcibios_setup(char str)
1da177e4	355	{
47a5c976 AN	356	if (pcibios_plat_setup)
47a5c976 AN	357	return pcibios_plat_setup(str);
1da177e4 LT	358	return str;
1da177e4 LT	359	}