[deliverable/linux.git] / arch / mips / pistachio / init.c

/*
 * Pistachio platform setup
 *
 * Copyright (C) 2014 Google, Inc.
 * Copyright (C) 2016 Imagination Technologies
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/of_address.h>
#include <linux/of_fdt.h>
#include <linux/of_platform.h>

#include <asm/cacheflush.h>
#include <asm/dma-coherence.h>
#include <asm/fw/fw.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-cm.h>
#include <asm/mips-cpc.h>
#include <asm/prom.h>
#include <asm/smp-ops.h>
#include <asm/traps.h>

/*
 * Core revision register decoding
 * Bits 23 to 20: Major rev
 * Bits 15 to 8: Minor rev
 * Bits 7 to 0: Maintenance rev
 */
#define PISTACHIO_CORE_REV_REG	0xB81483D0
#define PISTACHIO_CORE_REV_A1	0x00100006
#define PISTACHIO_CORE_REV_B0	0x00100106

const char *get_system_type(void)
{
	u32 core_rev;
	const char *sys_type;

	core_rev = __raw_readl((const void *)PISTACHIO_CORE_REV_REG);

	switch (core_rev) {
	case PISTACHIO_CORE_REV_B0:
		sys_type = "IMG Pistachio SoC (B0)";
		break;

	case PISTACHIO_CORE_REV_A1:
		sys_type = "IMG Pistachio SoC (A1)";
		break;

	default:
		sys_type = "IMG Pistachio SoC";
		break;
	}

	return sys_type;
}

static void __init plat_setup_iocoherency(void)
{
	/*
	 * Kernel has been configured with software coherency
	 * but we might choose to turn it off and use hardware
	 * coherency instead.
	 */
	if (mips_cm_numiocu() != 0) {
		/* Nothing special needs to be done to enable coherency */
		pr_info("CMP IOCU detected\n");
		hw_coherentio = 1;
		if (coherentio == 0)
			pr_info("Hardware DMA cache coherency disabled\n");
		else
			pr_info("Hardware DMA cache coherency enabled\n");
	} else {
		if (coherentio == 1)
			pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
		else
			pr_info("Software DMA cache coherency enabled\n");
	}
}

void __init *plat_get_fdt(void)
{
	if (fw_arg0 != -2)
		panic("Device-tree not present");
	return (void *)fw_arg1;
}

void __init plat_mem_setup(void)
{
	__dt_setup_arch(plat_get_fdt());

	plat_setup_iocoherency();
}

#define DEFAULT_CPC_BASE_ADDR	0x1bde0000
#define DEFAULT_CDMM_BASE_ADDR	0x1bdd0000

phys_addr_t mips_cpc_default_phys_base(void)
{
	return DEFAULT_CPC_BASE_ADDR;
}

phys_addr_t mips_cdmm_phys_base(void)
{
	return DEFAULT_CDMM_BASE_ADDR;
}

static void __init mips_nmi_setup(void)
{
	void *base;
	extern char except_vec_nmi;

	base = cpu_has_veic ?
		(void *)(CAC_BASE + 0xa80) :
		(void *)(CAC_BASE + 0x380);
	memcpy(base, &except_vec_nmi, 0x80);
	flush_icache_range((unsigned long)base,
			   (unsigned long)base + 0x80);
}

static void __init mips_ejtag_setup(void)
{
	void *base;
	extern char except_vec_ejtag_debug;

	base = cpu_has_veic ?
		(void *)(CAC_BASE + 0xa00) :
		(void *)(CAC_BASE + 0x300);
	memcpy(base, &except_vec_ejtag_debug, 0x80);
	flush_icache_range((unsigned long)base,
			   (unsigned long)base + 0x80);
}

void __init prom_init(void)
{
	board_nmi_handler_setup = mips_nmi_setup;
	board_ejtag_handler_setup = mips_ejtag_setup;

	mips_cm_probe();
	mips_cpc_probe();
	register_cps_smp_ops();

	pr_info("SoC Type: %s\n", get_system_type());
}

void __init prom_free_prom_memory(void)
{
}

void __init device_tree_init(void)
{
	if (!initial_boot_params)
		return;

	unflatten_and_copy_device_tree();
}

static int __init plat_of_setup(void)
{
	if (!of_have_populated_dt())
		panic("Device tree not present");

	if (of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL))
		panic("Failed to populate DT");

	return 0;
}
arch_initcall(plat_of_setup);
Commit	Line	Data
6a438309 AB	1	/*
	2	* Pistachio platform setup
	3	*
	4	* Copyright (C) 2014 Google, Inc.
ae07ea85	5	* Copyright (C) 2016 Imagination Technologies
6a438309 AB	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms and conditions of the GNU General Public License,
	9	* version 2, as published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/init.h>
ae07ea85	13	#include <linux/io.h>
6a438309 AB	14	#include <linux/kernel.h>
	15	#include <linux/of_address.h>
	16	#include <linux/of_fdt.h>
	17	#include <linux/of_platform.h>
	18
	19	#include <asm/cacheflush.h>
	20	#include <asm/dma-coherence.h>
	21	#include <asm/fw/fw.h>
	22	#include <asm/mips-boards/generic.h>
	23	#include <asm/mips-cm.h>
	24	#include <asm/mips-cpc.h>
	25	#include <asm/prom.h>
	26	#include <asm/smp-ops.h>
	27	#include <asm/traps.h>
	28
ae07ea85 JH	29	/*
	30	* Core revision register decoding
	31	* Bits 23 to 20: Major rev
	32	* Bits 15 to 8: Minor rev
	33	* Bits 7 to 0: Maintenance rev
	34	*/
	35	#define PISTACHIO_CORE_REV_REG 0xB81483D0
	36	#define PISTACHIO_CORE_REV_A1 0x00100006
	37	#define PISTACHIO_CORE_REV_B0 0x00100106
	38
6a438309 AB	39	const char *get_system_type(void)
6a438309 AB	40	{
ae07ea85 JH	41	u32 core_rev;
	42	const char *sys_type;
	43
	44	core_rev = __raw_readl((const void *)PISTACHIO_CORE_REV_REG);
	45
	46	switch (core_rev) {
	47	case PISTACHIO_CORE_REV_B0:
	48	sys_type = "IMG Pistachio SoC (B0)";
	49	break;
	50
	51	case PISTACHIO_CORE_REV_A1:
	52	sys_type = "IMG Pistachio SoC (A1)";
	53	break;
	54
	55	default:
	56	sys_type = "IMG Pistachio SoC";
	57	break;
	58	}
	59
	60	return sys_type;
6a438309 AB	61	}
	62
	63	static void __init plat_setup_iocoherency(void)
	64	{
	65	/*
	66	* Kernel has been configured with software coherency
	67	* but we might choose to turn it off and use hardware
	68	* coherency instead.
	69	*/
	70	if (mips_cm_numiocu() != 0) {
	71	/* Nothing special needs to be done to enable coherency */
	72	pr_info("CMP IOCU detected\n");
	73	hw_coherentio = 1;
	74	if (coherentio == 0)
	75	pr_info("Hardware DMA cache coherency disabled\n");
	76	else
	77	pr_info("Hardware DMA cache coherency enabled\n");
	78	} else {
	79	if (coherentio == 1)
	80	pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
	81	else
	82	pr_info("Software DMA cache coherency enabled\n");
	83	}
	84	}
	85
41cc07be	86	void __init *plat_get_fdt(void)
6a438309 AB	87	{
	88	if (fw_arg0 != -2)
	89	panic("Device-tree not present");
41cc07be MR	90	return (void *)fw_arg1;
41cc07be MR	91	}
6a438309	92
41cc07be MR	93	void __init plat_mem_setup(void)
	94	{
	95	__dt_setup_arch(plat_get_fdt());
6a438309 AB	96
	97	plat_setup_iocoherency();
	98	}
	99
6b5e741e JH	100	#define DEFAULT_CPC_BASE_ADDR 0x1bde0000
6b5e741e JH	101	#define DEFAULT_CDMM_BASE_ADDR 0x1bdd0000
6a438309 AB	102
	103	phys_addr_t mips_cpc_default_phys_base(void)
	104	{
	105	return DEFAULT_CPC_BASE_ADDR;
	106	}
	107
6b5e741e JH	108	phys_addr_t mips_cdmm_phys_base(void)
	109	{
	110	return DEFAULT_CDMM_BASE_ADDR;
	111	}
	112
6a438309 AB	113	static void __init mips_nmi_setup(void)
	114	{
	115	void *base;
	116	extern char except_vec_nmi;
	117
	118	base = cpu_has_veic ?
	119	(void *)(CAC_BASE + 0xa80) :
	120	(void *)(CAC_BASE + 0x380);
	121	memcpy(base, &except_vec_nmi, 0x80);
	122	flush_icache_range((unsigned long)base,
	123	(unsigned long)base + 0x80);
	124	}
	125
	126	static void __init mips_ejtag_setup(void)
	127	{
	128	void *base;
	129	extern char except_vec_ejtag_debug;
	130
	131	base = cpu_has_veic ?
	132	(void *)(CAC_BASE + 0xa00) :
	133	(void *)(CAC_BASE + 0x300);
	134	memcpy(base, &except_vec_ejtag_debug, 0x80);
	135	flush_icache_range((unsigned long)base,
	136	(unsigned long)base + 0x80);
	137	}
	138
	139	void __init prom_init(void)
	140	{
	141	board_nmi_handler_setup = mips_nmi_setup;
	142	board_ejtag_handler_setup = mips_ejtag_setup;
	143
	144	mips_cm_probe();
	145	mips_cpc_probe();
	146	register_cps_smp_ops();
ae07ea85 JH	147
ae07ea85 JH	148	pr_info("SoC Type: %s\n", get_system_type());
6a438309 AB	149	}
	150
	151	void __init prom_free_prom_memory(void)
	152	{
	153	}
	154
	155	void __init device_tree_init(void)
	156	{
	157	if (!initial_boot_params)
	158	return;
	159
	160	unflatten_and_copy_device_tree();
	161	}
	162
	163	static int __init plat_of_setup(void)
	164	{
	165	if (!of_have_populated_dt())
	166	panic("Device tree not present");
	167
	168	if (of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL))
	169	panic("Failed to populate DT");
	170
	171	return 0;
	172	}
	173	arch_initcall(plat_of_setup);