[deliverable/linux.git] / arch / mips / pistachio / init.c

/*
 * Pistachio platform setup
 *
 * Copyright (C) 2014 Google, Inc.
 * Copyright (C) 2016 Imagination Technologies
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/of_address.h>
#include <linux/of_fdt.h>

#include <asm/cacheflush.h>
#include <asm/dma-coherence.h>
#include <asm/fw/fw.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-cm.h>
#include <asm/mips-cpc.h>
#include <asm/prom.h>
#include <asm/smp-ops.h>
#include <asm/traps.h>

/*
 * Core revision register decoding
 * Bits 23 to 20: Major rev
 * Bits 15 to 8: Minor rev
 * Bits 7 to 0: Maintenance rev
 */
#define PISTACHIO_CORE_REV_REG	0xB81483D0
#define PISTACHIO_CORE_REV_A1	0x00100006
#define PISTACHIO_CORE_REV_B0	0x00100106

const char *get_system_type(void)
{
	u32 core_rev;
	const char *sys_type;

	core_rev = __raw_readl((const void *)PISTACHIO_CORE_REV_REG);

	switch (core_rev) {
	case PISTACHIO_CORE_REV_B0:
		sys_type = "IMG Pistachio SoC (B0)";
		break;

	case PISTACHIO_CORE_REV_A1:
		sys_type = "IMG Pistachio SoC (A1)";
		break;

	default:
		sys_type = "IMG Pistachio SoC";
		break;
	}

	return sys_type;
}

static void __init plat_setup_iocoherency(void)
{
	/*
	 * Kernel has been configured with software coherency
	 * but we might choose to turn it off and use hardware
	 * coherency instead.
	 */
	if (mips_cm_numiocu() != 0) {
		/* Nothing special needs to be done to enable coherency */
		pr_info("CMP IOCU detected\n");
		hw_coherentio = 1;
		if (coherentio == 0)
			pr_info("Hardware DMA cache coherency disabled\n");
		else
			pr_info("Hardware DMA cache coherency enabled\n");
	} else {
		if (coherentio == 1)
			pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
		else
			pr_info("Software DMA cache coherency enabled\n");
	}
}

void __init *plat_get_fdt(void)
{
	if (fw_arg0 != -2)
		panic("Device-tree not present");
	return (void *)fw_arg1;
}

void __init plat_mem_setup(void)
{
	__dt_setup_arch(plat_get_fdt());

	plat_setup_iocoherency();
}

#define DEFAULT_CPC_BASE_ADDR	0x1bde0000
#define DEFAULT_CDMM_BASE_ADDR	0x1bdd0000

phys_addr_t mips_cpc_default_phys_base(void)
{
	return DEFAULT_CPC_BASE_ADDR;
}

phys_addr_t mips_cdmm_phys_base(void)
{
	return DEFAULT_CDMM_BASE_ADDR;
}

static void __init mips_nmi_setup(void)
{
	void *base;
	extern char except_vec_nmi;

	base = cpu_has_veic ?
		(void *)(CAC_BASE + 0xa80) :
		(void *)(CAC_BASE + 0x380);
	memcpy(base, &except_vec_nmi, 0x80);
	flush_icache_range((unsigned long)base,
			   (unsigned long)base + 0x80);
}

static void __init mips_ejtag_setup(void)
{
	void *base;
	extern char except_vec_ejtag_debug;

	base = cpu_has_veic ?
		(void *)(CAC_BASE + 0xa00) :
		(void *)(CAC_BASE + 0x300);
	memcpy(base, &except_vec_ejtag_debug, 0x80);
	flush_icache_range((unsigned long)base,
			   (unsigned long)base + 0x80);
}

void __init prom_init(void)
{
	board_nmi_handler_setup = mips_nmi_setup;
	board_ejtag_handler_setup = mips_ejtag_setup;

	mips_cm_probe();
	mips_cpc_probe();
	register_cps_smp_ops();

	pr_info("SoC Type: %s\n", get_system_type());
}

void __init prom_free_prom_memory(void)
{
}

void __init device_tree_init(void)
{
	if (!initial_boot_params)
		return;

	unflatten_and_copy_device_tree();
}
Commit	Line	Data
6a438309 AB	1	/*
	2	* Pistachio platform setup
	3	*
	4	* Copyright (C) 2014 Google, Inc.
ae07ea85	5	* Copyright (C) 2016 Imagination Technologies
6a438309 AB	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms and conditions of the GNU General Public License,
	9	* version 2, as published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/init.h>
ae07ea85	13	#include <linux/io.h>
6a438309 AB	14	#include <linux/kernel.h>
	15	#include <linux/of_address.h>
	16	#include <linux/of_fdt.h>
6a438309 AB	17
	18	#include <asm/cacheflush.h>
	19	#include <asm/dma-coherence.h>
	20	#include <asm/fw/fw.h>
	21	#include <asm/mips-boards/generic.h>
	22	#include <asm/mips-cm.h>
	23	#include <asm/mips-cpc.h>
	24	#include <asm/prom.h>
	25	#include <asm/smp-ops.h>
	26	#include <asm/traps.h>
	27
ae07ea85 JH	28	/*
	29	* Core revision register decoding
	30	* Bits 23 to 20: Major rev
	31	* Bits 15 to 8: Minor rev
	32	* Bits 7 to 0: Maintenance rev
	33	*/
	34	#define PISTACHIO_CORE_REV_REG 0xB81483D0
	35	#define PISTACHIO_CORE_REV_A1 0x00100006
	36	#define PISTACHIO_CORE_REV_B0 0x00100106
	37
6a438309 AB	38	const char *get_system_type(void)
6a438309 AB	39	{
ae07ea85 JH	40	u32 core_rev;
	41	const char *sys_type;
	42
	43	core_rev = __raw_readl((const void *)PISTACHIO_CORE_REV_REG);
	44
	45	switch (core_rev) {
	46	case PISTACHIO_CORE_REV_B0:
	47	sys_type = "IMG Pistachio SoC (B0)";
	48	break;
	49
	50	case PISTACHIO_CORE_REV_A1:
	51	sys_type = "IMG Pistachio SoC (A1)";
	52	break;
	53
	54	default:
	55	sys_type = "IMG Pistachio SoC";
	56	break;
	57	}
	58
	59	return sys_type;
6a438309 AB	60	}
	61
	62	static void __init plat_setup_iocoherency(void)
	63	{
	64	/*
	65	* Kernel has been configured with software coherency
	66	* but we might choose to turn it off and use hardware
	67	* coherency instead.
	68	*/
	69	if (mips_cm_numiocu() != 0) {
	70	/* Nothing special needs to be done to enable coherency */
	71	pr_info("CMP IOCU detected\n");
	72	hw_coherentio = 1;
	73	if (coherentio == 0)
	74	pr_info("Hardware DMA cache coherency disabled\n");
	75	else
	76	pr_info("Hardware DMA cache coherency enabled\n");
	77	} else {
	78	if (coherentio == 1)
	79	pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
	80	else
	81	pr_info("Software DMA cache coherency enabled\n");
	82	}
	83	}
	84
41cc07be	85	void __init *plat_get_fdt(void)
6a438309 AB	86	{
	87	if (fw_arg0 != -2)
	88	panic("Device-tree not present");
41cc07be MR	89	return (void *)fw_arg1;
41cc07be MR	90	}
6a438309	91
41cc07be MR	92	void __init plat_mem_setup(void)
	93	{
	94	__dt_setup_arch(plat_get_fdt());
6a438309 AB	95
	96	plat_setup_iocoherency();
	97	}
	98
6b5e741e JH	99	#define DEFAULT_CPC_BASE_ADDR 0x1bde0000
6b5e741e JH	100	#define DEFAULT_CDMM_BASE_ADDR 0x1bdd0000
6a438309 AB	101
	102	phys_addr_t mips_cpc_default_phys_base(void)
	103	{
	104	return DEFAULT_CPC_BASE_ADDR;
	105	}
	106
6b5e741e JH	107	phys_addr_t mips_cdmm_phys_base(void)
	108	{
	109	return DEFAULT_CDMM_BASE_ADDR;
	110	}
	111
6a438309 AB	112	static void __init mips_nmi_setup(void)
	113	{
	114	void *base;
	115	extern char except_vec_nmi;
	116
	117	base = cpu_has_veic ?
	118	(void *)(CAC_BASE + 0xa80) :
	119	(void *)(CAC_BASE + 0x380);
	120	memcpy(base, &except_vec_nmi, 0x80);
	121	flush_icache_range((unsigned long)base,
	122	(unsigned long)base + 0x80);
	123	}
	124
	125	static void __init mips_ejtag_setup(void)
	126	{
	127	void *base;
	128	extern char except_vec_ejtag_debug;
	129
	130	base = cpu_has_veic ?
	131	(void *)(CAC_BASE + 0xa00) :
	132	(void *)(CAC_BASE + 0x300);
	133	memcpy(base, &except_vec_ejtag_debug, 0x80);
	134	flush_icache_range((unsigned long)base,
	135	(unsigned long)base + 0x80);
	136	}
	137
	138	void __init prom_init(void)
	139	{
	140	board_nmi_handler_setup = mips_nmi_setup;
	141	board_ejtag_handler_setup = mips_ejtag_setup;
	142
	143	mips_cm_probe();
	144	mips_cpc_probe();
	145	register_cps_smp_ops();
ae07ea85 JH	146
ae07ea85 JH	147	pr_info("SoC Type: %s\n", get_system_type());
6a438309 AB	148	}
	149
	150	void __init prom_free_prom_memory(void)
	151	{
	152	}
	153
	154	void __init device_tree_init(void)
	155	{
	156	if (!initial_boot_params)
	157	return;
	158
	159	unflatten_and_copy_device_tree();
	160	}