[deliverable/linux.git] / arch / mips / ralink / rt305x.c

/*
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation.
 *
 * Parts of this file are based on Ralink's 2.6.21 BSP
 *
 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>

#include <asm/mipsregs.h>
#include <asm/mach-ralink/ralink_regs.h>
#include <asm/mach-ralink/rt305x.h>

#include "common.h"

enum rt305x_soc_type rt305x_soc;

static struct ralink_pinmux_grp mode_mux[] = {
	{
		.name = "i2c",
		.mask = RT305X_GPIO_MODE_I2C,
		.gpio_first = RT305X_GPIO_I2C_SD,
		.gpio_last = RT305X_GPIO_I2C_SCLK,
	}, {
		.name = "spi",
		.mask = RT305X_GPIO_MODE_SPI,
		.gpio_first = RT305X_GPIO_SPI_EN,
		.gpio_last = RT305X_GPIO_SPI_CLK,
	}, {
		.name = "uartlite",
		.mask = RT305X_GPIO_MODE_UART1,
		.gpio_first = RT305X_GPIO_UART1_TXD,
		.gpio_last = RT305X_GPIO_UART1_RXD,
	}, {
		.name = "jtag",
		.mask = RT305X_GPIO_MODE_JTAG,
		.gpio_first = RT305X_GPIO_JTAG_TDO,
		.gpio_last = RT305X_GPIO_JTAG_TDI,
	}, {
		.name = "mdio",
		.mask = RT305X_GPIO_MODE_MDIO,
		.gpio_first = RT305X_GPIO_MDIO_MDC,
		.gpio_last = RT305X_GPIO_MDIO_MDIO,
	}, {
		.name = "sdram",
		.mask = RT305X_GPIO_MODE_SDRAM,
		.gpio_first = RT305X_GPIO_SDRAM_MD16,
		.gpio_last = RT305X_GPIO_SDRAM_MD31,
	}, {
		.name = "rgmii",
		.mask = RT305X_GPIO_MODE_RGMII,
		.gpio_first = RT305X_GPIO_GE0_TXD0,
		.gpio_last = RT305X_GPIO_GE0_RXCLK,
	}, {0}
};

static struct ralink_pinmux_grp uart_mux[] = {
	{
		.name = "uartf",
		.mask = RT305X_GPIO_MODE_UARTF,
		.gpio_first = RT305X_GPIO_7,
		.gpio_last = RT305X_GPIO_14,
	}, {
		.name = "pcm uartf",
		.mask = RT305X_GPIO_MODE_PCM_UARTF,
		.gpio_first = RT305X_GPIO_7,
		.gpio_last = RT305X_GPIO_14,
	}, {
		.name = "pcm i2s",
		.mask = RT305X_GPIO_MODE_PCM_I2S,
		.gpio_first = RT305X_GPIO_7,
		.gpio_last = RT305X_GPIO_14,
	}, {
		.name = "i2s uartf",
		.mask = RT305X_GPIO_MODE_I2S_UARTF,
		.gpio_first = RT305X_GPIO_7,
		.gpio_last = RT305X_GPIO_14,
	}, {
		.name = "pcm gpio",
		.mask = RT305X_GPIO_MODE_PCM_GPIO,
		.gpio_first = RT305X_GPIO_10,
		.gpio_last = RT305X_GPIO_14,
	}, {
		.name = "gpio uartf",
		.mask = RT305X_GPIO_MODE_GPIO_UARTF,
		.gpio_first = RT305X_GPIO_7,
		.gpio_last = RT305X_GPIO_10,
	}, {
		.name = "gpio i2s",
		.mask = RT305X_GPIO_MODE_GPIO_I2S,
		.gpio_first = RT305X_GPIO_7,
		.gpio_last = RT305X_GPIO_10,
	}, {
		.name = "gpio",
		.mask = RT305X_GPIO_MODE_GPIO,
	}, {0}
};

static void rt305x_wdt_reset(void)
{
	u32 t;

	/* enable WDT reset output on pin SRAM_CS_N */
	t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
	t |= RT305X_SYSCFG_SRAM_CS0_MODE_WDT <<
		RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT;
	rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
}

struct ralink_pinmux rt_gpio_pinmux = {
	.mode = mode_mux,
	.uart = uart_mux,
	.uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
	.uart_mask = RT305X_GPIO_MODE_UART0_MASK,
	.wdt_reset = rt305x_wdt_reset,
};

void __init ralink_clk_init(void)
{
	unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
	unsigned long wmac_rate = 40000000;

	u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);

	if (soc_is_rt305x() || soc_is_rt3350()) {
		t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
		     RT305X_SYSCFG_CPUCLK_MASK;
		switch (t) {
		case RT305X_SYSCFG_CPUCLK_LOW:
			cpu_rate = 320000000;
			break;
		case RT305X_SYSCFG_CPUCLK_HIGH:
			cpu_rate = 384000000;
			break;
		}
		sys_rate = uart_rate = wdt_rate = cpu_rate / 3;
	} else if (soc_is_rt3352()) {
		t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) &
		     RT3352_SYSCFG0_CPUCLK_MASK;
		switch (t) {
		case RT3352_SYSCFG0_CPUCLK_LOW:
			cpu_rate = 384000000;
			break;
		case RT3352_SYSCFG0_CPUCLK_HIGH:
			cpu_rate = 400000000;
			break;
		}
		sys_rate = wdt_rate = cpu_rate / 3;
		uart_rate = 40000000;
	} else if (soc_is_rt5350()) {
		t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) &
		     RT5350_SYSCFG0_CPUCLK_MASK;
		switch (t) {
		case RT5350_SYSCFG0_CPUCLK_360:
			cpu_rate = 360000000;
			sys_rate = cpu_rate / 3;
			break;
		case RT5350_SYSCFG0_CPUCLK_320:
			cpu_rate = 320000000;
			sys_rate = cpu_rate / 4;
			break;
		case RT5350_SYSCFG0_CPUCLK_300:
			cpu_rate = 300000000;
			sys_rate = cpu_rate / 3;
			break;
		default:
			BUG();
		}
		uart_rate = 40000000;
		wdt_rate = sys_rate;
	} else {
		BUG();
	}

	if (soc_is_rt3352() || soc_is_rt5350()) {
		u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);

		if (!(val & RT3352_CLKCFG0_XTAL_SEL))
			wmac_rate = 20000000;
	}

	ralink_clk_add("cpu", cpu_rate);
	ralink_clk_add("10000b00.spi", sys_rate);
	ralink_clk_add("10000100.timer", wdt_rate);
	ralink_clk_add("10000120.watchdog", wdt_rate);
	ralink_clk_add("10000500.uart", uart_rate);
	ralink_clk_add("10000c00.uartlite", uart_rate);
	ralink_clk_add("10100000.ethernet", sys_rate);
	ralink_clk_add("10180000.wmac", wmac_rate);
}

void __init ralink_of_remap(void)
{
	rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc");
	rt_memc_membase = plat_of_remap_node("ralink,rt3050-memc");

	if (!rt_sysc_membase || !rt_memc_membase)
		panic("Failed to remap core resources");
}

void prom_soc_init(struct ralink_soc_info *soc_info)
{
	void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
	unsigned char *name;
	u32 n0;
	u32 n1;
	u32 id;

	n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
	n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);

	if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) {
		unsigned long icache_sets;

		icache_sets = (read_c0_config1() >> 22) & 7;
		if (icache_sets == 1) {
			rt305x_soc = RT305X_SOC_RT3050;
			name = "RT3050";
			soc_info->compatible = "ralink,rt3050-soc";
		} else {
			rt305x_soc = RT305X_SOC_RT3052;
			name = "RT3052";
			soc_info->compatible = "ralink,rt3052-soc";
		}
	} else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) {
		rt305x_soc = RT305X_SOC_RT3350;
		name = "RT3350";
		soc_info->compatible = "ralink,rt3350-soc";
	} else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) {
		rt305x_soc = RT305X_SOC_RT3352;
		name = "RT3352";
		soc_info->compatible = "ralink,rt3352-soc";
	} else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) {
		rt305x_soc = RT305X_SOC_RT5350;
		name = "RT5350";
		soc_info->compatible = "ralink,rt5350-soc";
	} else {
		panic("rt305x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
	}

	id = __raw_readl(sysc + SYSC_REG_CHIP_ID);

	snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
		"Ralink %s id:%u rev:%u",
		name,
		(id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
		(id & CHIP_ID_REV_MASK));
}
Commit	Line	Data
2809b317 JC	1	/*
	2	* This program is free software; you can redistribute it and/or modify it
	3	* under the terms of the GNU General Public License version 2 as published
	4	* by the Free Software Foundation.
	5	*
	6	* Parts of this file are based on Ralink's 2.6.21 BSP
	7	*
	8	* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
	9	* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
	10	* Copyright (C) 2013 John Crispin <blogic@openwrt.org>
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/init.h>
	15	#include <linux/module.h>
	16
	17	#include <asm/mipsregs.h>
	18	#include <asm/mach-ralink/ralink_regs.h>
	19	#include <asm/mach-ralink/rt305x.h>
	20
	21	#include "common.h"
	22
	23	enum rt305x_soc_type rt305x_soc;
	24
0ba43370	25	static struct ralink_pinmux_grp mode_mux[] = {
2809b317 JC	26	{
	27	.name = "i2c",
	28	.mask = RT305X_GPIO_MODE_I2C,
	29	.gpio_first = RT305X_GPIO_I2C_SD,
	30	.gpio_last = RT305X_GPIO_I2C_SCLK,
	31	}, {
	32	.name = "spi",
	33	.mask = RT305X_GPIO_MODE_SPI,
	34	.gpio_first = RT305X_GPIO_SPI_EN,
	35	.gpio_last = RT305X_GPIO_SPI_CLK,
	36	}, {
	37	.name = "uartlite",
	38	.mask = RT305X_GPIO_MODE_UART1,
	39	.gpio_first = RT305X_GPIO_UART1_TXD,
	40	.gpio_last = RT305X_GPIO_UART1_RXD,
	41	}, {
	42	.name = "jtag",
	43	.mask = RT305X_GPIO_MODE_JTAG,
	44	.gpio_first = RT305X_GPIO_JTAG_TDO,
	45	.gpio_last = RT305X_GPIO_JTAG_TDI,
	46	}, {
	47	.name = "mdio",
	48	.mask = RT305X_GPIO_MODE_MDIO,
	49	.gpio_first = RT305X_GPIO_MDIO_MDC,
	50	.gpio_last = RT305X_GPIO_MDIO_MDIO,
	51	}, {
	52	.name = "sdram",
	53	.mask = RT305X_GPIO_MODE_SDRAM,
	54	.gpio_first = RT305X_GPIO_SDRAM_MD16,
	55	.gpio_last = RT305X_GPIO_SDRAM_MD31,
	56	}, {
	57	.name = "rgmii",
	58	.mask = RT305X_GPIO_MODE_RGMII,
	59	.gpio_first = RT305X_GPIO_GE0_TXD0,
	60	.gpio_last = RT305X_GPIO_GE0_RXCLK,
	61	}, {0}
	62	};
	63
0ba43370	64	static struct ralink_pinmux_grp uart_mux[] = {
2809b317 JC	65	{
	66	.name = "uartf",
	67	.mask = RT305X_GPIO_MODE_UARTF,
	68	.gpio_first = RT305X_GPIO_7,
	69	.gpio_last = RT305X_GPIO_14,
	70	}, {
	71	.name = "pcm uartf",
	72	.mask = RT305X_GPIO_MODE_PCM_UARTF,
	73	.gpio_first = RT305X_GPIO_7,
	74	.gpio_last = RT305X_GPIO_14,
	75	}, {
	76	.name = "pcm i2s",
	77	.mask = RT305X_GPIO_MODE_PCM_I2S,
	78	.gpio_first = RT305X_GPIO_7,
	79	.gpio_last = RT305X_GPIO_14,
	80	}, {
	81	.name = "i2s uartf",
	82	.mask = RT305X_GPIO_MODE_I2S_UARTF,
	83	.gpio_first = RT305X_GPIO_7,
	84	.gpio_last = RT305X_GPIO_14,
	85	}, {
	86	.name = "pcm gpio",
	87	.mask = RT305X_GPIO_MODE_PCM_GPIO,
	88	.gpio_first = RT305X_GPIO_10,
	89	.gpio_last = RT305X_GPIO_14,
	90	}, {
	91	.name = "gpio uartf",
	92	.mask = RT305X_GPIO_MODE_GPIO_UARTF,
	93	.gpio_first = RT305X_GPIO_7,
eb63875c	94	.gpio_last = RT305X_GPIO_10,
2809b317 JC	95	}, {
	96	.name = "gpio i2s",
	97	.mask = RT305X_GPIO_MODE_GPIO_I2S,
	98	.gpio_first = RT305X_GPIO_7,
eb63875c	99	.gpio_last = RT305X_GPIO_10,
2809b317 JC	100	}, {
	101	.name = "gpio",
	102	.mask = RT305X_GPIO_MODE_GPIO,
	103	}, {0}
	104	};
	105
0ba43370	106	static void rt305x_wdt_reset(void)
2809b317 JC	107	{
	108	u32 t;
	109
	110	/* enable WDT reset output on pin SRAM_CS_N */
	111	t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
	112	t \|= RT305X_SYSCFG_SRAM_CS0_MODE_WDT <<
	113	RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT;
	114	rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
	115	}
	116
4114b6a6	117	struct ralink_pinmux rt_gpio_pinmux = {
2809b317 JC	118	.mode = mode_mux,
	119	.uart = uart_mux,
	120	.uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
eb63875c	121	.uart_mask = RT305X_GPIO_MODE_UART0_MASK,
2809b317 JC	122	.wdt_reset = rt305x_wdt_reset,
	123	};
	124
	125	void __init ralink_clk_init(void)
	126	{
	127	unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
6ac8579b JC	128	unsigned long wmac_rate = 40000000;
6ac8579b JC	129
2809b317 JC	130	u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
	131
	132	if (soc_is_rt305x() \|\| soc_is_rt3350()) {
	133	t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
	134	RT305X_SYSCFG_CPUCLK_MASK;
	135	switch (t) {
	136	case RT305X_SYSCFG_CPUCLK_LOW:
	137	cpu_rate = 320000000;
	138	break;
	139	case RT305X_SYSCFG_CPUCLK_HIGH:
	140	cpu_rate = 384000000;
	141	break;
	142	}
	143	sys_rate = uart_rate = wdt_rate = cpu_rate / 3;
	144	} else if (soc_is_rt3352()) {
	145	t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) &
	146	RT3352_SYSCFG0_CPUCLK_MASK;
	147	switch (t) {
	148	case RT3352_SYSCFG0_CPUCLK_LOW:
	149	cpu_rate = 384000000;
	150	break;
	151	case RT3352_SYSCFG0_CPUCLK_HIGH:
	152	cpu_rate = 400000000;
	153	break;
	154	}
	155	sys_rate = wdt_rate = cpu_rate / 3;
	156	uart_rate = 40000000;
	157	} else if (soc_is_rt5350()) {
	158	t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) &
	159	RT5350_SYSCFG0_CPUCLK_MASK;
	160	switch (t) {
	161	case RT5350_SYSCFG0_CPUCLK_360:
	162	cpu_rate = 360000000;
	163	sys_rate = cpu_rate / 3;
	164	break;
	165	case RT5350_SYSCFG0_CPUCLK_320:
	166	cpu_rate = 320000000;
	167	sys_rate = cpu_rate / 4;
	168	break;
	169	case RT5350_SYSCFG0_CPUCLK_300:
	170	cpu_rate = 300000000;
	171	sys_rate = cpu_rate / 3;
	172	break;
	173	default:
	174	BUG();
	175	}
	176	uart_rate = 40000000;
	177	wdt_rate = sys_rate;
	178	} else {
	179	BUG();
	180	}
	181
6ac8579b JC	182	if (soc_is_rt3352() \|\| soc_is_rt5350()) {
	183	u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
	184
	185	if (!(val & RT3352_CLKCFG0_XTAL_SEL))
	186	wmac_rate = 20000000;
	187	}
	188
2809b317 JC	189	ralink_clk_add("cpu", cpu_rate);
	190	ralink_clk_add("10000b00.spi", sys_rate);
	191	ralink_clk_add("10000100.timer", wdt_rate);
6ac8579b	192	ralink_clk_add("10000120.watchdog", wdt_rate);
2809b317 JC	193	ralink_clk_add("10000500.uart", uart_rate);
2809b317 JC	194	ralink_clk_add("10000c00.uartlite", uart_rate);
6ac8579b JC	195	ralink_clk_add("10100000.ethernet", sys_rate);
6ac8579b JC	196	ralink_clk_add("10180000.wmac", wmac_rate);
2809b317 JC	197	}
	198
	199	void __init ralink_of_remap(void)
	200	{
	201	rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc");
	202	rt_memc_membase = plat_of_remap_node("ralink,rt3050-memc");
	203
	204	if (!rt_sysc_membase \|\| !rt_memc_membase)
	205	panic("Failed to remap core resources");
	206	}
	207
	208	void prom_soc_init(struct ralink_soc_info *soc_info)
	209	{
	210	void __iomem sysc = (void __iomem ) KSEG1ADDR(RT305X_SYSC_BASE);
	211	unsigned char *name;
	212	u32 n0;
	213	u32 n1;
	214	u32 id;
	215
	216	n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
	217	n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
	218
	219	if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) {
	220	unsigned long icache_sets;
	221
	222	icache_sets = (read_c0_config1() >> 22) & 7;
	223	if (icache_sets == 1) {
	224	rt305x_soc = RT305X_SOC_RT3050;
	225	name = "RT3050";
	226	soc_info->compatible = "ralink,rt3050-soc";
	227	} else {
	228	rt305x_soc = RT305X_SOC_RT3052;
	229	name = "RT3052";
	230	soc_info->compatible = "ralink,rt3052-soc";
	231	}
	232	} else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) {
	233	rt305x_soc = RT305X_SOC_RT3350;
	234	name = "RT3350";
	235	soc_info->compatible = "ralink,rt3350-soc";
	236	} else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) {
	237	rt305x_soc = RT305X_SOC_RT3352;
	238	name = "RT3352";
	239	soc_info->compatible = "ralink,rt3352-soc";
	240	} else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) {
	241	rt305x_soc = RT305X_SOC_RT5350;
	242	name = "RT5350";
	243	soc_info->compatible = "ralink,rt5350-soc";
	244	} else {
	245	panic("rt305x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
	246	}
	247
	248	id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
	249
	250	snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
	251	"Ralink %s id:%u rev:%u",
	252	name,
	253	(id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
	254	(id & CHIP_ID_REV_MASK));
	255	}