[deliverable/linux.git] / arch / mips / rb532 / devices.c

/*
 *  RouterBoard 500 Platform devices
 *
 *  Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
 *  Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 *  GNU General Public License for more details.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/ctype.h>
#include <linux/string.h>
#include <linux/platform_device.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/serial_8250.h>

#include <asm/bootinfo.h>

#include <asm/mach-rc32434/rc32434.h>
#include <asm/mach-rc32434/dma.h>
#include <asm/mach-rc32434/dma_v.h>
#include <asm/mach-rc32434/eth.h>
#include <asm/mach-rc32434/rb.h>
#include <asm/mach-rc32434/integ.h>
#include <asm/mach-rc32434/gpio.h>
#include <asm/mach-rc32434/irq.h>

#define ETH0_RX_DMA_ADDR  (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET)
#define ETH0_TX_DMA_ADDR  (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET)

extern unsigned int idt_cpu_freq;

static struct mpmc_device dev3;

void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
{
	unsigned long flags;

	spin_lock_irqsave(&dev3.lock, flags);

	dev3.state = (dev3.state | or_mask) & ~nand_mask;
	writeb(dev3.state, dev3.base);

	spin_unlock_irqrestore(&dev3.lock, flags);
}
EXPORT_SYMBOL(set_latch_u5);

unsigned char get_latch_u5(void)
{
	return dev3.state;
}
EXPORT_SYMBOL(get_latch_u5);

static struct resource korina_dev0_res[] = {
	{
		.name = "korina_regs",
		.start = ETH0_BASE_ADDR,
		.end = ETH0_BASE_ADDR + sizeof(struct eth_regs),
		.flags = IORESOURCE_MEM,
	 }, {
		.name = "korina_rx",
		.start = ETH0_DMA_RX_IRQ,
		.end = ETH0_DMA_RX_IRQ,
		.flags = IORESOURCE_IRQ
	}, {
		.name = "korina_tx",
		.start = ETH0_DMA_TX_IRQ,
		.end = ETH0_DMA_TX_IRQ,
		.flags = IORESOURCE_IRQ
	}, {
		.name = "korina_ovr",
		.start = ETH0_RX_OVR_IRQ,
		.end = ETH0_RX_OVR_IRQ,
		.flags = IORESOURCE_IRQ
	}, {
		.name = "korina_und",
		.start = ETH0_TX_UND_IRQ,
		.end = ETH0_TX_UND_IRQ,
		.flags = IORESOURCE_IRQ
	}, {
		.name = "korina_dma_rx",
		.start = ETH0_RX_DMA_ADDR,
		.end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
		.flags = IORESOURCE_MEM,
	 }, {
		.name = "korina_dma_tx",
		.start = ETH0_TX_DMA_ADDR,
		.end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
		.flags = IORESOURCE_MEM,
	 }
};

static struct korina_device korina_dev0_data = {
	.name = "korina0",
	.mac = {0xde, 0xca, 0xff, 0xc0, 0xff, 0xee}
};

static struct platform_device korina_dev0 = {
	.id = -1,
	.name = "korina",
	.resource = korina_dev0_res,
	.num_resources = ARRAY_SIZE(korina_dev0_res),
};

static struct resource cf_slot0_res[] = {
	{
		.name = "cf_membase",
		.flags = IORESOURCE_MEM
	}, {
		.name = "cf_irq",
		.start = (8 + 4 * 32 + CF_GPIO_NUM),	/* 149 */
		.end = (8 + 4 * 32 + CF_GPIO_NUM),
		.flags = IORESOURCE_IRQ
	}
};

static struct cf_device cf_slot0_data = {
	.gpio_pin = CF_GPIO_NUM
};

static struct platform_device cf_slot0 = {
	.id = -1,
	.name = "pata-rb532-cf",
	.dev.platform_data = &cf_slot0_data,
	.resource = cf_slot0_res,
	.num_resources = ARRAY_SIZE(cf_slot0_res),
};

/* Resources and device for NAND */
static int rb532_dev_ready(struct mtd_info *mtd)
{
	return gpio_get_value(GPIO_RDY);
}

static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
	struct nand_chip *chip = mtd->priv;
	unsigned char orbits, nandbits;

	if (ctrl & NAND_CTRL_CHANGE) {
		orbits = (ctrl & NAND_CLE) << 1;
		orbits |= (ctrl & NAND_ALE) >> 1;

		nandbits = (~ctrl & NAND_CLE) << 1;
		nandbits |= (~ctrl & NAND_ALE) >> 1;

		set_latch_u5(orbits, nandbits);
	}
	if (cmd != NAND_CMD_NONE)
		writeb(cmd, chip->IO_ADDR_W);
}

static struct resource nand_slot0_res[] = {
	[0] = {
		.name = "nand_membase",
		.flags = IORESOURCE_MEM
	}
};

static struct platform_nand_data rb532_nand_data = {
	.ctrl.dev_ready = rb532_dev_ready,
	.ctrl.cmd_ctrl	= rb532_cmd_ctrl,
};

static struct platform_device nand_slot0 = {
	.name = "gen_nand",
	.id = -1,
	.resource = nand_slot0_res,
	.num_resources = ARRAY_SIZE(nand_slot0_res),
	.dev.platform_data = &rb532_nand_data,
};

static struct mtd_partition rb532_partition_info[] = {
	{
		.name = "Routerboard NAND boot",
		.offset = 0,
		.size = 4 * 1024 * 1024,
	}, {
		.name = "rootfs",
		.offset = MTDPART_OFS_NXTBLK,
		.size = MTDPART_SIZ_FULL,
	}
};

static struct platform_device rb532_led = {
	.name = "rb532-led",
	.id = -1,
};

static struct platform_device rb532_button = {
	.name	= "rb532-button",
	.id	= -1,
};

static struct resource rb532_wdt_res[] = {
	{
		.name = "rb532_wdt_res",
		.start = INTEG0_BASE_ADDR,
		.end = INTEG0_BASE_ADDR + sizeof(struct integ),
		.flags = IORESOURCE_MEM,
	}
};

static struct platform_device rb532_wdt = {
	.name 		= "rc32434_wdt",
	.id 		= -1,
	.resource 	= rb532_wdt_res,
	.num_resources	= ARRAY_SIZE(rb532_wdt_res),
};

static struct plat_serial8250_port rb532_uart_res[] = {
	{
		.membase	= (char *)KSEG1ADDR(REGBASE + UART0BASE),
		.irq		= UART0_IRQ,
		.regshift	= 2,
		.iotype		= UPIO_MEM,
		.flags		= UPF_BOOT_AUTOCONF,
	},
	{
		.flags		= 0,
	}
};

static struct platform_device rb532_uart = {
	.name              = "serial8250",
	.id                = PLAT8250_DEV_PLATFORM,
	.dev.platform_data = &rb532_uart_res,
};

static struct platform_device *rb532_devs[] = {
	&korina_dev0,
	&nand_slot0,
	&cf_slot0,
	&rb532_led,
	&rb532_button,
	&rb532_uart,
	&rb532_wdt
};

static void __init parse_mac_addr(char *macstr)
{
	int i, h, l;

	for (i = 0; i < 6; i++) {
		if (i != 5 && *(macstr + 2) != ':')
			return;

		h = hex_to_bin(*macstr++);
		if (h == -1)
			return;

		l = hex_to_bin(*macstr++);
		if (l == -1)
			return;

		macstr++;
		korina_dev0_data.mac[i] = (h << 4) + l;
	}
}


/* NAND definitions */
#define NAND_CHIP_DELAY	25

static void __init rb532_nand_setup(void)
{
	switch (mips_machtype) {
	case MACH_MIKROTIK_RB532A:
		set_latch_u5(LO_FOFF | LO_CEX,
				LO_ULED | LO_ALE | LO_CLE | LO_WPX);
		break;
	default:
		set_latch_u5(LO_WPX | LO_FOFF | LO_CEX,
				LO_ULED | LO_ALE | LO_CLE);
		break;
	}

	/* Setup NAND specific settings */
	rb532_nand_data.chip.nr_chips = 1;
	rb532_nand_data.chip.nr_partitions = ARRAY_SIZE(rb532_partition_info);
	rb532_nand_data.chip.partitions = rb532_partition_info;
	rb532_nand_data.chip.chip_delay = NAND_CHIP_DELAY;
}


static int __init plat_setup_devices(void)
{
	/* Look for the CF card reader */
	if (!readl(IDT434_REG_BASE + DEV1MASK))
		rb532_devs[2] = NULL;	/* disable cf_slot0 at index 2 */
	else {
		cf_slot0_res[0].start =
		    readl(IDT434_REG_BASE + DEV1BASE);
		cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
	}

	/* Read the NAND resources from the device controller */
	nand_slot0_res[0].start = readl(IDT434_REG_BASE + DEV2BASE);
	nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;

	/* Read and map device controller 3 */
	dev3.base = ioremap_nocache(readl(IDT434_REG_BASE + DEV3BASE), 1);

	if (!dev3.base) {
		printk(KERN_ERR "rb532: cannot remap device controller 3\n");
		return -ENXIO;
	}

	/* Initialise the NAND device */
	rb532_nand_setup();

	/* set the uart clock to the current cpu frequency */
	rb532_uart_res[0].uartclk = idt_cpu_freq;

	dev_set_drvdata(&korina_dev0.dev, &korina_dev0_data);

	return platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs));
}

static int __init setup_kmac(char *s)
{
	printk(KERN_INFO "korina mac = %s\n", s);
	parse_mac_addr(s);
	return 0;
}

__setup("kmac=", setup_kmac);

arch_initcall(plat_setup_devices);
Commit	Line	Data
73b4390f RB	1	/*
	2	* RouterBoard 500 Platform devices
	3	*
	4	* Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
	5	* Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17	#include <linux/kernel.h>
	18	#include <linux/init.h>
	19	#include <linux/ctype.h>
	20	#include <linux/string.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/mtd/nand.h>
	23	#include <linux/mtd/mtd.h>
	24	#include <linux/mtd/partitions.h>
	25	#include <linux/gpio_keys.h>
	26	#include <linux/input.h>
1452fc7d	27	#include <linux/serial_8250.h>
73b4390f RB	28
	29	#include <asm/bootinfo.h>
	30
	31	#include <asm/mach-rc32434/rc32434.h>
	32	#include <asm/mach-rc32434/dma.h>
	33	#include <asm/mach-rc32434/dma_v.h>
	34	#include <asm/mach-rc32434/eth.h>
	35	#include <asm/mach-rc32434/rb.h>
	36	#include <asm/mach-rc32434/integ.h>
	37	#include <asm/mach-rc32434/gpio.h>
3cd4e067	38	#include <asm/mach-rc32434/irq.h>
73b4390f RB	39
	40	#define ETH0_RX_DMA_ADDR (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET)
	41	#define ETH0_TX_DMA_ADDR (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET)
	42
1452fc7d PS	43	extern unsigned int idt_cpu_freq;
1452fc7d PS	44
36f2db4b PS	45	static struct mpmc_device dev3;
	46
	47	void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
	48	{
	49	unsigned long flags;
	50
	51	spin_lock_irqsave(&dev3.lock, flags);
	52
	53	dev3.state = (dev3.state \| or_mask) & ~nand_mask;
	54	writeb(dev3.state, dev3.base);
	55
	56	spin_unlock_irqrestore(&dev3.lock, flags);
	57	}
	58	EXPORT_SYMBOL(set_latch_u5);
	59
	60	unsigned char get_latch_u5(void)
	61	{
	62	return dev3.state;
	63	}
	64	EXPORT_SYMBOL(get_latch_u5);
	65
73b4390f RB	66	static struct resource korina_dev0_res[] = {
	67	{
	68	.name = "korina_regs",
	69	.start = ETH0_BASE_ADDR,
	70	.end = ETH0_BASE_ADDR + sizeof(struct eth_regs),
	71	.flags = IORESOURCE_MEM,
	72	}, {
	73	.name = "korina_rx",
	74	.start = ETH0_DMA_RX_IRQ,
	75	.end = ETH0_DMA_RX_IRQ,
	76	.flags = IORESOURCE_IRQ
	77	}, {
	78	.name = "korina_tx",
	79	.start = ETH0_DMA_TX_IRQ,
	80	.end = ETH0_DMA_TX_IRQ,
	81	.flags = IORESOURCE_IRQ
	82	}, {
	83	.name = "korina_ovr",
	84	.start = ETH0_RX_OVR_IRQ,
	85	.end = ETH0_RX_OVR_IRQ,
	86	.flags = IORESOURCE_IRQ
	87	}, {
	88	.name = "korina_und",
	89	.start = ETH0_TX_UND_IRQ,
	90	.end = ETH0_TX_UND_IRQ,
	91	.flags = IORESOURCE_IRQ
	92	}, {
	93	.name = "korina_dma_rx",
	94	.start = ETH0_RX_DMA_ADDR,
	95	.end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
	96	.flags = IORESOURCE_MEM,
	97	}, {
	98	.name = "korina_dma_tx",
	99	.start = ETH0_TX_DMA_ADDR,
	100	.end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
	101	.flags = IORESOURCE_MEM,
	102	}
	103	};
	104
	105	static struct korina_device korina_dev0_data = {
	106	.name = "korina0",
	107	.mac = {0xde, 0xca, 0xff, 0xc0, 0xff, 0xee}
	108	};
	109
	110	static struct platform_device korina_dev0 = {
b6e2f58a	111	.id = -1,
73b4390f	112	.name = "korina",
73b4390f RB	113	.resource = korina_dev0_res,
	114	.num_resources = ARRAY_SIZE(korina_dev0_res),
	115	};
	116
73b4390f RB	117	static struct resource cf_slot0_res[] = {
	118	{
	119	.name = "cf_membase",
	120	.flags = IORESOURCE_MEM
	121	}, {
	122	.name = "cf_irq",
	123	.start = (8 + 4 * 32 + CF_GPIO_NUM), /* 149 */
	124	.end = (8 + 4 * 32 + CF_GPIO_NUM),
	125	.flags = IORESOURCE_IRQ
	126	}
	127	};
	128
	129	static struct cf_device cf_slot0_data = {
3cd4e067	130	.gpio_pin = CF_GPIO_NUM
73b4390f RB	131	};
	132
	133	static struct platform_device cf_slot0 = {
b6e2f58a	134	.id = -1,
73b4390f RB	135	.name = "pata-rb532-cf",
	136	.dev.platform_data = &cf_slot0_data,
	137	.resource = cf_slot0_res,
	138	.num_resources = ARRAY_SIZE(cf_slot0_res),
	139	};
	140
	141	/* Resources and device for NAND */
	142	static int rb532_dev_ready(struct mtd_info *mtd)
	143	{
1b432840	144	return gpio_get_value(GPIO_RDY);
73b4390f RB	145	}
	146
	147	static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
	148	{
	149	struct nand_chip *chip = mtd->priv;
	150	unsigned char orbits, nandbits;
	151
	152	if (ctrl & NAND_CTRL_CHANGE) {
	153	orbits = (ctrl & NAND_CLE) << 1;
	154	orbits \|= (ctrl & NAND_ALE) >> 1;
	155
	156	nandbits = (~ctrl & NAND_CLE) << 1;
	157	nandbits \|= (~ctrl & NAND_ALE) >> 1;
	158
	159	set_latch_u5(orbits, nandbits);
	160	}
	161	if (cmd != NAND_CMD_NONE)
	162	writeb(cmd, chip->IO_ADDR_W);
	163	}
	164
	165	static struct resource nand_slot0_res[] = {
	166	[0] = {
	167	.name = "nand_membase",
	168	.flags = IORESOURCE_MEM
	169	}
	170	};
	171
	172	static struct platform_nand_data rb532_nand_data = {
	173	.ctrl.dev_ready = rb532_dev_ready,
	174	.ctrl.cmd_ctrl = rb532_cmd_ctrl,
	175	};
	176
	177	static struct platform_device nand_slot0 = {
	178	.name = "gen_nand",
	179	.id = -1,
	180	.resource = nand_slot0_res,
	181	.num_resources = ARRAY_SIZE(nand_slot0_res),
	182	.dev.platform_data = &rb532_nand_data,
	183	};
	184
	185	static struct mtd_partition rb532_partition_info[] = {
	186	{
	187	.name = "Routerboard NAND boot",
	188	.offset = 0,
	189	.size = 4 * 1024 * 1024,
	190	}, {
	191	.name = "rootfs",
	192	.offset = MTDPART_OFS_NXTBLK,
	193	.size = MTDPART_SIZ_FULL,
	194	}
	195	};
	196
	197	static struct platform_device rb532_led = {
	198	.name = "rb532-led",
b6e2f58a	199	.id = -1,
73b4390f RB	200	};
73b4390f RB	201
73b4390f	202	static struct platform_device rb532_button = {
d9bdffd2	203	.name = "rb532-button",
73b4390f	204	.id = -1,
73b4390f RB	205	};
	206
	207	static struct resource rb532_wdt_res[] = {
	208	{
	209	.name = "rb532_wdt_res",
	210	.start = INTEG0_BASE_ADDR,
	211	.end = INTEG0_BASE_ADDR + sizeof(struct integ),
	212	.flags = IORESOURCE_MEM,
	213	}
	214	};
	215
	216	static struct platform_device rb532_wdt = {
	217	.name = "rc32434_wdt",
	218	.id = -1,
	219	.resource = rb532_wdt_res,
	220	.num_resources = ARRAY_SIZE(rb532_wdt_res),
	221	};
	222
1452fc7d PS	223	static struct plat_serial8250_port rb532_uart_res[] = {
	224	{
	225	.membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
	226	.irq = UART0_IRQ,
	227	.regshift = 2,
	228	.iotype = UPIO_MEM,
	229	.flags = UPF_BOOT_AUTOCONF,
	230	},
	231	{
	232	.flags = 0,
	233	}
	234	};
	235
	236	static struct platform_device rb532_uart = {
	237	.name = "serial8250",
	238	.id = PLAT8250_DEV_PLATFORM,
	239	.dev.platform_data = &rb532_uart_res,
	240	};
	241
73b4390f RB	242	static struct platform_device *rb532_devs[] = {
	243	&korina_dev0,
	244	&nand_slot0,
	245	&cf_slot0,
	246	&rb532_led,
	247	&rb532_button,
1452fc7d	248	&rb532_uart,
73b4390f RB	249	&rb532_wdt
	250	};
	251
	252	static void __init parse_mac_addr(char *macstr)
	253	{
c8e58856	254	int i, h, l;
73b4390f RB	255
73b4390f RB	256	for (i = 0; i < 6; i++) {
73b4390f RB	257	if (i != 5 && *(macstr + 2) != ':')
	258	return;
	259
c8e58856 AS	260	h = hex_to_bin(*macstr++);
	261	if (h == -1)
	262	return;
	263
	264	l = hex_to_bin(*macstr++);
	265	if (l == -1)
	266	return;
73b4390f RB	267
73b4390f RB	268	macstr++;
c8e58856	269	korina_dev0_data.mac[i] = (h << 4) + l;
73b4390f RB	270	}
	271	}
	272
	273
73b4390f RB	274	/* NAND definitions */
	275	#define NAND_CHIP_DELAY 25
	276
	277	static void __init rb532_nand_setup(void)
	278	{
	279	switch (mips_machtype) {
	280	case MACH_MIKROTIK_RB532A:
	281	set_latch_u5(LO_FOFF \| LO_CEX,
	282	LO_ULED \| LO_ALE \| LO_CLE \| LO_WPX);
	283	break;
	284	default:
	285	set_latch_u5(LO_WPX \| LO_FOFF \| LO_CEX,
	286	LO_ULED \| LO_ALE \| LO_CLE);
	287	break;
	288	}
	289
	290	/* Setup NAND specific settings */
	291	rb532_nand_data.chip.nr_chips = 1;
	292	rb532_nand_data.chip.nr_partitions = ARRAY_SIZE(rb532_partition_info);
	293	rb532_nand_data.chip.partitions = rb532_partition_info;
	294	rb532_nand_data.chip.chip_delay = NAND_CHIP_DELAY;
73b4390f RB	295	}
	296
	297
	298	static int __init plat_setup_devices(void)
	299	{
	300	/* Look for the CF card reader */
1ddfe82d	301	if (!readl(IDT434_REG_BASE + DEV1MASK))
bc4c4e83	302	rb532_devs[2] = NULL; /* disable cf_slot0 at index 2 */
73b4390f RB	303	else {
73b4390f RB	304	cf_slot0_res[0].start =
1ddfe82d	305	readl(IDT434_REG_BASE + DEV1BASE);
73b4390f RB	306	cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
	307	}
	308
	309	/* Read the NAND resources from the device controller */
1ddfe82d	310	nand_slot0_res[0].start = readl(IDT434_REG_BASE + DEV2BASE);
73b4390f RB	311	nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
73b4390f RB	312
1c4db8e8 PS	313	/* Read and map device controller 3 */
1c4db8e8 PS	314	dev3.base = ioremap_nocache(readl(IDT434_REG_BASE + DEV3BASE), 1);
36f2db4b PS	315
	316	if (!dev3.base) {
	317	printk(KERN_ERR "rb532: cannot remap device controller 3\n");
	318	return -ENXIO;
	319	}
	320
73b4390f RB	321	/* Initialise the NAND device */
	322	rb532_nand_setup();
	323
1452fc7d PS	324	/* set the uart clock to the current cpu frequency */
	325	rb532_uart_res[0].uartclk = idt_cpu_freq;
	326
4e7c81af FF	327	dev_set_drvdata(&korina_dev0.dev, &korina_dev0_data);
4e7c81af FF	328
73b4390f RB	329	return platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs));
	330	}
	331
	332	static int __init setup_kmac(char *s)
	333	{
	334	printk(KERN_INFO "korina mac = %s\n", s);
	335	parse_mac_addr(s);
	336	return 0;
	337	}
	338
	339	__setup("kmac=", setup_kmac);
	340
	341	arch_initcall(plat_setup_devices);