[deliverable/linux.git] / arch / mips / sgi-ip22 / ip22-int.c

/*
 * ip22-int.c: Routines for generic manipulation of the INT[23] ASIC
 *             found on INDY and Indigo2 workstations.
 *
 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
 * Copyright (C) 1997, 1998 Ralf Baechle (ralf@gnu.org)
 * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu)
 *                    - Indigo2 changes
 *                    - Interrupt handling fixes
 * Copyright (C) 2001, 2003 Ladislav Michl (ladis@linux-mips.org)
 */
#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/interrupt.h>
#include <linux/ftrace.h>

#include <asm/irq_cpu.h>
#include <asm/sgi/hpc3.h>
#include <asm/sgi/ip22.h>

/* So far nothing hangs here */
#undef USE_LIO3_IRQ

struct sgint_regs *sgint;

static char lc0msk_to_irqnr[256];
static char lc1msk_to_irqnr[256];
static char lc2msk_to_irqnr[256];
static char lc3msk_to_irqnr[256];

extern int ip22_eisa_init(void);

static void enable_local0_irq(unsigned int irq)
{
	/* don't allow mappable interrupt to be enabled from setup_irq,
	 * we have our own way to do so */
	if (irq != SGI_MAP_0_IRQ)
		sgint->imask0 |= (1 << (irq - SGINT_LOCAL0));
}

static void disable_local0_irq(unsigned int irq)
{
	sgint->imask0 &= ~(1 << (irq - SGINT_LOCAL0));
}

static struct irq_chip ip22_local0_irq_type = {
	.name		= "IP22 local 0",
	.ack		= disable_local0_irq,
	.mask		= disable_local0_irq,
	.mask_ack	= disable_local0_irq,
	.unmask		= enable_local0_irq,
};

static void enable_local1_irq(unsigned int irq)
{
	/* don't allow mappable interrupt to be enabled from setup_irq,
	 * we have our own way to do so */
	if (irq != SGI_MAP_1_IRQ)
		sgint->imask1 |= (1 << (irq - SGINT_LOCAL1));
}

static void disable_local1_irq(unsigned int irq)
{
	sgint->imask1 &= ~(1 << (irq - SGINT_LOCAL1));
}

static struct irq_chip ip22_local1_irq_type = {
	.name		= "IP22 local 1",
	.ack		= disable_local1_irq,
	.mask		= disable_local1_irq,
	.mask_ack	= disable_local1_irq,
	.unmask		= enable_local1_irq,
};

static void enable_local2_irq(unsigned int irq)
{
	sgint->imask0 |= (1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
	sgint->cmeimask0 |= (1 << (irq - SGINT_LOCAL2));
}

static void disable_local2_irq(unsigned int irq)
{
	sgint->cmeimask0 &= ~(1 << (irq - SGINT_LOCAL2));
	if (!sgint->cmeimask0)
		sgint->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
}

static struct irq_chip ip22_local2_irq_type = {
	.name		= "IP22 local 2",
	.ack		= disable_local2_irq,
	.mask		= disable_local2_irq,
	.mask_ack	= disable_local2_irq,
	.unmask		= enable_local2_irq,
};

static void enable_local3_irq(unsigned int irq)
{
	sgint->imask1 |= (1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
	sgint->cmeimask1 |= (1 << (irq - SGINT_LOCAL3));
}

static void disable_local3_irq(unsigned int irq)
{
	sgint->cmeimask1 &= ~(1 << (irq - SGINT_LOCAL3));
	if (!sgint->cmeimask1)
		sgint->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
}

static struct irq_chip ip22_local3_irq_type = {
	.name		= "IP22 local 3",
	.ack		= disable_local3_irq,
	.mask		= disable_local3_irq,
	.mask_ack	= disable_local3_irq,
	.unmask		= enable_local3_irq,
};

static void indy_local0_irqdispatch(void)
{
	u8 mask = sgint->istat0 & sgint->imask0;
	u8 mask2;
	int irq;

	if (mask & SGINT_ISTAT0_LIO2) {
		mask2 = sgint->vmeistat & sgint->cmeimask0;
		irq = lc2msk_to_irqnr[mask2];
	} else
		irq = lc0msk_to_irqnr[mask];

	/* if irq == 0, then the interrupt has already been cleared */
	if (irq)
		do_IRQ(irq);
}

static void indy_local1_irqdispatch(void)
{
	u8 mask = sgint->istat1 & sgint->imask1;
	u8 mask2;
	int irq;

	if (mask & SGINT_ISTAT1_LIO3) {
		mask2 = sgint->vmeistat & sgint->cmeimask1;
		irq = lc3msk_to_irqnr[mask2];
	} else
		irq = lc1msk_to_irqnr[mask];

	/* if irq == 0, then the interrupt has already been cleared */
	if (irq)
		do_IRQ(irq);
}

extern void ip22_be_interrupt(int irq);

static void __irq_entry indy_buserror_irq(void)
{
	int irq = SGI_BUSERR_IRQ;

	irq_enter();
	kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq));
	ip22_be_interrupt(irq);
	irq_exit();
}

static struct irqaction local0_cascade = {
	.handler	= no_action,
	.flags		= IRQF_DISABLED,
	.name		= "local0 cascade",
};

static struct irqaction local1_cascade = {
	.handler	= no_action,
	.flags		= IRQF_DISABLED,
	.name		= "local1 cascade",
};

static struct irqaction buserr = {
	.handler	= no_action,
	.flags		= IRQF_DISABLED,
	.name		= "Bus Error",
};

static struct irqaction map0_cascade = {
	.handler	= no_action,
	.flags		= IRQF_DISABLED,
	.name		= "mapable0 cascade",
};

#ifdef USE_LIO3_IRQ
static struct irqaction map1_cascade = {
	.handler	= no_action,
	.flags		= IRQF_DISABLED,
	.name		= "mapable1 cascade",
};
#define SGI_INTERRUPTS	SGINT_END
#else
#define SGI_INTERRUPTS	SGINT_LOCAL3
#endif

extern void indy_8254timer_irq(void);

/*
 * IRQs on the INDY look basically (barring software IRQs which we don't use
 * at all) like:
 *
 *	MIPS IRQ	Source
 *      --------        ------
 *             0	Software (ignored)
 *             1        Software (ignored)
 *             2        Local IRQ level zero
 *             3        Local IRQ level one
 *             4        8254 Timer zero
 *             5        8254 Timer one
 *             6        Bus Error
 *             7        R4k timer (what we use)
 *
 * We handle the IRQ according to _our_ priority which is:
 *
 * Highest ----     R4k Timer
 *                  Local IRQ zero
 *                  Local IRQ one
 *                  Bus Error
 *                  8254 Timer zero
 * Lowest  ----     8254 Timer one
 *
 * then we just return, if multiple IRQs are pending then we will just take
 * another exception, big deal.
 */

asmlinkage void plat_irq_dispatch(void)
{
	unsigned int pending = read_c0_status() & read_c0_cause();

	/*
	 * First we check for r4k counter/timer IRQ.
	 */
	if (pending & CAUSEF_IP7)
		do_IRQ(SGI_TIMER_IRQ);
	else if (pending & CAUSEF_IP2)
		indy_local0_irqdispatch();
	else if (pending & CAUSEF_IP3)
		indy_local1_irqdispatch();
	else if (pending & CAUSEF_IP6)
		indy_buserror_irq();
	else if (pending & (CAUSEF_IP4 | CAUSEF_IP5))
		indy_8254timer_irq();
}

void __init arch_init_irq(void)
{
	int i;

	/* Init local mask --> irq tables. */
	for (i = 0; i < 256; i++) {
		if (i & 0x80) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 7;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 7;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 7;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 7;
		} else if (i & 0x40) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 6;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 6;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 6;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 6;
		} else if (i & 0x20) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 5;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 5;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 5;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 5;
		} else if (i & 0x10) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 4;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 4;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 4;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 4;
		} else if (i & 0x08) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 3;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 3;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 3;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 3;
		} else if (i & 0x04) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 2;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 2;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 2;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 2;
		} else if (i & 0x02) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 1;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 1;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 1;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 1;
		} else if (i & 0x01) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 0;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 0;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 0;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 0;
		} else {
			lc0msk_to_irqnr[i] = 0;
			lc1msk_to_irqnr[i] = 0;
			lc2msk_to_irqnr[i] = 0;
			lc3msk_to_irqnr[i] = 0;
		}
	}

	/* Mask out all interrupts. */
	sgint->imask0 = 0;
	sgint->imask1 = 0;
	sgint->cmeimask0 = 0;
	sgint->cmeimask1 = 0;

	/* init CPU irqs */
	mips_cpu_irq_init();

	for (i = SGINT_LOCAL0; i < SGI_INTERRUPTS; i++) {
		struct irq_chip *handler;

		if (i < SGINT_LOCAL1)
			handler		= &ip22_local0_irq_type;
		else if (i < SGINT_LOCAL2)
			handler		= &ip22_local1_irq_type;
		else if (i < SGINT_LOCAL3)
			handler		= &ip22_local2_irq_type;
		else
			handler		= &ip22_local3_irq_type;

		set_irq_chip_and_handler(i, handler, handle_level_irq);
	}

	/* vector handler. this register the IRQ as non-sharable */
	setup_irq(SGI_LOCAL_0_IRQ, &local0_cascade);
	setup_irq(SGI_LOCAL_1_IRQ, &local1_cascade);
	setup_irq(SGI_BUSERR_IRQ, &buserr);

	/* cascade in cascade. i love Indy ;-) */
	setup_irq(SGI_MAP_0_IRQ, &map0_cascade);
#ifdef USE_LIO3_IRQ
	setup_irq(SGI_MAP_1_IRQ, &map1_cascade);
#endif

#ifdef CONFIG_EISA
	if (ip22_is_fullhouse())	/* Only Indigo-2 has EISA stuff */
		ip22_eisa_init();
#endif
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* ip22-int.c: Routines for generic manipulation of the INT[23] ASIC
	3	* found on INDY and Indigo2 workstations.
	4	*
	5	* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
	6	* Copyright (C) 1997, 1998 Ralf Baechle (ralf@gnu.org)
	7	* Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu)
	8	* - Indigo2 changes
	9	* - Interrupt handling fixes
	10	* Copyright (C) 2001, 2003 Ladislav Michl (ladis@linux-mips.org)
	11	*/
1da177e4 LT	12	#include <linux/types.h>
	13	#include <linux/init.h>
	14	#include <linux/kernel_stat.h>
1da177e4	15	#include <linux/interrupt.h>
8f99a162	16	#include <linux/ftrace.h>
1da177e4	17
97dcb82d	18	#include <asm/irq_cpu.h>
1da177e4 LT	19	#include <asm/sgi/hpc3.h>
1da177e4 LT	20	#include <asm/sgi/ip22.h>
1da177e4 LT	21
1da177e4 LT	22	/* So far nothing hangs here */
42a3b4f2	23	#undef USE_LIO3_IRQ
1da177e4 LT	24
	25	struct sgint_regs *sgint;
	26
	27	static char lc0msk_to_irqnr[256];
	28	static char lc1msk_to_irqnr[256];
	29	static char lc2msk_to_irqnr[256];
	30	static char lc3msk_to_irqnr[256];
	31
1da177e4 LT	32	extern int ip22_eisa_init(void);
	33
	34	static void enable_local0_irq(unsigned int irq)
	35	{
1da177e4 LT	36	/* don't allow mappable interrupt to be enabled from setup_irq,
	37	* we have our own way to do so */
	38	if (irq != SGI_MAP_0_IRQ)
	39	sgint->imask0 \|= (1 << (irq - SGINT_LOCAL0));
1da177e4 LT	40	}
	41
	42	static void disable_local0_irq(unsigned int irq)
	43	{
1da177e4	44	sgint->imask0 &= ~(1 << (irq - SGINT_LOCAL0));
1da177e4 LT	45	}
1da177e4 LT	46
94dee171	47	static struct irq_chip ip22_local0_irq_type = {
70d21cde	48	.name = "IP22 local 0",
1603b5ac AN	49	.ack = disable_local0_irq,
	50	.mask = disable_local0_irq,
	51	.mask_ack = disable_local0_irq,
	52	.unmask = enable_local0_irq,
1da177e4 LT	53	};
	54
	55	static void enable_local1_irq(unsigned int irq)
	56	{
1da177e4 LT	57	/* don't allow mappable interrupt to be enabled from setup_irq,
	58	* we have our own way to do so */
	59	if (irq != SGI_MAP_1_IRQ)
	60	sgint->imask1 \|= (1 << (irq - SGINT_LOCAL1));
1da177e4 LT	61	}
1da177e4 LT	62
14823ccb	63	static void disable_local1_irq(unsigned int irq)
1da177e4	64	{
1da177e4	65	sgint->imask1 &= ~(1 << (irq - SGINT_LOCAL1));
1da177e4 LT	66	}
1da177e4 LT	67
94dee171	68	static struct irq_chip ip22_local1_irq_type = {
70d21cde	69	.name = "IP22 local 1",
1603b5ac AN	70	.ack = disable_local1_irq,
	71	.mask = disable_local1_irq,
	72	.mask_ack = disable_local1_irq,
	73	.unmask = enable_local1_irq,
1da177e4 LT	74	};
	75
	76	static void enable_local2_irq(unsigned int irq)
	77	{
1da177e4 LT	78	sgint->imask0 \|= (1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
1da177e4 LT	79	sgint->cmeimask0 \|= (1 << (irq - SGINT_LOCAL2));
1da177e4 LT	80	}
1da177e4 LT	81
14823ccb	82	static void disable_local2_irq(unsigned int irq)
1da177e4	83	{
1da177e4 LT	84	sgint->cmeimask0 &= ~(1 << (irq - SGINT_LOCAL2));
	85	if (!sgint->cmeimask0)
	86	sgint->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
1da177e4 LT	87	}
1da177e4 LT	88
94dee171	89	static struct irq_chip ip22_local2_irq_type = {
70d21cde	90	.name = "IP22 local 2",
1603b5ac AN	91	.ack = disable_local2_irq,
	92	.mask = disable_local2_irq,
	93	.mask_ack = disable_local2_irq,
	94	.unmask = enable_local2_irq,
1da177e4 LT	95	};
	96
	97	static void enable_local3_irq(unsigned int irq)
	98	{
1da177e4 LT	99	sgint->imask1 \|= (1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
1da177e4 LT	100	sgint->cmeimask1 \|= (1 << (irq - SGINT_LOCAL3));
1da177e4 LT	101	}
1da177e4 LT	102
14823ccb	103	static void disable_local3_irq(unsigned int irq)
1da177e4	104	{
1da177e4 LT	105	sgint->cmeimask1 &= ~(1 << (irq - SGINT_LOCAL3));
	106	if (!sgint->cmeimask1)
	107	sgint->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
1da177e4 LT	108	}
1da177e4 LT	109
94dee171	110	static struct irq_chip ip22_local3_irq_type = {
70d21cde	111	.name = "IP22 local 3",
1603b5ac AN	112	.ack = disable_local3_irq,
	113	.mask = disable_local3_irq,
	114	.mask_ack = disable_local3_irq,
	115	.unmask = enable_local3_irq,
1da177e4 LT	116	};
1da177e4 LT	117
937a8015	118	static void indy_local0_irqdispatch(void)
1da177e4 LT	119	{
	120	u8 mask = sgint->istat0 & sgint->imask0;
	121	u8 mask2;
	122	int irq;
	123
	124	if (mask & SGINT_ISTAT0_LIO2) {
	125	mask2 = sgint->vmeistat & sgint->cmeimask0;
	126	irq = lc2msk_to_irqnr[mask2];
	127	} else
	128	irq = lc0msk_to_irqnr[mask];
	129
	130	/* if irq == 0, then the interrupt has already been cleared */
	131	if (irq)
937a8015	132	do_IRQ(irq);
1da177e4 LT	133	}
1da177e4 LT	134
937a8015	135	static void indy_local1_irqdispatch(void)
1da177e4 LT	136	{
	137	u8 mask = sgint->istat1 & sgint->imask1;
	138	u8 mask2;
	139	int irq;
	140
	141	if (mask & SGINT_ISTAT1_LIO3) {
	142	mask2 = sgint->vmeistat & sgint->cmeimask1;
	143	irq = lc3msk_to_irqnr[mask2];
	144	} else
	145	irq = lc1msk_to_irqnr[mask];
	146
	147	/* if irq == 0, then the interrupt has already been cleared */
	148	if (irq)
937a8015	149	do_IRQ(irq);
1da177e4 LT	150	}
1da177e4 LT	151
937a8015	152	extern void ip22_be_interrupt(int irq);
1da177e4	153
8f99a162	154	static void __irq_entry indy_buserror_irq(void)
1da177e4 LT	155	{
	156	int irq = SGI_BUSERR_IRQ;
	157
	158	irq_enter();
d2287f5e	159	kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq));
937a8015	160	ip22_be_interrupt(irq);
1da177e4 LT	161	irq_exit();
	162	}
	163
42a3b4f2	164	static struct irqaction local0_cascade = {
1da177e4	165	.handler = no_action,
f40298fd	166	.flags = IRQF_DISABLED,
1da177e4 LT	167	.name = "local0 cascade",
	168	};
	169
42a3b4f2	170	static struct irqaction local1_cascade = {
1da177e4	171	.handler = no_action,
f40298fd	172	.flags = IRQF_DISABLED,
1da177e4 LT	173	.name = "local1 cascade",
	174	};
	175
42a3b4f2	176	static struct irqaction buserr = {
1da177e4	177	.handler = no_action,
f40298fd	178	.flags = IRQF_DISABLED,
1da177e4 LT	179	.name = "Bus Error",
	180	};
	181
42a3b4f2	182	static struct irqaction map0_cascade = {
1da177e4	183	.handler = no_action,
f40298fd	184	.flags = IRQF_DISABLED,
1da177e4 LT	185	.name = "mapable0 cascade",
	186	};
	187
	188	#ifdef USE_LIO3_IRQ
42a3b4f2	189	static struct irqaction map1_cascade = {
1da177e4	190	.handler = no_action,
f40298fd	191	.flags = IRQF_DISABLED,
1da177e4 LT	192	.name = "mapable1 cascade",
	193	};
	194	#define SGI_INTERRUPTS SGINT_END
	195	#else
	196	#define SGI_INTERRUPTS SGINT_LOCAL3
	197	#endif
	198
937a8015	199	extern void indy_8254timer_irq(void);
e4ac58af RB	200
	201	/*
	202	* IRQs on the INDY look basically (barring software IRQs which we don't use
	203	* at all) like:
	204	*
	205	* MIPS IRQ Source
	206	* -------- ------
	207	* 0 Software (ignored)
	208	* 1 Software (ignored)
	209	* 2 Local IRQ level zero
	210	* 3 Local IRQ level one
	211	* 4 8254 Timer zero
	212	* 5 8254 Timer one
	213	* 6 Bus Error
	214	* 7 R4k timer (what we use)
	215	*
	216	* We handle the IRQ according to _our_ priority which is:
	217	*
	218	* Highest ---- R4k Timer
	219	* Local IRQ zero
	220	* Local IRQ one
	221	* Bus Error
	222	* 8254 Timer zero
	223	* Lowest ---- 8254 Timer one
	224	*
	225	* then we just return, if multiple IRQs are pending then we will just take
	226	* another exception, big deal.
	227	*/
	228
937a8015	229	asmlinkage void plat_irq_dispatch(void)
e4ac58af	230	{
119537c0	231	unsigned int pending = read_c0_status() & read_c0_cause();
e4ac58af RB	232
	233	/*
	234	* First we check for r4k counter/timer IRQ.
	235	*/
	236	if (pending & CAUSEF_IP7)
7bcf7717	237	do_IRQ(SGI_TIMER_IRQ);
e4ac58af	238	else if (pending & CAUSEF_IP2)
937a8015	239	indy_local0_irqdispatch();
e4ac58af	240	else if (pending & CAUSEF_IP3)
937a8015	241	indy_local1_irqdispatch();
e4ac58af	242	else if (pending & CAUSEF_IP6)
937a8015	243	indy_buserror_irq();
e4ac58af	244	else if (pending & (CAUSEF_IP4 \| CAUSEF_IP5))
937a8015	245	indy_8254timer_irq();
e4ac58af RB	246	}
e4ac58af RB	247
1da177e4 LT	248	void __init arch_init_irq(void)
	249	{
	250	int i;
	251
	252	/* Init local mask --> irq tables. */
	253	for (i = 0; i < 256; i++) {
	254	if (i & 0x80) {
	255	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 7;
	256	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 7;
	257	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 7;
	258	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 7;
	259	} else if (i & 0x40) {
	260	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 6;
	261	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 6;
	262	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 6;
	263	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 6;
	264	} else if (i & 0x20) {
	265	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 5;
	266	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 5;
	267	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 5;
	268	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 5;
	269	} else if (i & 0x10) {
	270	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 4;
	271	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 4;
	272	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 4;
	273	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 4;
	274	} else if (i & 0x08) {
	275	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 3;
	276	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 3;
	277	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 3;
	278	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 3;
	279	} else if (i & 0x04) {
	280	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 2;
	281	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 2;
	282	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 2;
	283	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 2;
	284	} else if (i & 0x02) {
	285	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 1;
	286	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 1;
	287	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 1;
	288	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 1;
	289	} else if (i & 0x01) {
	290	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 0;
	291	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 0;
	292	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 0;
	293	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 0;
	294	} else {
	295	lc0msk_to_irqnr[i] = 0;
	296	lc1msk_to_irqnr[i] = 0;
	297	lc2msk_to_irqnr[i] = 0;
	298	lc3msk_to_irqnr[i] = 0;
	299	}
	300	}
	301
	302	/* Mask out all interrupts. */
	303	sgint->imask0 = 0;
	304	sgint->imask1 = 0;
	305	sgint->cmeimask0 = 0;
	306	sgint->cmeimask1 = 0;
	307
1da177e4	308	/* init CPU irqs */
97dcb82d	309	mips_cpu_irq_init();
1da177e4 LT	310
1da177e4 LT	311	for (i = SGINT_LOCAL0; i < SGI_INTERRUPTS; i++) {
94dee171	312	struct irq_chip *handler;
1da177e4 LT	313
	314	if (i < SGINT_LOCAL1)
	315	handler = &ip22_local0_irq_type;
	316	else if (i < SGINT_LOCAL2)
	317	handler = &ip22_local1_irq_type;
	318	else if (i < SGINT_LOCAL3)
	319	handler = &ip22_local2_irq_type;
	320	else
	321	handler = &ip22_local3_irq_type;
	322
1417836e	323	set_irq_chip_and_handler(i, handler, handle_level_irq);
1da177e4 LT	324	}
	325
	326	/* vector handler. this register the IRQ as non-sharable */
	327	setup_irq(SGI_LOCAL_0_IRQ, &local0_cascade);
	328	setup_irq(SGI_LOCAL_1_IRQ, &local1_cascade);
	329	setup_irq(SGI_BUSERR_IRQ, &buserr);
	330
	331	/* cascade in cascade. i love Indy ;-) */
	332	setup_irq(SGI_MAP_0_IRQ, &map0_cascade);
	333	#ifdef USE_LIO3_IRQ
	334	setup_irq(SGI_MAP_1_IRQ, &map1_cascade);
	335	#endif
	336
	337	#ifdef CONFIG_EISA
	338	if (ip22_is_fullhouse()) /* Only Indigo-2 has EISA stuff */
14823ccb	339	ip22_eisa_init();
1da177e4 LT	340	#endif
1da177e4 LT	341	}