[deliverable/linux.git] / arch / mips / sgi-ip22 / ip22-int.c

/*
 * ip22-int.c: Routines for generic manipulation of the INT[23] ASIC
 *             found on INDY and Indigo2 workstations.
 *
 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
 * Copyright (C) 1997, 1998 Ralf Baechle (ralf@gnu.org)
 * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu)
 *                    - Indigo2 changes
 *                    - Interrupt handling fixes
 * Copyright (C) 2001, 2003 Ladislav Michl (ladis@linux-mips.org)
 */
#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/interrupt.h>
#include <linux/ftrace.h>

#include <asm/irq_cpu.h>
#include <asm/sgi/hpc3.h>
#include <asm/sgi/ip22.h>

/* So far nothing hangs here */
#undef USE_LIO3_IRQ

struct sgint_regs *sgint;

static char lc0msk_to_irqnr[256];
static char lc1msk_to_irqnr[256];
static char lc2msk_to_irqnr[256];
static char lc3msk_to_irqnr[256];

extern int ip22_eisa_init(void);

static void enable_local0_irq(struct irq_data *d)
{
	/* don't allow mappable interrupt to be enabled from setup_irq,
	 * we have our own way to do so */
	if (d->irq != SGI_MAP_0_IRQ)
		sgint->imask0 |= (1 << (d->irq - SGINT_LOCAL0));
}

static void disable_local0_irq(struct irq_data *d)
{
	sgint->imask0 &= ~(1 << (d->irq - SGINT_LOCAL0));
}

static struct irq_chip ip22_local0_irq_type = {
	.name		= "IP22 local 0",
	.irq_mask	= disable_local0_irq,
	.irq_unmask	= enable_local0_irq,
};

static void enable_local1_irq(struct irq_data *d)
{
	/* don't allow mappable interrupt to be enabled from setup_irq,
	 * we have our own way to do so */
	if (d->irq != SGI_MAP_1_IRQ)
		sgint->imask1 |= (1 << (d->irq - SGINT_LOCAL1));
}

static void disable_local1_irq(struct irq_data *d)
{
	sgint->imask1 &= ~(1 << (d->irq - SGINT_LOCAL1));
}

static struct irq_chip ip22_local1_irq_type = {
	.name		= "IP22 local 1",
	.irq_mask	= disable_local1_irq,
	.irq_unmask	= enable_local1_irq,
};

static void enable_local2_irq(struct irq_data *d)
{
	sgint->imask0 |= (1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
	sgint->cmeimask0 |= (1 << (d->irq - SGINT_LOCAL2));
}

static void disable_local2_irq(struct irq_data *d)
{
	sgint->cmeimask0 &= ~(1 << (d->irq - SGINT_LOCAL2));
	if (!sgint->cmeimask0)
		sgint->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
}

static struct irq_chip ip22_local2_irq_type = {
	.name		= "IP22 local 2",
	.irq_mask	= disable_local2_irq,
	.irq_unmask	= enable_local2_irq,
};

static void enable_local3_irq(struct irq_data *d)
{
	sgint->imask1 |= (1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
	sgint->cmeimask1 |= (1 << (d->irq - SGINT_LOCAL3));
}

static void disable_local3_irq(struct irq_data *d)
{
	sgint->cmeimask1 &= ~(1 << (d->irq - SGINT_LOCAL3));
	if (!sgint->cmeimask1)
		sgint->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
}

static struct irq_chip ip22_local3_irq_type = {
	.name		= "IP22 local 3",
	.irq_mask	= disable_local3_irq,
	.irq_unmask	= enable_local3_irq,
};

static void indy_local0_irqdispatch(void)
{
	u8 mask = sgint->istat0 & sgint->imask0;
	u8 mask2;
	int irq;

	if (mask & SGINT_ISTAT0_LIO2) {
		mask2 = sgint->vmeistat & sgint->cmeimask0;
		irq = lc2msk_to_irqnr[mask2];
	} else
		irq = lc0msk_to_irqnr[mask];

	/* if irq == 0, then the interrupt has already been cleared */
	if (irq)
		do_IRQ(irq);
}

static void indy_local1_irqdispatch(void)
{
	u8 mask = sgint->istat1 & sgint->imask1;
	u8 mask2;
	int irq;

	if (mask & SGINT_ISTAT1_LIO3) {
		mask2 = sgint->vmeistat & sgint->cmeimask1;
		irq = lc3msk_to_irqnr[mask2];
	} else
		irq = lc1msk_to_irqnr[mask];

	/* if irq == 0, then the interrupt has already been cleared */
	if (irq)
		do_IRQ(irq);
}

extern void ip22_be_interrupt(int irq);

static void __irq_entry indy_buserror_irq(void)
{
	int irq = SGI_BUSERR_IRQ;

	irq_enter();
	kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq));
	ip22_be_interrupt(irq);
	irq_exit();
}

static struct irqaction local0_cascade = {
	.handler	= no_action,
	.flags		= IRQF_NO_THREAD,
	.name		= "local0 cascade",
};

static struct irqaction local1_cascade = {
	.handler	= no_action,
	.flags		= IRQF_NO_THREAD,
	.name		= "local1 cascade",
};

static struct irqaction buserr = {
	.handler	= no_action,
	.flags		= IRQF_NO_THREAD,
	.name		= "Bus Error",
};

static struct irqaction map0_cascade = {
	.handler	= no_action,
	.flags		= IRQF_NO_THREAD,
	.name		= "mapable0 cascade",
};

#ifdef USE_LIO3_IRQ
static struct irqaction map1_cascade = {
	.handler	= no_action,
	.flags		= IRQF_NO_THREAD,
	.name		= "mapable1 cascade",
};
#define SGI_INTERRUPTS	SGINT_END
#else
#define SGI_INTERRUPTS	SGINT_LOCAL3
#endif

extern void indy_8254timer_irq(void);

/*
 * IRQs on the INDY look basically (barring software IRQs which we don't use
 * at all) like:
 *
 *	MIPS IRQ	Source
 *      --------        ------
 *             0	Software (ignored)
 *             1        Software (ignored)
 *             2        Local IRQ level zero
 *             3        Local IRQ level one
 *             4        8254 Timer zero
 *             5        8254 Timer one
 *             6        Bus Error
 *             7        R4k timer (what we use)
 *
 * We handle the IRQ according to _our_ priority which is:
 *
 * Highest ----     R4k Timer
 *                  Local IRQ zero
 *                  Local IRQ one
 *                  Bus Error
 *                  8254 Timer zero
 * Lowest  ----     8254 Timer one
 *
 * then we just return, if multiple IRQs are pending then we will just take
 * another exception, big deal.
 */

asmlinkage void plat_irq_dispatch(void)
{
	unsigned int pending = read_c0_status() & read_c0_cause();

	/*
	 * First we check for r4k counter/timer IRQ.
	 */
	if (pending & CAUSEF_IP7)
		do_IRQ(SGI_TIMER_IRQ);
	else if (pending & CAUSEF_IP2)
		indy_local0_irqdispatch();
	else if (pending & CAUSEF_IP3)
		indy_local1_irqdispatch();
	else if (pending & CAUSEF_IP6)
		indy_buserror_irq();
	else if (pending & (CAUSEF_IP4 | CAUSEF_IP5))
		indy_8254timer_irq();
}

void __init arch_init_irq(void)
{
	int i;

	/* Init local mask --> irq tables. */
	for (i = 0; i < 256; i++) {
		if (i & 0x80) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 7;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 7;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 7;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 7;
		} else if (i & 0x40) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 6;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 6;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 6;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 6;
		} else if (i & 0x20) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 5;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 5;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 5;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 5;
		} else if (i & 0x10) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 4;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 4;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 4;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 4;
		} else if (i & 0x08) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 3;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 3;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 3;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 3;
		} else if (i & 0x04) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 2;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 2;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 2;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 2;
		} else if (i & 0x02) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 1;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 1;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 1;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 1;
		} else if (i & 0x01) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 0;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 0;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 0;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 0;
		} else {
			lc0msk_to_irqnr[i] = 0;
			lc1msk_to_irqnr[i] = 0;
			lc2msk_to_irqnr[i] = 0;
			lc3msk_to_irqnr[i] = 0;
		}
	}

	/* Mask out all interrupts. */
	sgint->imask0 = 0;
	sgint->imask1 = 0;
	sgint->cmeimask0 = 0;
	sgint->cmeimask1 = 0;

	/* init CPU irqs */
	mips_cpu_irq_init();

	for (i = SGINT_LOCAL0; i < SGI_INTERRUPTS; i++) {
		struct irq_chip *handler;

		if (i < SGINT_LOCAL1)
			handler		= &ip22_local0_irq_type;
		else if (i < SGINT_LOCAL2)
			handler		= &ip22_local1_irq_type;
		else if (i < SGINT_LOCAL3)
			handler		= &ip22_local2_irq_type;
		else
			handler		= &ip22_local3_irq_type;

		irq_set_chip_and_handler(i, handler, handle_level_irq);
	}

	/* vector handler. this register the IRQ as non-sharable */
	setup_irq(SGI_LOCAL_0_IRQ, &local0_cascade);
	setup_irq(SGI_LOCAL_1_IRQ, &local1_cascade);
	setup_irq(SGI_BUSERR_IRQ, &buserr);

	/* cascade in cascade. i love Indy ;-) */
	setup_irq(SGI_MAP_0_IRQ, &map0_cascade);
#ifdef USE_LIO3_IRQ
	setup_irq(SGI_MAP_1_IRQ, &map1_cascade);
#endif

#ifdef CONFIG_EISA
	if (ip22_is_fullhouse())	/* Only Indigo-2 has EISA stuff */
		ip22_eisa_init();
#endif
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* ip22-int.c: Routines for generic manipulation of the INT[23] ASIC
	3	* found on INDY and Indigo2 workstations.
	4	*
79add627	5	* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
1da177e4 LT	6	* Copyright (C) 1997, 1998 Ralf Baechle (ralf@gnu.org)
	7	* Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu)
	8	* - Indigo2 changes
	9	* - Interrupt handling fixes
	10	* Copyright (C) 2001, 2003 Ladislav Michl (ladis@linux-mips.org)
	11	*/
1da177e4 LT	12	#include <linux/types.h>
	13	#include <linux/init.h>
	14	#include <linux/kernel_stat.h>
1da177e4	15	#include <linux/interrupt.h>
8f99a162	16	#include <linux/ftrace.h>
1da177e4	17
97dcb82d	18	#include <asm/irq_cpu.h>
1da177e4 LT	19	#include <asm/sgi/hpc3.h>
1da177e4 LT	20	#include <asm/sgi/ip22.h>
1da177e4 LT	21
1da177e4 LT	22	/* So far nothing hangs here */
42a3b4f2	23	#undef USE_LIO3_IRQ
1da177e4 LT	24
	25	struct sgint_regs *sgint;
	26
	27	static char lc0msk_to_irqnr[256];
	28	static char lc1msk_to_irqnr[256];
	29	static char lc2msk_to_irqnr[256];
	30	static char lc3msk_to_irqnr[256];
	31
1da177e4 LT	32	extern int ip22_eisa_init(void);
1da177e4 LT	33
9458ea56	34	static void enable_local0_irq(struct irq_data *d)
1da177e4	35	{
1da177e4 LT	36	/* don't allow mappable interrupt to be enabled from setup_irq,
1da177e4 LT	37	* we have our own way to do so */
9458ea56 TG	38	if (d->irq != SGI_MAP_0_IRQ)
9458ea56 TG	39	sgint->imask0 \|= (1 << (d->irq - SGINT_LOCAL0));
1da177e4 LT	40	}
1da177e4 LT	41
9458ea56	42	static void disable_local0_irq(struct irq_data *d)
1da177e4	43	{
9458ea56	44	sgint->imask0 &= ~(1 << (d->irq - SGINT_LOCAL0));
1da177e4 LT	45	}
1da177e4 LT	46
94dee171	47	static struct irq_chip ip22_local0_irq_type = {
70d21cde	48	.name = "IP22 local 0",
9458ea56 TG	49	.irq_mask = disable_local0_irq,
9458ea56 TG	50	.irq_unmask = enable_local0_irq,
1da177e4 LT	51	};
1da177e4 LT	52
9458ea56	53	static void enable_local1_irq(struct irq_data *d)
1da177e4	54	{
1da177e4 LT	55	/* don't allow mappable interrupt to be enabled from setup_irq,
1da177e4 LT	56	* we have our own way to do so */
9458ea56 TG	57	if (d->irq != SGI_MAP_1_IRQ)
9458ea56 TG	58	sgint->imask1 \|= (1 << (d->irq - SGINT_LOCAL1));
1da177e4 LT	59	}
1da177e4 LT	60
9458ea56	61	static void disable_local1_irq(struct irq_data *d)
1da177e4	62	{
9458ea56	63	sgint->imask1 &= ~(1 << (d->irq - SGINT_LOCAL1));
1da177e4 LT	64	}
1da177e4 LT	65
94dee171	66	static struct irq_chip ip22_local1_irq_type = {
70d21cde	67	.name = "IP22 local 1",
9458ea56 TG	68	.irq_mask = disable_local1_irq,
9458ea56 TG	69	.irq_unmask = enable_local1_irq,
1da177e4 LT	70	};
1da177e4 LT	71
9458ea56	72	static void enable_local2_irq(struct irq_data *d)
1da177e4	73	{
1da177e4	74	sgint->imask0 \|= (1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
9458ea56	75	sgint->cmeimask0 \|= (1 << (d->irq - SGINT_LOCAL2));
1da177e4 LT	76	}
1da177e4 LT	77
9458ea56	78	static void disable_local2_irq(struct irq_data *d)
1da177e4	79	{
9458ea56	80	sgint->cmeimask0 &= ~(1 << (d->irq - SGINT_LOCAL2));
1da177e4 LT	81	if (!sgint->cmeimask0)
1da177e4 LT	82	sgint->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
1da177e4 LT	83	}
1da177e4 LT	84
94dee171	85	static struct irq_chip ip22_local2_irq_type = {
70d21cde	86	.name = "IP22 local 2",
9458ea56 TG	87	.irq_mask = disable_local2_irq,
9458ea56 TG	88	.irq_unmask = enable_local2_irq,
1da177e4 LT	89	};
1da177e4 LT	90
9458ea56	91	static void enable_local3_irq(struct irq_data *d)
1da177e4	92	{
1da177e4	93	sgint->imask1 \|= (1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
9458ea56	94	sgint->cmeimask1 \|= (1 << (d->irq - SGINT_LOCAL3));
1da177e4 LT	95	}
1da177e4 LT	96
9458ea56	97	static void disable_local3_irq(struct irq_data *d)
1da177e4	98	{
9458ea56	99	sgint->cmeimask1 &= ~(1 << (d->irq - SGINT_LOCAL3));
1da177e4 LT	100	if (!sgint->cmeimask1)
1da177e4 LT	101	sgint->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
1da177e4 LT	102	}
1da177e4 LT	103
94dee171	104	static struct irq_chip ip22_local3_irq_type = {
70d21cde	105	.name = "IP22 local 3",
9458ea56 TG	106	.irq_mask = disable_local3_irq,
9458ea56 TG	107	.irq_unmask = enable_local3_irq,
1da177e4 LT	108	};
1da177e4 LT	109
937a8015	110	static void indy_local0_irqdispatch(void)
1da177e4 LT	111	{
	112	u8 mask = sgint->istat0 & sgint->imask0;
	113	u8 mask2;
	114	int irq;
	115
	116	if (mask & SGINT_ISTAT0_LIO2) {
	117	mask2 = sgint->vmeistat & sgint->cmeimask0;
	118	irq = lc2msk_to_irqnr[mask2];
	119	} else
	120	irq = lc0msk_to_irqnr[mask];
	121
	122	/* if irq == 0, then the interrupt has already been cleared */
	123	if (irq)
937a8015	124	do_IRQ(irq);
1da177e4 LT	125	}
1da177e4 LT	126
937a8015	127	static void indy_local1_irqdispatch(void)
1da177e4 LT	128	{
	129	u8 mask = sgint->istat1 & sgint->imask1;
	130	u8 mask2;
	131	int irq;
	132
	133	if (mask & SGINT_ISTAT1_LIO3) {
	134	mask2 = sgint->vmeistat & sgint->cmeimask1;
	135	irq = lc3msk_to_irqnr[mask2];
	136	} else
	137	irq = lc1msk_to_irqnr[mask];
	138
	139	/* if irq == 0, then the interrupt has already been cleared */
	140	if (irq)
937a8015	141	do_IRQ(irq);
1da177e4 LT	142	}
1da177e4 LT	143
937a8015	144	extern void ip22_be_interrupt(int irq);
1da177e4	145
8f99a162	146	static void __irq_entry indy_buserror_irq(void)
1da177e4 LT	147	{
	148	int irq = SGI_BUSERR_IRQ;
	149
	150	irq_enter();
d2287f5e	151	kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq));
937a8015	152	ip22_be_interrupt(irq);
1da177e4 LT	153	irq_exit();
	154	}
	155
42a3b4f2	156	static struct irqaction local0_cascade = {
1da177e4	157	.handler = no_action,
8b5690f8	158	.flags = IRQF_NO_THREAD,
1da177e4 LT	159	.name = "local0 cascade",
	160	};
	161
42a3b4f2	162	static struct irqaction local1_cascade = {
1da177e4	163	.handler = no_action,
8b5690f8	164	.flags = IRQF_NO_THREAD,
1da177e4 LT	165	.name = "local1 cascade",
	166	};
	167
42a3b4f2	168	static struct irqaction buserr = {
1da177e4	169	.handler = no_action,
8b5690f8	170	.flags = IRQF_NO_THREAD,
1da177e4 LT	171	.name = "Bus Error",
	172	};
	173
42a3b4f2	174	static struct irqaction map0_cascade = {
1da177e4	175	.handler = no_action,
8b5690f8	176	.flags = IRQF_NO_THREAD,
1da177e4 LT	177	.name = "mapable0 cascade",
	178	};
	179
	180	#ifdef USE_LIO3_IRQ
42a3b4f2	181	static struct irqaction map1_cascade = {
1da177e4	182	.handler = no_action,
8b5690f8	183	.flags = IRQF_NO_THREAD,
1da177e4 LT	184	.name = "mapable1 cascade",
	185	};
	186	#define SGI_INTERRUPTS SGINT_END
	187	#else
	188	#define SGI_INTERRUPTS SGINT_LOCAL3
	189	#endif
	190
937a8015	191	extern void indy_8254timer_irq(void);
e4ac58af RB	192
	193	/*
	194	* IRQs on the INDY look basically (barring software IRQs which we don't use
	195	* at all) like:
	196	*
	197	* MIPS IRQ Source
	198	* -------- ------
	199	* 0 Software (ignored)
	200	* 1 Software (ignored)
	201	* 2 Local IRQ level zero
	202	* 3 Local IRQ level one
	203	* 4 8254 Timer zero
	204	* 5 8254 Timer one
	205	* 6 Bus Error
	206	* 7 R4k timer (what we use)
	207	*
	208	* We handle the IRQ according to _our_ priority which is:
	209	*
	210	* Highest ---- R4k Timer
	211	* Local IRQ zero
	212	* Local IRQ one
	213	* Bus Error
	214	* 8254 Timer zero
	215	* Lowest ---- 8254 Timer one
	216	*
	217	* then we just return, if multiple IRQs are pending then we will just take
	218	* another exception, big deal.
	219	*/
	220
937a8015	221	asmlinkage void plat_irq_dispatch(void)
e4ac58af	222	{
119537c0	223	unsigned int pending = read_c0_status() & read_c0_cause();
e4ac58af RB	224
	225	/*
	226	* First we check for r4k counter/timer IRQ.
	227	*/
	228	if (pending & CAUSEF_IP7)
7bcf7717	229	do_IRQ(SGI_TIMER_IRQ);
e4ac58af	230	else if (pending & CAUSEF_IP2)
937a8015	231	indy_local0_irqdispatch();
e4ac58af	232	else if (pending & CAUSEF_IP3)
937a8015	233	indy_local1_irqdispatch();
e4ac58af	234	else if (pending & CAUSEF_IP6)
937a8015	235	indy_buserror_irq();
e4ac58af	236	else if (pending & (CAUSEF_IP4 \| CAUSEF_IP5))
937a8015	237	indy_8254timer_irq();
e4ac58af RB	238	}
e4ac58af RB	239
1da177e4 LT	240	void __init arch_init_irq(void)
	241	{
	242	int i;
	243
	244	/* Init local mask --> irq tables. */
	245	for (i = 0; i < 256; i++) {
	246	if (i & 0x80) {
	247	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 7;
	248	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 7;
	249	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 7;
	250	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 7;
	251	} else if (i & 0x40) {
	252	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 6;
	253	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 6;
	254	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 6;
	255	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 6;
	256	} else if (i & 0x20) {
	257	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 5;
	258	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 5;
	259	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 5;
	260	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 5;
	261	} else if (i & 0x10) {
	262	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 4;
	263	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 4;
	264	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 4;
	265	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 4;
	266	} else if (i & 0x08) {
	267	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 3;
	268	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 3;
	269	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 3;
	270	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 3;
	271	} else if (i & 0x04) {
	272	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 2;
	273	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 2;
	274	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 2;
	275	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 2;
	276	} else if (i & 0x02) {
	277	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 1;
	278	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 1;
	279	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 1;
	280	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 1;
	281	} else if (i & 0x01) {
	282	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 0;
	283	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 0;
	284	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 0;
	285	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 0;
	286	} else {
	287	lc0msk_to_irqnr[i] = 0;
	288	lc1msk_to_irqnr[i] = 0;
	289	lc2msk_to_irqnr[i] = 0;
	290	lc3msk_to_irqnr[i] = 0;
	291	}
	292	}
	293
	294	/* Mask out all interrupts. */
	295	sgint->imask0 = 0;
	296	sgint->imask1 = 0;
	297	sgint->cmeimask0 = 0;
	298	sgint->cmeimask1 = 0;
	299
1da177e4	300	/* init CPU irqs */
97dcb82d	301	mips_cpu_irq_init();
1da177e4 LT	302
1da177e4 LT	303	for (i = SGINT_LOCAL0; i < SGI_INTERRUPTS; i++) {
94dee171	304	struct irq_chip *handler;
1da177e4 LT	305
	306	if (i < SGINT_LOCAL1)
	307	handler = &ip22_local0_irq_type;
	308	else if (i < SGINT_LOCAL2)
	309	handler = &ip22_local1_irq_type;
	310	else if (i < SGINT_LOCAL3)
	311	handler = &ip22_local2_irq_type;
	312	else
	313	handler = &ip22_local3_irq_type;
	314
e4ec7989	315	irq_set_chip_and_handler(i, handler, handle_level_irq);
1da177e4 LT	316	}
	317
	318	/* vector handler. this register the IRQ as non-sharable */
	319	setup_irq(SGI_LOCAL_0_IRQ, &local0_cascade);
	320	setup_irq(SGI_LOCAL_1_IRQ, &local1_cascade);
	321	setup_irq(SGI_BUSERR_IRQ, &buserr);
	322
	323	/* cascade in cascade. i love Indy ;-) */
	324	setup_irq(SGI_MAP_0_IRQ, &map0_cascade);
	325	#ifdef USE_LIO3_IRQ
	326	setup_irq(SGI_MAP_1_IRQ, &map1_cascade);
	327	#endif
	328
	329	#ifdef CONFIG_EISA
	330	if (ip22_is_fullhouse()) /* Only Indigo-2 has EISA stuff */
14823ccb	331	ip22_eisa_init();
1da177e4 LT	332	#endif
1da177e4 LT	333	}