[deliverable/linux.git] / arch / mips / sgi-ip22 / ip22-int.c

/*
 * ip22-int.c: Routines for generic manipulation of the INT[23] ASIC
 *	       found on INDY and Indigo2 workstations.
 *
 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
 * Copyright (C) 1997, 1998 Ralf Baechle (ralf@gnu.org)
 * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu)
 *		      - Indigo2 changes
 *		      - Interrupt handling fixes
 * Copyright (C) 2001, 2003 Ladislav Michl (ladis@linux-mips.org)
 */
#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/interrupt.h>
#include <linux/ftrace.h>

#include <asm/irq_cpu.h>
#include <asm/sgi/hpc3.h>
#include <asm/sgi/ip22.h>

/* So far nothing hangs here */
#undef USE_LIO3_IRQ

struct sgint_regs *sgint;

static char lc0msk_to_irqnr[256];
static char lc1msk_to_irqnr[256];
static char lc2msk_to_irqnr[256];
static char lc3msk_to_irqnr[256];

extern int ip22_eisa_init(void);

static void enable_local0_irq(struct irq_data *d)
{
	/* don't allow mappable interrupt to be enabled from setup_irq,
	 * we have our own way to do so */
	if (d->irq != SGI_MAP_0_IRQ)
		sgint->imask0 |= (1 << (d->irq - SGINT_LOCAL0));
}

static void disable_local0_irq(struct irq_data *d)
{
	sgint->imask0 &= ~(1 << (d->irq - SGINT_LOCAL0));
}

static struct irq_chip ip22_local0_irq_type = {
	.name		= "IP22 local 0",
	.irq_mask	= disable_local0_irq,
	.irq_unmask	= enable_local0_irq,
};

static void enable_local1_irq(struct irq_data *d)
{
	/* don't allow mappable interrupt to be enabled from setup_irq,
	 * we have our own way to do so */
	if (d->irq != SGI_MAP_1_IRQ)
		sgint->imask1 |= (1 << (d->irq - SGINT_LOCAL1));
}

static void disable_local1_irq(struct irq_data *d)
{
	sgint->imask1 &= ~(1 << (d->irq - SGINT_LOCAL1));
}

static struct irq_chip ip22_local1_irq_type = {
	.name		= "IP22 local 1",
	.irq_mask	= disable_local1_irq,
	.irq_unmask	= enable_local1_irq,
};

static void enable_local2_irq(struct irq_data *d)
{
	sgint->imask0 |= (1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
	sgint->cmeimask0 |= (1 << (d->irq - SGINT_LOCAL2));
}

static void disable_local2_irq(struct irq_data *d)
{
	sgint->cmeimask0 &= ~(1 << (d->irq - SGINT_LOCAL2));
	if (!sgint->cmeimask0)
		sgint->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
}

static struct irq_chip ip22_local2_irq_type = {
	.name		= "IP22 local 2",
	.irq_mask	= disable_local2_irq,
	.irq_unmask	= enable_local2_irq,
};

static void enable_local3_irq(struct irq_data *d)
{
	sgint->imask1 |= (1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
	sgint->cmeimask1 |= (1 << (d->irq - SGINT_LOCAL3));
}

static void disable_local3_irq(struct irq_data *d)
{
	sgint->cmeimask1 &= ~(1 << (d->irq - SGINT_LOCAL3));
	if (!sgint->cmeimask1)
		sgint->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
}

static struct irq_chip ip22_local3_irq_type = {
	.name		= "IP22 local 3",
	.irq_mask	= disable_local3_irq,
	.irq_unmask	= enable_local3_irq,
};

static void indy_local0_irqdispatch(void)
{
	u8 mask = sgint->istat0 & sgint->imask0;
	u8 mask2;
	int irq;

	if (mask & SGINT_ISTAT0_LIO2) {
		mask2 = sgint->vmeistat & sgint->cmeimask0;
		irq = lc2msk_to_irqnr[mask2];
	} else
		irq = lc0msk_to_irqnr[mask];

	/*
	 * workaround for INT2 bug; if irq == 0, INT2 has seen a fifo full
	 * irq, but failed to latch it into status register
	 */
	if (irq)
		do_IRQ(irq);
	else
		do_IRQ(SGINT_LOCAL0 + 0);
}

static void indy_local1_irqdispatch(void)
{
	u8 mask = sgint->istat1 & sgint->imask1;
	u8 mask2;
	int irq;

	if (mask & SGINT_ISTAT1_LIO3) {
		mask2 = sgint->vmeistat & sgint->cmeimask1;
		irq = lc3msk_to_irqnr[mask2];
	} else
		irq = lc1msk_to_irqnr[mask];

	/* if irq == 0, then the interrupt has already been cleared */
	if (irq)
		do_IRQ(irq);
}

extern void ip22_be_interrupt(int irq);

static void __irq_entry indy_buserror_irq(void)
{
	int irq = SGI_BUSERR_IRQ;

	irq_enter();
	kstat_incr_irq_this_cpu(irq);
	ip22_be_interrupt(irq);
	irq_exit();
}

static struct irqaction local0_cascade = {
	.handler	= no_action,
	.flags		= IRQF_NO_THREAD,
	.name		= "local0 cascade",
};

static struct irqaction local1_cascade = {
	.handler	= no_action,
	.flags		= IRQF_NO_THREAD,
	.name		= "local1 cascade",
};

static struct irqaction buserr = {
	.handler	= no_action,
	.flags		= IRQF_NO_THREAD,
	.name		= "Bus Error",
};

static struct irqaction map0_cascade = {
	.handler	= no_action,
	.flags		= IRQF_NO_THREAD,
	.name		= "mapable0 cascade",
};

#ifdef USE_LIO3_IRQ
static struct irqaction map1_cascade = {
	.handler	= no_action,
	.flags		= IRQF_NO_THREAD,
	.name		= "mapable1 cascade",
};
#define SGI_INTERRUPTS	SGINT_END
#else
#define SGI_INTERRUPTS	SGINT_LOCAL3
#endif

extern void indy_8254timer_irq(void);

/*
 * IRQs on the INDY look basically (barring software IRQs which we don't use
 * at all) like:
 *
 *	MIPS IRQ	Source
 *	--------	------
 *	       0	Software (ignored)
 *	       1	Software (ignored)
 *	       2	Local IRQ level zero
 *	       3	Local IRQ level one
 *	       4	8254 Timer zero
 *	       5	8254 Timer one
 *	       6	Bus Error
 *	       7	R4k timer (what we use)
 *
 * We handle the IRQ according to _our_ priority which is:
 *
 * Highest ----	    R4k Timer
 *		    Local IRQ zero
 *		    Local IRQ one
 *		    Bus Error
 *		    8254 Timer zero
 * Lowest  ----	    8254 Timer one
 *
 * then we just return, if multiple IRQs are pending then we will just take
 * another exception, big deal.
 */

asmlinkage void plat_irq_dispatch(void)
{
	unsigned int pending = read_c0_status() & read_c0_cause();

	/*
	 * First we check for r4k counter/timer IRQ.
	 */
	if (pending & CAUSEF_IP7)
		do_IRQ(SGI_TIMER_IRQ);
	else if (pending & CAUSEF_IP2)
		indy_local0_irqdispatch();
	else if (pending & CAUSEF_IP3)
		indy_local1_irqdispatch();
	else if (pending & CAUSEF_IP6)
		indy_buserror_irq();
	else if (pending & (CAUSEF_IP4 | CAUSEF_IP5))
		indy_8254timer_irq();
}

void __init arch_init_irq(void)
{
	int i;

	/* Init local mask --> irq tables. */
	for (i = 0; i < 256; i++) {
		if (i & 0x80) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 7;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 7;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 7;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 7;
		} else if (i & 0x40) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 6;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 6;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 6;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 6;
		} else if (i & 0x20) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 5;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 5;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 5;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 5;
		} else if (i & 0x10) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 4;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 4;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 4;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 4;
		} else if (i & 0x08) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 3;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 3;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 3;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 3;
		} else if (i & 0x04) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 2;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 2;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 2;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 2;
		} else if (i & 0x02) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 1;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 1;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 1;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 1;
		} else if (i & 0x01) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 0;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 0;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 0;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 0;
		} else {
			lc0msk_to_irqnr[i] = 0;
			lc1msk_to_irqnr[i] = 0;
			lc2msk_to_irqnr[i] = 0;
			lc3msk_to_irqnr[i] = 0;
		}
	}

	/* Mask out all interrupts. */
	sgint->imask0 = 0;
	sgint->imask1 = 0;
	sgint->cmeimask0 = 0;
	sgint->cmeimask1 = 0;

	/* init CPU irqs */
	mips_cpu_irq_init();

	for (i = SGINT_LOCAL0; i < SGI_INTERRUPTS; i++) {
		struct irq_chip *handler;

		if (i < SGINT_LOCAL1)
			handler		= &ip22_local0_irq_type;
		else if (i < SGINT_LOCAL2)
			handler		= &ip22_local1_irq_type;
		else if (i < SGINT_LOCAL3)
			handler		= &ip22_local2_irq_type;
		else
			handler		= &ip22_local3_irq_type;

		irq_set_chip_and_handler(i, handler, handle_level_irq);
	}

	/* vector handler. this register the IRQ as non-sharable */
	setup_irq(SGI_LOCAL_0_IRQ, &local0_cascade);
	setup_irq(SGI_LOCAL_1_IRQ, &local1_cascade);
	setup_irq(SGI_BUSERR_IRQ, &buserr);

	/* cascade in cascade. i love Indy ;-) */
	setup_irq(SGI_MAP_0_IRQ, &map0_cascade);
#ifdef USE_LIO3_IRQ
	setup_irq(SGI_MAP_1_IRQ, &map1_cascade);
#endif

#ifdef CONFIG_EISA
	if (ip22_is_fullhouse())	/* Only Indigo-2 has EISA stuff */
		ip22_eisa_init();
#endif
}
Commit	Line	Data
1da177e4 LT	1	/*
1da177e4 LT	2	* ip22-int.c: Routines for generic manipulation of the INT[23] ASIC
70342287	3	* found on INDY and Indigo2 workstations.
1da177e4	4	*
79add627	5	* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
1da177e4 LT	6	* Copyright (C) 1997, 1998 Ralf Baechle (ralf@gnu.org)
1da177e4 LT	7	* Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu)
70342287 RB	8	* - Indigo2 changes
70342287 RB	9	* - Interrupt handling fixes
1da177e4 LT	10	* Copyright (C) 2001, 2003 Ladislav Michl (ladis@linux-mips.org)
1da177e4 LT	11	*/
1da177e4 LT	12	#include <linux/types.h>
	13	#include <linux/init.h>
	14	#include <linux/kernel_stat.h>
1da177e4	15	#include <linux/interrupt.h>
8f99a162	16	#include <linux/ftrace.h>
1da177e4	17
97dcb82d	18	#include <asm/irq_cpu.h>
1da177e4 LT	19	#include <asm/sgi/hpc3.h>
1da177e4 LT	20	#include <asm/sgi/ip22.h>
1da177e4 LT	21
1da177e4 LT	22	/* So far nothing hangs here */
42a3b4f2	23	#undef USE_LIO3_IRQ
1da177e4 LT	24
	25	struct sgint_regs *sgint;
	26
	27	static char lc0msk_to_irqnr[256];
	28	static char lc1msk_to_irqnr[256];
	29	static char lc2msk_to_irqnr[256];
	30	static char lc3msk_to_irqnr[256];
	31
1da177e4 LT	32	extern int ip22_eisa_init(void);
1da177e4 LT	33
9458ea56	34	static void enable_local0_irq(struct irq_data *d)
1da177e4	35	{
1da177e4 LT	36	/* don't allow mappable interrupt to be enabled from setup_irq,
1da177e4 LT	37	* we have our own way to do so */
9458ea56 TG	38	if (d->irq != SGI_MAP_0_IRQ)
9458ea56 TG	39	sgint->imask0 \|= (1 << (d->irq - SGINT_LOCAL0));
1da177e4 LT	40	}
1da177e4 LT	41
9458ea56	42	static void disable_local0_irq(struct irq_data *d)
1da177e4	43	{
9458ea56	44	sgint->imask0 &= ~(1 << (d->irq - SGINT_LOCAL0));
1da177e4 LT	45	}
1da177e4 LT	46
94dee171	47	static struct irq_chip ip22_local0_irq_type = {
70d21cde	48	.name = "IP22 local 0",
9458ea56 TG	49	.irq_mask = disable_local0_irq,
9458ea56 TG	50	.irq_unmask = enable_local0_irq,
1da177e4 LT	51	};
1da177e4 LT	52
9458ea56	53	static void enable_local1_irq(struct irq_data *d)
1da177e4	54	{
1da177e4 LT	55	/* don't allow mappable interrupt to be enabled from setup_irq,
1da177e4 LT	56	* we have our own way to do so */
9458ea56 TG	57	if (d->irq != SGI_MAP_1_IRQ)
9458ea56 TG	58	sgint->imask1 \|= (1 << (d->irq - SGINT_LOCAL1));
1da177e4 LT	59	}
1da177e4 LT	60
9458ea56	61	static void disable_local1_irq(struct irq_data *d)
1da177e4	62	{
9458ea56	63	sgint->imask1 &= ~(1 << (d->irq - SGINT_LOCAL1));
1da177e4 LT	64	}
1da177e4 LT	65
94dee171	66	static struct irq_chip ip22_local1_irq_type = {
70d21cde	67	.name = "IP22 local 1",
9458ea56 TG	68	.irq_mask = disable_local1_irq,
9458ea56 TG	69	.irq_unmask = enable_local1_irq,
1da177e4 LT	70	};
1da177e4 LT	71
9458ea56	72	static void enable_local2_irq(struct irq_data *d)
1da177e4	73	{
1da177e4	74	sgint->imask0 \|= (1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
9458ea56	75	sgint->cmeimask0 \|= (1 << (d->irq - SGINT_LOCAL2));
1da177e4 LT	76	}
1da177e4 LT	77
9458ea56	78	static void disable_local2_irq(struct irq_data *d)
1da177e4	79	{
9458ea56	80	sgint->cmeimask0 &= ~(1 << (d->irq - SGINT_LOCAL2));
1da177e4 LT	81	if (!sgint->cmeimask0)
1da177e4 LT	82	sgint->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
1da177e4 LT	83	}
1da177e4 LT	84
94dee171	85	static struct irq_chip ip22_local2_irq_type = {
70d21cde	86	.name = "IP22 local 2",
9458ea56 TG	87	.irq_mask = disable_local2_irq,
9458ea56 TG	88	.irq_unmask = enable_local2_irq,
1da177e4 LT	89	};
1da177e4 LT	90
9458ea56	91	static void enable_local3_irq(struct irq_data *d)
1da177e4	92	{
1da177e4	93	sgint->imask1 \|= (1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
9458ea56	94	sgint->cmeimask1 \|= (1 << (d->irq - SGINT_LOCAL3));
1da177e4 LT	95	}
1da177e4 LT	96
9458ea56	97	static void disable_local3_irq(struct irq_data *d)
1da177e4	98	{
9458ea56	99	sgint->cmeimask1 &= ~(1 << (d->irq - SGINT_LOCAL3));
1da177e4 LT	100	if (!sgint->cmeimask1)
1da177e4 LT	101	sgint->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
1da177e4 LT	102	}
1da177e4 LT	103
94dee171	104	static struct irq_chip ip22_local3_irq_type = {
70d21cde	105	.name = "IP22 local 3",
9458ea56 TG	106	.irq_mask = disable_local3_irq,
9458ea56 TG	107	.irq_unmask = enable_local3_irq,
1da177e4 LT	108	};
1da177e4 LT	109
937a8015	110	static void indy_local0_irqdispatch(void)
1da177e4 LT	111	{
	112	u8 mask = sgint->istat0 & sgint->imask0;
	113	u8 mask2;
	114	int irq;
	115
	116	if (mask & SGINT_ISTAT0_LIO2) {
	117	mask2 = sgint->vmeistat & sgint->cmeimask0;
	118	irq = lc2msk_to_irqnr[mask2];
	119	} else
	120	irq = lc0msk_to_irqnr[mask];
	121
1d421ca9 TB	122	/*
	123	* workaround for INT2 bug; if irq == 0, INT2 has seen a fifo full
	124	* irq, but failed to latch it into status register
	125	*/
1da177e4	126	if (irq)
937a8015	127	do_IRQ(irq);
1d421ca9 TB	128	else
1d421ca9 TB	129	do_IRQ(SGINT_LOCAL0 + 0);
1da177e4 LT	130	}
1da177e4 LT	131
937a8015	132	static void indy_local1_irqdispatch(void)
1da177e4 LT	133	{
	134	u8 mask = sgint->istat1 & sgint->imask1;
	135	u8 mask2;
	136	int irq;
	137
	138	if (mask & SGINT_ISTAT1_LIO3) {
	139	mask2 = sgint->vmeistat & sgint->cmeimask1;
	140	irq = lc3msk_to_irqnr[mask2];
	141	} else
	142	irq = lc1msk_to_irqnr[mask];
	143
	144	/* if irq == 0, then the interrupt has already been cleared */
	145	if (irq)
937a8015	146	do_IRQ(irq);
1da177e4 LT	147	}
1da177e4 LT	148
937a8015	149	extern void ip22_be_interrupt(int irq);
1da177e4	150
8f99a162	151	static void __irq_entry indy_buserror_irq(void)
1da177e4 LT	152	{
	153	int irq = SGI_BUSERR_IRQ;
	154
	155	irq_enter();
310ff2c8	156	kstat_incr_irq_this_cpu(irq);
937a8015	157	ip22_be_interrupt(irq);
1da177e4 LT	158	irq_exit();
	159	}
	160
42a3b4f2	161	static struct irqaction local0_cascade = {
1da177e4	162	.handler = no_action,
8b5690f8	163	.flags = IRQF_NO_THREAD,
1da177e4 LT	164	.name = "local0 cascade",
	165	};
	166
42a3b4f2	167	static struct irqaction local1_cascade = {
1da177e4	168	.handler = no_action,
8b5690f8	169	.flags = IRQF_NO_THREAD,
1da177e4 LT	170	.name = "local1 cascade",
	171	};
	172
42a3b4f2	173	static struct irqaction buserr = {
1da177e4	174	.handler = no_action,
8b5690f8	175	.flags = IRQF_NO_THREAD,
1da177e4 LT	176	.name = "Bus Error",
	177	};
	178
42a3b4f2	179	static struct irqaction map0_cascade = {
1da177e4	180	.handler = no_action,
8b5690f8	181	.flags = IRQF_NO_THREAD,
1da177e4 LT	182	.name = "mapable0 cascade",
	183	};
	184
	185	#ifdef USE_LIO3_IRQ
42a3b4f2	186	static struct irqaction map1_cascade = {
1da177e4	187	.handler = no_action,
8b5690f8	188	.flags = IRQF_NO_THREAD,
1da177e4 LT	189	.name = "mapable1 cascade",
	190	};
	191	#define SGI_INTERRUPTS SGINT_END
	192	#else
	193	#define SGI_INTERRUPTS SGINT_LOCAL3
	194	#endif
	195
937a8015	196	extern void indy_8254timer_irq(void);
e4ac58af RB	197
	198	/*
	199	* IRQs on the INDY look basically (barring software IRQs which we don't use
	200	* at all) like:
	201	*
	202	* MIPS IRQ Source
70342287 RB	203	* -------- ------
	204	* 0 Software (ignored)
	205	* 1 Software (ignored)
	206	* 2 Local IRQ level zero
	207	* 3 Local IRQ level one
	208	* 4 8254 Timer zero
	209	* 5 8254 Timer one
	210	* 6 Bus Error
	211	* 7 R4k timer (what we use)
e4ac58af RB	212	*
	213	* We handle the IRQ according to _our_ priority which is:
	214	*
70342287 RB	215	* Highest ---- R4k Timer
	216	* Local IRQ zero
	217	* Local IRQ one
	218	* Bus Error
	219	* 8254 Timer zero
	220	* Lowest ---- 8254 Timer one
e4ac58af RB	221	*
	222	* then we just return, if multiple IRQs are pending then we will just take
	223	* another exception, big deal.
	224	*/
	225
937a8015	226	asmlinkage void plat_irq_dispatch(void)
e4ac58af	227	{
119537c0	228	unsigned int pending = read_c0_status() & read_c0_cause();
e4ac58af RB	229
	230	/*
	231	* First we check for r4k counter/timer IRQ.
	232	*/
	233	if (pending & CAUSEF_IP7)
7bcf7717	234	do_IRQ(SGI_TIMER_IRQ);
e4ac58af	235	else if (pending & CAUSEF_IP2)
937a8015	236	indy_local0_irqdispatch();
e4ac58af	237	else if (pending & CAUSEF_IP3)
937a8015	238	indy_local1_irqdispatch();
e4ac58af	239	else if (pending & CAUSEF_IP6)
937a8015	240	indy_buserror_irq();
e4ac58af	241	else if (pending & (CAUSEF_IP4 \| CAUSEF_IP5))
937a8015	242	indy_8254timer_irq();
e4ac58af RB	243	}
e4ac58af RB	244
1da177e4 LT	245	void __init arch_init_irq(void)
	246	{
	247	int i;
	248
	249	/* Init local mask --> irq tables. */
	250	for (i = 0; i < 256; i++) {
	251	if (i & 0x80) {
	252	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 7;
	253	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 7;
	254	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 7;
	255	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 7;
	256	} else if (i & 0x40) {
	257	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 6;
	258	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 6;
	259	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 6;
	260	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 6;
	261	} else if (i & 0x20) {
	262	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 5;
	263	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 5;
	264	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 5;
	265	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 5;
	266	} else if (i & 0x10) {
	267	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 4;
	268	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 4;
	269	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 4;
	270	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 4;
	271	} else if (i & 0x08) {
	272	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 3;
	273	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 3;
	274	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 3;
	275	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 3;
	276	} else if (i & 0x04) {
	277	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 2;
	278	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 2;
	279	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 2;
	280	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 2;
	281	} else if (i & 0x02) {
	282	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 1;
	283	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 1;
	284	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 1;
	285	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 1;
	286	} else if (i & 0x01) {
	287	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 0;
	288	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 0;
	289	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 0;
	290	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 0;
	291	} else {
	292	lc0msk_to_irqnr[i] = 0;
	293	lc1msk_to_irqnr[i] = 0;
	294	lc2msk_to_irqnr[i] = 0;
	295	lc3msk_to_irqnr[i] = 0;
	296	}
	297	}
	298
	299	/* Mask out all interrupts. */
	300	sgint->imask0 = 0;
	301	sgint->imask1 = 0;
	302	sgint->cmeimask0 = 0;
	303	sgint->cmeimask1 = 0;
	304
1da177e4	305	/* init CPU irqs */
97dcb82d	306	mips_cpu_irq_init();
1da177e4 LT	307
1da177e4 LT	308	for (i = SGINT_LOCAL0; i < SGI_INTERRUPTS; i++) {
94dee171	309	struct irq_chip *handler;
1da177e4 LT	310
	311	if (i < SGINT_LOCAL1)
	312	handler = &ip22_local0_irq_type;
	313	else if (i < SGINT_LOCAL2)
	314	handler = &ip22_local1_irq_type;
	315	else if (i < SGINT_LOCAL3)
	316	handler = &ip22_local2_irq_type;
	317	else
	318	handler = &ip22_local3_irq_type;
	319
e4ec7989	320	irq_set_chip_and_handler(i, handler, handle_level_irq);
1da177e4 LT	321	}
	322
	323	/* vector handler. this register the IRQ as non-sharable */
	324	setup_irq(SGI_LOCAL_0_IRQ, &local0_cascade);
	325	setup_irq(SGI_LOCAL_1_IRQ, &local1_cascade);
	326	setup_irq(SGI_BUSERR_IRQ, &buserr);
	327
	328	/* cascade in cascade. i love Indy ;-) */
	329	setup_irq(SGI_MAP_0_IRQ, &map0_cascade);
	330	#ifdef USE_LIO3_IRQ
	331	setup_irq(SGI_MAP_1_IRQ, &map1_cascade);
	332	#endif
	333
	334	#ifdef CONFIG_EISA
	335	if (ip22_is_fullhouse()) /* Only Indigo-2 has EISA stuff */
14823ccb	336	ip22_eisa_init();
1da177e4 LT	337	#endif
1da177e4 LT	338	}