[deliverable/linux.git] / arch / mips / sgi-ip22 / ip22-int.c

/*
 * ip22-int.c: Routines for generic manipulation of the INT[23] ASIC
 *             found on INDY and Indigo2 workstations.
 *
 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
 * Copyright (C) 1997, 1998 Ralf Baechle (ralf@gnu.org)
 * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu)
 *                    - Indigo2 changes
 *                    - Interrupt handling fixes
 * Copyright (C) 2001, 2003 Ladislav Michl (ladis@linux-mips.org)
 */
#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/irq.h>

#include <asm/mipsregs.h>
#include <asm/addrspace.h>

#include <asm/sgi/ioc.h>
#include <asm/sgi/hpc3.h>
#include <asm/sgi/ip22.h>

/* #define DEBUG_SGINT */

/* So far nothing hangs here */
#undef USE_LIO3_IRQ

struct sgint_regs *sgint;

static char lc0msk_to_irqnr[256];
static char lc1msk_to_irqnr[256];
static char lc2msk_to_irqnr[256];
static char lc3msk_to_irqnr[256];

extern int ip22_eisa_init(void);

static void enable_local0_irq(unsigned int irq)
{
	/* don't allow mappable interrupt to be enabled from setup_irq,
	 * we have our own way to do so */
	if (irq != SGI_MAP_0_IRQ)
		sgint->imask0 |= (1 << (irq - SGINT_LOCAL0));
}

static void disable_local0_irq(unsigned int irq)
{
	sgint->imask0 &= ~(1 << (irq - SGINT_LOCAL0));
}

static void end_local0_irq (unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
		enable_local0_irq(irq);
}

static struct irq_chip ip22_local0_irq_type = {
	.typename	= "IP22 local 0",
	.ack		= disable_local0_irq,
	.mask		= disable_local0_irq,
	.mask_ack	= disable_local0_irq,
	.unmask		= enable_local0_irq,
	.end		= end_local0_irq,
};

static void enable_local1_irq(unsigned int irq)
{
	/* don't allow mappable interrupt to be enabled from setup_irq,
	 * we have our own way to do so */
	if (irq != SGI_MAP_1_IRQ)
		sgint->imask1 |= (1 << (irq - SGINT_LOCAL1));
}

void disable_local1_irq(unsigned int irq)
{
	sgint->imask1 &= ~(1 << (irq - SGINT_LOCAL1));
}

static void end_local1_irq (unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
		enable_local1_irq(irq);
}

static struct irq_chip ip22_local1_irq_type = {
	.typename	= "IP22 local 1",
	.ack		= disable_local1_irq,
	.mask		= disable_local1_irq,
	.mask_ack	= disable_local1_irq,
	.unmask		= enable_local1_irq,
	.end		= end_local1_irq,
};

static void enable_local2_irq(unsigned int irq)
{
	sgint->imask0 |= (1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
	sgint->cmeimask0 |= (1 << (irq - SGINT_LOCAL2));
}

void disable_local2_irq(unsigned int irq)
{
	sgint->cmeimask0 &= ~(1 << (irq - SGINT_LOCAL2));
	if (!sgint->cmeimask0)
		sgint->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
}

static void end_local2_irq (unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
		enable_local2_irq(irq);
}

static struct irq_chip ip22_local2_irq_type = {
	.typename	= "IP22 local 2",
	.ack		= disable_local2_irq,
	.mask		= disable_local2_irq,
	.mask_ack	= disable_local2_irq,
	.unmask		= enable_local2_irq,
	.end		= end_local2_irq,
};

static void enable_local3_irq(unsigned int irq)
{
	sgint->imask1 |= (1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
	sgint->cmeimask1 |= (1 << (irq - SGINT_LOCAL3));
}

void disable_local3_irq(unsigned int irq)
{
	sgint->cmeimask1 &= ~(1 << (irq - SGINT_LOCAL3));
	if (!sgint->cmeimask1)
		sgint->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
}

static void end_local3_irq (unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
		enable_local3_irq(irq);
}

static struct irq_chip ip22_local3_irq_type = {
	.typename	= "IP22 local 3",
	.ack		= disable_local3_irq,
	.mask		= disable_local3_irq,
	.mask_ack	= disable_local3_irq,
	.unmask		= enable_local3_irq,
	.end		= end_local3_irq,
};

static void indy_local0_irqdispatch(void)
{
	u8 mask = sgint->istat0 & sgint->imask0;
	u8 mask2;
	int irq;

	if (mask & SGINT_ISTAT0_LIO2) {
		mask2 = sgint->vmeistat & sgint->cmeimask0;
		irq = lc2msk_to_irqnr[mask2];
	} else
		irq = lc0msk_to_irqnr[mask];

	/* if irq == 0, then the interrupt has already been cleared */
	if (irq)
		do_IRQ(irq);
}

static void indy_local1_irqdispatch(void)
{
	u8 mask = sgint->istat1 & sgint->imask1;
	u8 mask2;
	int irq;

	if (mask & SGINT_ISTAT1_LIO3) {
		mask2 = sgint->vmeistat & sgint->cmeimask1;
		irq = lc3msk_to_irqnr[mask2];
	} else
		irq = lc1msk_to_irqnr[mask];

	/* if irq == 0, then the interrupt has already been cleared */
	if (irq)
		do_IRQ(irq);
}

extern void ip22_be_interrupt(int irq);

static void indy_buserror_irq(void)
{
	int irq = SGI_BUSERR_IRQ;

	irq_enter();
	kstat_this_cpu.irqs[irq]++;
	ip22_be_interrupt(irq);
	irq_exit();
}

static struct irqaction local0_cascade = {
	.handler	= no_action,
	.flags		= IRQF_DISABLED,
	.name		= "local0 cascade",
};

static struct irqaction local1_cascade = {
	.handler	= no_action,
	.flags		= IRQF_DISABLED,
	.name		= "local1 cascade",
};

static struct irqaction buserr = {
	.handler	= no_action,
	.flags		= IRQF_DISABLED,
	.name		= "Bus Error",
};

static struct irqaction map0_cascade = {
	.handler	= no_action,
	.flags		= IRQF_DISABLED,
	.name		= "mapable0 cascade",
};

#ifdef USE_LIO3_IRQ
static struct irqaction map1_cascade = {
	.handler	= no_action,
	.flags		= IRQF_DISABLED,
	.name		= "mapable1 cascade",
};
#define SGI_INTERRUPTS	SGINT_END
#else
#define SGI_INTERRUPTS	SGINT_LOCAL3
#endif

extern void indy_r4k_timer_interrupt(void);
extern void indy_8254timer_irq(void);

/*
 * IRQs on the INDY look basically (barring software IRQs which we don't use
 * at all) like:
 *
 *	MIPS IRQ	Source
 *      --------        ------
 *             0	Software (ignored)
 *             1        Software (ignored)
 *             2        Local IRQ level zero
 *             3        Local IRQ level one
 *             4        8254 Timer zero
 *             5        8254 Timer one
 *             6        Bus Error
 *             7        R4k timer (what we use)
 *
 * We handle the IRQ according to _our_ priority which is:
 *
 * Highest ----     R4k Timer
 *                  Local IRQ zero
 *                  Local IRQ one
 *                  Bus Error
 *                  8254 Timer zero
 * Lowest  ----     8254 Timer one
 *
 * then we just return, if multiple IRQs are pending then we will just take
 * another exception, big deal.
 */

asmlinkage void plat_irq_dispatch(void)
{
	unsigned int pending = read_c0_cause();

	/*
	 * First we check for r4k counter/timer IRQ.
	 */
	if (pending & CAUSEF_IP7)
		indy_r4k_timer_interrupt();
	else if (pending & CAUSEF_IP2)
		indy_local0_irqdispatch();
	else if (pending & CAUSEF_IP3)
		indy_local1_irqdispatch();
	else if (pending & CAUSEF_IP6)
		indy_buserror_irq();
	else if (pending & (CAUSEF_IP4 | CAUSEF_IP5))
		indy_8254timer_irq();
}

extern void mips_cpu_irq_init(unsigned int irq_base);

void __init arch_init_irq(void)
{
	int i;

	/* Init local mask --> irq tables. */
	for (i = 0; i < 256; i++) {
		if (i & 0x80) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 7;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 7;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 7;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 7;
		} else if (i & 0x40) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 6;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 6;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 6;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 6;
		} else if (i & 0x20) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 5;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 5;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 5;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 5;
		} else if (i & 0x10) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 4;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 4;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 4;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 4;
		} else if (i & 0x08) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 3;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 3;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 3;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 3;
		} else if (i & 0x04) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 2;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 2;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 2;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 2;
		} else if (i & 0x02) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 1;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 1;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 1;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 1;
		} else if (i & 0x01) {
			lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 0;
			lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 0;
			lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 0;
			lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 0;
		} else {
			lc0msk_to_irqnr[i] = 0;
			lc1msk_to_irqnr[i] = 0;
			lc2msk_to_irqnr[i] = 0;
			lc3msk_to_irqnr[i] = 0;
		}
	}

	/* Mask out all interrupts. */
	sgint->imask0 = 0;
	sgint->imask1 = 0;
	sgint->cmeimask0 = 0;
	sgint->cmeimask1 = 0;

	/* init CPU irqs */
	mips_cpu_irq_init(SGINT_CPU);

	for (i = SGINT_LOCAL0; i < SGI_INTERRUPTS; i++) {
		struct irq_chip *handler;

		if (i < SGINT_LOCAL1)
			handler		= &ip22_local0_irq_type;
		else if (i < SGINT_LOCAL2)
			handler		= &ip22_local1_irq_type;
		else if (i < SGINT_LOCAL3)
			handler		= &ip22_local2_irq_type;
		else
			handler		= &ip22_local3_irq_type;

		set_irq_chip_and_handler(i, handler, handle_level_irq);
	}

	/* vector handler. this register the IRQ as non-sharable */
	setup_irq(SGI_LOCAL_0_IRQ, &local0_cascade);
	setup_irq(SGI_LOCAL_1_IRQ, &local1_cascade);
	setup_irq(SGI_BUSERR_IRQ, &buserr);

	/* cascade in cascade. i love Indy ;-) */
	setup_irq(SGI_MAP_0_IRQ, &map0_cascade);
#ifdef USE_LIO3_IRQ
	setup_irq(SGI_MAP_1_IRQ, &map1_cascade);
#endif

#ifdef CONFIG_EISA
	if (ip22_is_fullhouse())	/* Only Indigo-2 has EISA stuff */
	        ip22_eisa_init ();
#endif
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* ip22-int.c: Routines for generic manipulation of the INT[23] ASIC
	3	* found on INDY and Indigo2 workstations.
	4	*
	5	* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
	6	* Copyright (C) 1997, 1998 Ralf Baechle (ralf@gnu.org)
	7	* Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu)
	8	* - Indigo2 changes
	9	* - Interrupt handling fixes
	10	* Copyright (C) 2001, 2003 Ladislav Michl (ladis@linux-mips.org)
	11	*/
1da177e4 LT	12	#include <linux/types.h>
	13	#include <linux/init.h>
	14	#include <linux/kernel_stat.h>
	15	#include <linux/signal.h>
	16	#include <linux/sched.h>
	17	#include <linux/interrupt.h>
	18	#include <linux/irq.h>
	19
	20	#include <asm/mipsregs.h>
	21	#include <asm/addrspace.h>
	22
	23	#include <asm/sgi/ioc.h>
	24	#include <asm/sgi/hpc3.h>
	25	#include <asm/sgi/ip22.h>
	26
	27	/* #define DEBUG_SGINT */
	28
	29	/* So far nothing hangs here */
42a3b4f2	30	#undef USE_LIO3_IRQ
1da177e4 LT	31
	32	struct sgint_regs *sgint;
	33
	34	static char lc0msk_to_irqnr[256];
	35	static char lc1msk_to_irqnr[256];
	36	static char lc2msk_to_irqnr[256];
	37	static char lc3msk_to_irqnr[256];
	38
1da177e4 LT	39	extern int ip22_eisa_init(void);
	40
	41	static void enable_local0_irq(unsigned int irq)
	42	{
1da177e4 LT	43	/* don't allow mappable interrupt to be enabled from setup_irq,
	44	* we have our own way to do so */
	45	if (irq != SGI_MAP_0_IRQ)
	46	sgint->imask0 \|= (1 << (irq - SGINT_LOCAL0));
1da177e4 LT	47	}
	48
	49	static void disable_local0_irq(unsigned int irq)
	50	{
1da177e4	51	sgint->imask0 &= ~(1 << (irq - SGINT_LOCAL0));
1da177e4 LT	52	}
1da177e4 LT	53
1da177e4 LT	54	static void end_local0_irq (unsigned int irq)
	55	{
	56	if (!(irq_desc[irq].status & (IRQ_DISABLED\|IRQ_INPROGRESS)))
	57	enable_local0_irq(irq);
	58	}
	59
94dee171	60	static struct irq_chip ip22_local0_irq_type = {
1da177e4	61	.typename = "IP22 local 0",
1603b5ac AN	62	.ack = disable_local0_irq,
	63	.mask = disable_local0_irq,
	64	.mask_ack = disable_local0_irq,
	65	.unmask = enable_local0_irq,
1da177e4 LT	66	.end = end_local0_irq,
	67	};
	68
	69	static void enable_local1_irq(unsigned int irq)
	70	{
1da177e4 LT	71	/* don't allow mappable interrupt to be enabled from setup_irq,
	72	* we have our own way to do so */
	73	if (irq != SGI_MAP_1_IRQ)
	74	sgint->imask1 \|= (1 << (irq - SGINT_LOCAL1));
1da177e4 LT	75	}
	76
	77	void disable_local1_irq(unsigned int irq)
	78	{
1da177e4	79	sgint->imask1 &= ~(1 << (irq - SGINT_LOCAL1));
1da177e4 LT	80	}
1da177e4 LT	81
1da177e4 LT	82	static void end_local1_irq (unsigned int irq)
	83	{
	84	if (!(irq_desc[irq].status & (IRQ_DISABLED\|IRQ_INPROGRESS)))
	85	enable_local1_irq(irq);
	86	}
	87
94dee171	88	static struct irq_chip ip22_local1_irq_type = {
1da177e4	89	.typename = "IP22 local 1",
1603b5ac AN	90	.ack = disable_local1_irq,
	91	.mask = disable_local1_irq,
	92	.mask_ack = disable_local1_irq,
	93	.unmask = enable_local1_irq,
1da177e4 LT	94	.end = end_local1_irq,
	95	};
	96
	97	static void enable_local2_irq(unsigned int irq)
	98	{
1da177e4 LT	99	sgint->imask0 \|= (1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
1da177e4 LT	100	sgint->cmeimask0 \|= (1 << (irq - SGINT_LOCAL2));
1da177e4 LT	101	}
	102
	103	void disable_local2_irq(unsigned int irq)
	104	{
1da177e4 LT	105	sgint->cmeimask0 &= ~(1 << (irq - SGINT_LOCAL2));
	106	if (!sgint->cmeimask0)
	107	sgint->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
1da177e4 LT	108	}
1da177e4 LT	109
1da177e4 LT	110	static void end_local2_irq (unsigned int irq)
	111	{
	112	if (!(irq_desc[irq].status & (IRQ_DISABLED\|IRQ_INPROGRESS)))
	113	enable_local2_irq(irq);
	114	}
	115
94dee171	116	static struct irq_chip ip22_local2_irq_type = {
1da177e4	117	.typename = "IP22 local 2",
1603b5ac AN	118	.ack = disable_local2_irq,
	119	.mask = disable_local2_irq,
	120	.mask_ack = disable_local2_irq,
	121	.unmask = enable_local2_irq,
1da177e4 LT	122	.end = end_local2_irq,
	123	};
	124
	125	static void enable_local3_irq(unsigned int irq)
	126	{
1da177e4 LT	127	sgint->imask1 \|= (1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
1da177e4 LT	128	sgint->cmeimask1 \|= (1 << (irq - SGINT_LOCAL3));
1da177e4 LT	129	}
	130
	131	void disable_local3_irq(unsigned int irq)
	132	{
1da177e4 LT	133	sgint->cmeimask1 &= ~(1 << (irq - SGINT_LOCAL3));
	134	if (!sgint->cmeimask1)
	135	sgint->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
1da177e4 LT	136	}
1da177e4 LT	137
1da177e4 LT	138	static void end_local3_irq (unsigned int irq)
	139	{
	140	if (!(irq_desc[irq].status & (IRQ_DISABLED\|IRQ_INPROGRESS)))
	141	enable_local3_irq(irq);
	142	}
	143
94dee171	144	static struct irq_chip ip22_local3_irq_type = {
1da177e4	145	.typename = "IP22 local 3",
1603b5ac AN	146	.ack = disable_local3_irq,
	147	.mask = disable_local3_irq,
	148	.mask_ack = disable_local3_irq,
	149	.unmask = enable_local3_irq,
1da177e4 LT	150	.end = end_local3_irq,
	151	};
	152
937a8015	153	static void indy_local0_irqdispatch(void)
1da177e4 LT	154	{
	155	u8 mask = sgint->istat0 & sgint->imask0;
	156	u8 mask2;
	157	int irq;
	158
	159	if (mask & SGINT_ISTAT0_LIO2) {
	160	mask2 = sgint->vmeistat & sgint->cmeimask0;
	161	irq = lc2msk_to_irqnr[mask2];
	162	} else
	163	irq = lc0msk_to_irqnr[mask];
	164
	165	/* if irq == 0, then the interrupt has already been cleared */
	166	if (irq)
937a8015	167	do_IRQ(irq);
1da177e4 LT	168	}
1da177e4 LT	169
937a8015	170	static void indy_local1_irqdispatch(void)
1da177e4 LT	171	{
	172	u8 mask = sgint->istat1 & sgint->imask1;
	173	u8 mask2;
	174	int irq;
	175
	176	if (mask & SGINT_ISTAT1_LIO3) {
	177	mask2 = sgint->vmeistat & sgint->cmeimask1;
	178	irq = lc3msk_to_irqnr[mask2];
	179	} else
	180	irq = lc1msk_to_irqnr[mask];
	181
	182	/* if irq == 0, then the interrupt has already been cleared */
	183	if (irq)
937a8015	184	do_IRQ(irq);
1da177e4 LT	185	}
1da177e4 LT	186
937a8015	187	extern void ip22_be_interrupt(int irq);
1da177e4	188
937a8015	189	static void indy_buserror_irq(void)
1da177e4 LT	190	{
	191	int irq = SGI_BUSERR_IRQ;
	192
	193	irq_enter();
	194	kstat_this_cpu.irqs[irq]++;
937a8015	195	ip22_be_interrupt(irq);
1da177e4 LT	196	irq_exit();
	197	}
	198
42a3b4f2	199	static struct irqaction local0_cascade = {
1da177e4	200	.handler = no_action,
f40298fd	201	.flags = IRQF_DISABLED,
1da177e4 LT	202	.name = "local0 cascade",
	203	};
	204
42a3b4f2	205	static struct irqaction local1_cascade = {
1da177e4	206	.handler = no_action,
f40298fd	207	.flags = IRQF_DISABLED,
1da177e4 LT	208	.name = "local1 cascade",
	209	};
	210
42a3b4f2	211	static struct irqaction buserr = {
1da177e4	212	.handler = no_action,
f40298fd	213	.flags = IRQF_DISABLED,
1da177e4 LT	214	.name = "Bus Error",
	215	};
	216
42a3b4f2	217	static struct irqaction map0_cascade = {
1da177e4	218	.handler = no_action,
f40298fd	219	.flags = IRQF_DISABLED,
1da177e4 LT	220	.name = "mapable0 cascade",
	221	};
	222
	223	#ifdef USE_LIO3_IRQ
42a3b4f2	224	static struct irqaction map1_cascade = {
1da177e4	225	.handler = no_action,
f40298fd	226	.flags = IRQF_DISABLED,
1da177e4 LT	227	.name = "mapable1 cascade",
	228	};
	229	#define SGI_INTERRUPTS SGINT_END
	230	#else
	231	#define SGI_INTERRUPTS SGINT_LOCAL3
	232	#endif
	233
937a8015 RB	234	extern void indy_r4k_timer_interrupt(void);
937a8015 RB	235	extern void indy_8254timer_irq(void);
e4ac58af RB	236
	237	/*
	238	* IRQs on the INDY look basically (barring software IRQs which we don't use
	239	* at all) like:
	240	*
	241	* MIPS IRQ Source
	242	* -------- ------
	243	* 0 Software (ignored)
	244	* 1 Software (ignored)
	245	* 2 Local IRQ level zero
	246	* 3 Local IRQ level one
	247	* 4 8254 Timer zero
	248	* 5 8254 Timer one
	249	* 6 Bus Error
	250	* 7 R4k timer (what we use)
	251	*
	252	* We handle the IRQ according to _our_ priority which is:
	253	*
	254	* Highest ---- R4k Timer
	255	* Local IRQ zero
	256	* Local IRQ one
	257	* Bus Error
	258	* 8254 Timer zero
	259	* Lowest ---- 8254 Timer one
	260	*
	261	* then we just return, if multiple IRQs are pending then we will just take
	262	* another exception, big deal.
	263	*/
	264
937a8015	265	asmlinkage void plat_irq_dispatch(void)
e4ac58af RB	266	{
	267	unsigned int pending = read_c0_cause();
	268
	269	/*
	270	* First we check for r4k counter/timer IRQ.
	271	*/
	272	if (pending & CAUSEF_IP7)
937a8015	273	indy_r4k_timer_interrupt();
e4ac58af	274	else if (pending & CAUSEF_IP2)
937a8015	275	indy_local0_irqdispatch();
e4ac58af	276	else if (pending & CAUSEF_IP3)
937a8015	277	indy_local1_irqdispatch();
e4ac58af	278	else if (pending & CAUSEF_IP6)
937a8015	279	indy_buserror_irq();
e4ac58af	280	else if (pending & (CAUSEF_IP4 \| CAUSEF_IP5))
937a8015	281	indy_8254timer_irq();
e4ac58af RB	282	}
e4ac58af RB	283
1da177e4 LT	284	extern void mips_cpu_irq_init(unsigned int irq_base);
	285
	286	void __init arch_init_irq(void)
	287	{
	288	int i;
	289
	290	/* Init local mask --> irq tables. */
	291	for (i = 0; i < 256; i++) {
	292	if (i & 0x80) {
	293	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 7;
	294	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 7;
	295	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 7;
	296	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 7;
	297	} else if (i & 0x40) {
	298	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 6;
	299	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 6;
	300	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 6;
	301	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 6;
	302	} else if (i & 0x20) {
	303	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 5;
	304	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 5;
	305	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 5;
	306	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 5;
	307	} else if (i & 0x10) {
	308	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 4;
	309	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 4;
	310	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 4;
	311	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 4;
	312	} else if (i & 0x08) {
	313	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 3;
	314	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 3;
	315	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 3;
	316	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 3;
	317	} else if (i & 0x04) {
	318	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 2;
	319	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 2;
	320	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 2;
	321	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 2;
	322	} else if (i & 0x02) {
	323	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 1;
	324	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 1;
	325	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 1;
	326	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 1;
	327	} else if (i & 0x01) {
	328	lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 0;
	329	lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 0;
	330	lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 0;
	331	lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 0;
	332	} else {
	333	lc0msk_to_irqnr[i] = 0;
	334	lc1msk_to_irqnr[i] = 0;
	335	lc2msk_to_irqnr[i] = 0;
	336	lc3msk_to_irqnr[i] = 0;
	337	}
	338	}
	339
	340	/* Mask out all interrupts. */
	341	sgint->imask0 = 0;
	342	sgint->imask1 = 0;
	343	sgint->cmeimask0 = 0;
	344	sgint->cmeimask1 = 0;
	345
1da177e4 LT	346	/* init CPU irqs */
	347	mips_cpu_irq_init(SGINT_CPU);
	348
	349	for (i = SGINT_LOCAL0; i < SGI_INTERRUPTS; i++) {
94dee171	350	struct irq_chip *handler;
1da177e4 LT	351
	352	if (i < SGINT_LOCAL1)
	353	handler = &ip22_local0_irq_type;
	354	else if (i < SGINT_LOCAL2)
	355	handler = &ip22_local1_irq_type;
	356	else if (i < SGINT_LOCAL3)
	357	handler = &ip22_local2_irq_type;
	358	else
	359	handler = &ip22_local3_irq_type;
	360
1417836e	361	set_irq_chip_and_handler(i, handler, handle_level_irq);
1da177e4 LT	362	}
	363
	364	/* vector handler. this register the IRQ as non-sharable */
	365	setup_irq(SGI_LOCAL_0_IRQ, &local0_cascade);
	366	setup_irq(SGI_LOCAL_1_IRQ, &local1_cascade);
	367	setup_irq(SGI_BUSERR_IRQ, &buserr);
	368
	369	/* cascade in cascade. i love Indy ;-) */
	370	setup_irq(SGI_MAP_0_IRQ, &map0_cascade);
	371	#ifdef USE_LIO3_IRQ
	372	setup_irq(SGI_MAP_1_IRQ, &map1_cascade);
	373	#endif
	374
	375	#ifdef CONFIG_EISA
	376	if (ip22_is_fullhouse()) /* Only Indigo-2 has EISA stuff */
	377	ip22_eisa_init ();
	378	#endif
	379	}