[deliverable/linux.git] / arch / mips / sgi-ip32 / ip32-irq.c

/*
 * Code to handle IP32 IRQs
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2000 Harald Koerfgen
 * Copyright (C) 2001 Keith M Wesolowski
 */
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/bitops.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/mm.h>
#include <linux/random.h>
#include <linux/sched.h>

#include <asm/mipsregs.h>
#include <asm/signal.h>
#include <asm/system.h>
#include <asm/time.h>
#include <asm/ip32/crime.h>
#include <asm/ip32/mace.h>
#include <asm/ip32/ip32_ints.h>

/* issue a PIO read to make sure no PIO writes are pending */
static void inline flush_crime_bus(void)
{
	crime->control;
}

static void inline flush_mace_bus(void)
{
	mace->perif.ctrl.misc;
}

#undef DEBUG_IRQ
#ifdef DEBUG_IRQ
#define DBG(x...) printk(x)
#else
#define DBG(x...)
#endif

/* O2 irq map
 *
 * IP0 -> software (ignored)
 * IP1 -> software (ignored)
 * IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ???
 * IP3 -> (irq1) X unknown
 * IP4 -> (irq2) X unknown
 * IP5 -> (irq3) X unknown
 * IP6 -> (irq4) X unknown
 * IP7 -> (irq5) 0 CPU count/compare timer (system timer)
 *
 * crime: (C)
 *
 * CRIME_INT_STAT 31:0:
 *
 * 0  -> 1  Video in 1
 * 1  -> 2  Video in 2
 * 2  -> 3  Video out
 * 3  -> 4  Mace ethernet
 * 4  -> S  SuperIO sub-interrupt
 * 5  -> M  Miscellaneous sub-interrupt
 * 6  -> A  Audio sub-interrupt
 * 7  -> 8  PCI bridge errors
 * 8  -> 9  PCI SCSI aic7xxx 0
 * 9  -> 10 PCI SCSI aic7xxx 1
 * 10 -> 11 PCI slot 0
 * 11 -> 12 unused (PCI slot 1)
 * 12 -> 13 unused (PCI slot 2)
 * 13 -> 14 unused (PCI shared 0)
 * 14 -> 15 unused (PCI shared 1)
 * 15 -> 16 unused (PCI shared 2)
 * 16 -> 17 GBE0 (E)
 * 17 -> 18 GBE1 (E)
 * 18 -> 19 GBE2 (E)
 * 19 -> 20 GBE3 (E)
 * 20 -> 21 CPU errors
 * 21 -> 22 Memory errors
 * 22 -> 23 RE empty edge (E)
 * 23 -> 24 RE full edge (E)
 * 24 -> 25 RE idle edge (E)
 * 25 -> 26 RE empty level
 * 26 -> 27 RE full level
 * 27 -> 28 RE idle level
 * 28 -> 29 unused (software 0) (E)
 * 29 -> 30 unused (software 1) (E)
 * 30 -> 31 unused (software 2) - crime 1.5 CPU SysCorError (E)
 * 31 -> 32 VICE
 *
 * S, M, A: Use the MACE ISA interrupt register
 * MACE_ISA_INT_STAT 31:0
 *
 * 0-7 -> 33-40 Audio
 * 8 -> 41 RTC
 * 9 -> 42 Keyboard
 * 10 -> X Keyboard polled
 * 11 -> 44 Mouse
 * 12 -> X Mouse polled
 * 13-15 -> 46-48 Count/compare timers
 * 16-19 -> 49-52 Parallel (16 E)
 * 20-25 -> 53-58 Serial 1 (22 E)
 * 26-31 -> 59-64 Serial 2 (28 E)
 *
 * Note that this means IRQs 5-7, 43, and 45 do not exist.  This is a
 * different IRQ map than IRIX uses, but that's OK as Linux irq handling
 * is quite different anyway.
 */

/* Some initial interrupts to set up */
extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);

struct irqaction memerr_irq = {
	.handler = crime_memerr_intr,
	.flags = IRQF_DISABLED,
	.mask = CPU_MASK_NONE,
	.name = "CRIME memory error",
};
struct irqaction cpuerr_irq = {
	.handler = crime_cpuerr_intr,
	.flags = IRQF_DISABLED,
	.mask = CPU_MASK_NONE,
	.name = "CRIME CPU error",
};

/*
 * For interrupts wired from a single device to the CPU.  Only the clock
 * uses this it seems, which is IRQ 0 and IP7.
 */

static void enable_cpu_irq(unsigned int irq)
{
	set_c0_status(STATUSF_IP7);
}

static void disable_cpu_irq(unsigned int irq)
{
	clear_c0_status(STATUSF_IP7);
}

static void end_cpu_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
		enable_cpu_irq (irq);
}

static struct irq_chip ip32_cpu_interrupt = {
	.name = "IP32 CPU",
	.ack = disable_cpu_irq,
	.mask = disable_cpu_irq,
	.mask_ack = disable_cpu_irq,
	.unmask = enable_cpu_irq,
	.end = end_cpu_irq,
};

/*
 * This is for pure CRIME interrupts - ie not MACE.  The advantage?
 * We get to split the register in half and do faster lookups.
 */

static uint64_t crime_mask;

static void enable_crime_irq(unsigned int irq)
{
	crime_mask |= 1 << (irq - 1);
	crime->imask = crime_mask;
}

static void disable_crime_irq(unsigned int irq)
{
	crime_mask &= ~(1 << (irq - 1));
	crime->imask = crime_mask;
	flush_crime_bus();
}

static void mask_and_ack_crime_irq(unsigned int irq)
{
	/* Edge triggered interrupts must be cleared. */
	if ((irq >= CRIME_GBE0_IRQ && irq <= CRIME_GBE3_IRQ)
	    || (irq >= CRIME_RE_EMPTY_E_IRQ && irq <= CRIME_RE_IDLE_E_IRQ)
	    || (irq >= CRIME_SOFT0_IRQ && irq <= CRIME_SOFT2_IRQ)) {
	        uint64_t crime_int;
		crime_int = crime->hard_int;
		crime_int &= ~(1 << (irq - 1));
		crime->hard_int = crime_int;
	}
	disable_crime_irq(irq);
}

static void end_crime_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
		enable_crime_irq(irq);
}

static struct irq_chip ip32_crime_interrupt = {
	.name = "IP32 CRIME",
	.ack = mask_and_ack_crime_irq,
	.mask = disable_crime_irq,
	.mask_ack = mask_and_ack_crime_irq,
	.unmask = enable_crime_irq,
	.end = end_crime_irq,
};

/*
 * This is for MACE PCI interrupts.  We can decrease bus traffic by masking
 * as close to the source as possible.  This also means we can take the
 * next chunk of the CRIME register in one piece.
 */

static unsigned long macepci_mask;

static void enable_macepci_irq(unsigned int irq)
{
	macepci_mask |= MACEPCI_CONTROL_INT(irq - 9);
	mace->pci.control = macepci_mask;
	crime_mask |= 1 << (irq - 1);
	crime->imask = crime_mask;
}

static void disable_macepci_irq(unsigned int irq)
{
	crime_mask &= ~(1 << (irq - 1));
	crime->imask = crime_mask;
	flush_crime_bus();
	macepci_mask &= ~MACEPCI_CONTROL_INT(irq - 9);
	mace->pci.control = macepci_mask;
	flush_mace_bus();
}

static void end_macepci_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
		enable_macepci_irq(irq);
}

static struct irq_chip ip32_macepci_interrupt = {
	.name = "IP32 MACE PCI",
	.ack = disable_macepci_irq,
	.mask = disable_macepci_irq,
	.mask_ack = disable_macepci_irq,
	.unmask = enable_macepci_irq,
	.end = end_macepci_irq,
};

/* This is used for MACE ISA interrupts.  That means bits 4-6 in the
 * CRIME register.
 */

#define MACEISA_AUDIO_INT	(MACEISA_AUDIO_SW_INT |		\
				 MACEISA_AUDIO_SC_INT |		\
				 MACEISA_AUDIO1_DMAT_INT |	\
				 MACEISA_AUDIO1_OF_INT |	\
				 MACEISA_AUDIO2_DMAT_INT |	\
				 MACEISA_AUDIO2_MERR_INT |	\
				 MACEISA_AUDIO3_DMAT_INT |	\
				 MACEISA_AUDIO3_MERR_INT)
#define MACEISA_MISC_INT	(MACEISA_RTC_INT |		\
				 MACEISA_KEYB_INT |		\
				 MACEISA_KEYB_POLL_INT |	\
				 MACEISA_MOUSE_INT |		\
				 MACEISA_MOUSE_POLL_INT |	\
				 MACEISA_TIMER0_INT |		\
				 MACEISA_TIMER1_INT |		\
				 MACEISA_TIMER2_INT)
#define MACEISA_SUPERIO_INT	(MACEISA_PARALLEL_INT |		\
				 MACEISA_PAR_CTXA_INT |		\
				 MACEISA_PAR_CTXB_INT |		\
				 MACEISA_PAR_MERR_INT |		\
				 MACEISA_SERIAL1_INT |		\
				 MACEISA_SERIAL1_TDMAT_INT |	\
				 MACEISA_SERIAL1_TDMAPR_INT |	\
				 MACEISA_SERIAL1_TDMAME_INT |	\
				 MACEISA_SERIAL1_RDMAT_INT |	\
				 MACEISA_SERIAL1_RDMAOR_INT |	\
				 MACEISA_SERIAL2_INT |		\
				 MACEISA_SERIAL2_TDMAT_INT |	\
				 MACEISA_SERIAL2_TDMAPR_INT |	\
				 MACEISA_SERIAL2_TDMAME_INT |	\
				 MACEISA_SERIAL2_RDMAT_INT |	\
				 MACEISA_SERIAL2_RDMAOR_INT)

static unsigned long maceisa_mask;

static void enable_maceisa_irq (unsigned int irq)
{
	unsigned int crime_int = 0;

	DBG ("maceisa enable: %u\n", irq);

	switch (irq) {
	case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ:
		crime_int = MACE_AUDIO_INT;
		break;
	case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ:
		crime_int = MACE_MISC_INT;
		break;
	case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ:
		crime_int = MACE_SUPERIO_INT;
		break;
	}
	DBG ("crime_int %08x enabled\n", crime_int);
	crime_mask |= crime_int;
	crime->imask = crime_mask;
	maceisa_mask |= 1 << (irq - 33);
	mace->perif.ctrl.imask = maceisa_mask;
}

static void disable_maceisa_irq(unsigned int irq)
{
	unsigned int crime_int = 0;

	maceisa_mask &= ~(1 << (irq - 33));
        if(!(maceisa_mask & MACEISA_AUDIO_INT))
		crime_int |= MACE_AUDIO_INT;
        if(!(maceisa_mask & MACEISA_MISC_INT))
		crime_int |= MACE_MISC_INT;
        if(!(maceisa_mask & MACEISA_SUPERIO_INT))
		crime_int |= MACE_SUPERIO_INT;
	crime_mask &= ~crime_int;
	crime->imask = crime_mask;
	flush_crime_bus();
	mace->perif.ctrl.imask = maceisa_mask;
	flush_mace_bus();
}

static void mask_and_ack_maceisa_irq(unsigned int irq)
{
	unsigned long mace_int;

	switch (irq) {
	case MACEISA_PARALLEL_IRQ:
	case MACEISA_SERIAL1_TDMAPR_IRQ:
	case MACEISA_SERIAL2_TDMAPR_IRQ:
		/* edge triggered */
		mace_int = mace->perif.ctrl.istat;
		mace_int &= ~(1 << (irq - 33));
		mace->perif.ctrl.istat = mace_int;
		break;
	}
	disable_maceisa_irq(irq);
}

static void end_maceisa_irq(unsigned irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
		enable_maceisa_irq(irq);
}

static struct irq_chip ip32_maceisa_interrupt = {
	.name = "IP32 MACE ISA",
	.ack = mask_and_ack_maceisa_irq,
	.mask = disable_maceisa_irq,
	.mask_ack = mask_and_ack_maceisa_irq,
	.unmask = enable_maceisa_irq,
	.end = end_maceisa_irq,
};

/* This is used for regular non-ISA, non-PCI MACE interrupts.  That means
 * bits 0-3 and 7 in the CRIME register.
 */

static void enable_mace_irq(unsigned int irq)
{
	crime_mask |= 1 << (irq - 1);
	crime->imask = crime_mask;
}

static void disable_mace_irq(unsigned int irq)
{
	crime_mask &= ~(1 << (irq - 1));
	crime->imask = crime_mask;
	flush_crime_bus();
}

static void end_mace_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
		enable_mace_irq(irq);
}

static struct irq_chip ip32_mace_interrupt = {
	.name = "IP32 MACE",
	.ack = disable_mace_irq,
	.mask = disable_mace_irq,
	.mask_ack = disable_mace_irq,
	.unmask = enable_mace_irq,
	.end = end_mace_irq,
};

static void ip32_unknown_interrupt(void)
{
	printk ("Unknown interrupt occurred!\n");
	printk ("cp0_status: %08x\n", read_c0_status());
	printk ("cp0_cause: %08x\n", read_c0_cause());
	printk ("CRIME intr mask: %016lx\n", crime->imask);
	printk ("CRIME intr status: %016lx\n", crime->istat);
	printk ("CRIME hardware intr register: %016lx\n", crime->hard_int);
	printk ("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask);
	printk ("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat);
	printk ("MACE PCI control register: %08x\n", mace->pci.control);

	printk("Register dump:\n");
	show_regs(get_irq_regs());

	printk("Please mail this report to linux-mips@linux-mips.org\n");
	printk("Spinning...");
	while(1) ;
}

/* CRIME 1.1 appears to deliver all interrupts to this one pin. */
/* change this to loop over all edge-triggered irqs, exception masked out ones */
static void ip32_irq0(void)
{
	uint64_t crime_int;
	int irq = 0;

	crime_int = crime->istat & crime_mask;
	irq = __ffs(crime_int);
	crime_int = 1 << irq;

	if (crime_int & CRIME_MACEISA_INT_MASK) {
		unsigned long mace_int = mace->perif.ctrl.istat;
		irq = __ffs(mace_int & maceisa_mask) + 32;
	}
	irq++;
	DBG("*irq %u*\n", irq);
	do_IRQ(irq);
}

static void ip32_irq1(void)
{
	ip32_unknown_interrupt();
}

static void ip32_irq2(void)
{
	ip32_unknown_interrupt();
}

static void ip32_irq3(void)
{
	ip32_unknown_interrupt();
}

static void ip32_irq4(void)
{
	ip32_unknown_interrupt();
}

static void ip32_irq5(void)
{
	do_IRQ(IP32_R4K_TIMER_IRQ);
}

asmlinkage void plat_irq_dispatch(void)
{
	unsigned int pending = read_c0_status() & read_c0_cause();

	if (likely(pending & IE_IRQ0))
		ip32_irq0();
	else if (unlikely(pending & IE_IRQ1))
		ip32_irq1();
	else if (unlikely(pending & IE_IRQ2))
		ip32_irq2();
	else if (unlikely(pending & IE_IRQ3))
		ip32_irq3();
	else if (unlikely(pending & IE_IRQ4))
		ip32_irq4();
	else if (likely(pending & IE_IRQ5))
		ip32_irq5();
}

void __init arch_init_irq(void)
{
	unsigned int irq;

	/* Install our interrupt handler, then clear and disable all
	 * CRIME and MACE interrupts. */
	crime->imask = 0;
	crime->hard_int = 0;
	crime->soft_int = 0;
	mace->perif.ctrl.istat = 0;
	mace->perif.ctrl.imask = 0;

	for (irq = 0; irq <= IP32_IRQ_MAX; irq++) {
		struct irq_chip *controller;

		if (irq == IP32_R4K_TIMER_IRQ)
			controller = &ip32_cpu_interrupt;
		else if (irq <= MACE_PCI_BRIDGE_IRQ && irq >= MACE_VID_IN1_IRQ)
			controller = &ip32_mace_interrupt;
		else if (irq <= MACEPCI_SHARED2_IRQ && irq >= MACEPCI_SCSI0_IRQ)
			controller = &ip32_macepci_interrupt;
		else if (irq <= CRIME_VICE_IRQ && irq >= CRIME_GBE0_IRQ)
			controller = &ip32_crime_interrupt;
		else
			controller = &ip32_maceisa_interrupt;

		set_irq_chip(irq, controller);
	}
	setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
	setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);

#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
	change_c0_status(ST0_IM, ALLINTS);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Code to handle IP32 IRQs
	3	*
	4	* This file is subject to the terms and conditions of the GNU General Public
	5	* License. See the file "COPYING" in the main directory of this archive
	6	* for more details.
	7	*
	8	* Copyright (C) 2000 Harald Koerfgen
	9	* Copyright (C) 2001 Keith M Wesolowski
	10	*/
	11	#include <linux/init.h>
	12	#include <linux/kernel_stat.h>
	13	#include <linux/types.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/irq.h>
	16	#include <linux/bitops.h>
	17	#include <linux/kernel.h>
	18	#include <linux/slab.h>
	19	#include <linux/mm.h>
	20	#include <linux/random.h>
	21	#include <linux/sched.h>
	22
	23	#include <asm/mipsregs.h>
	24	#include <asm/signal.h>
	25	#include <asm/system.h>
	26	#include <asm/time.h>
	27	#include <asm/ip32/crime.h>
	28	#include <asm/ip32/mace.h>
	29	#include <asm/ip32/ip32_ints.h>
	30
	31	/* issue a PIO read to make sure no PIO writes are pending */
	32	static void inline flush_crime_bus(void)
	33	{
b6d7c7a9	34	crime->control;
1da177e4 LT	35	}
	36
	37	static void inline flush_mace_bus(void)
	38	{
b6d7c7a9	39	mace->perif.ctrl.misc;
1da177e4 LT	40	}
	41
	42	#undef DEBUG_IRQ
	43	#ifdef DEBUG_IRQ
	44	#define DBG(x...) printk(x)
	45	#else
	46	#define DBG(x...)
	47	#endif
	48
	49	/* O2 irq map
	50	*
	51	* IP0 -> software (ignored)
	52	* IP1 -> software (ignored)
	53	* IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ???
	54	* IP3 -> (irq1) X unknown
	55	* IP4 -> (irq2) X unknown
	56	* IP5 -> (irq3) X unknown
	57	* IP6 -> (irq4) X unknown
	58	* IP7 -> (irq5) 0 CPU count/compare timer (system timer)
	59	*
	60	* crime: (C)
	61	*
	62	* CRIME_INT_STAT 31:0:
	63	*
	64	* 0 -> 1 Video in 1
	65	* 1 -> 2 Video in 2
	66	* 2 -> 3 Video out
	67	* 3 -> 4 Mace ethernet
	68	* 4 -> S SuperIO sub-interrupt
	69	* 5 -> M Miscellaneous sub-interrupt
	70	* 6 -> A Audio sub-interrupt
	71	* 7 -> 8 PCI bridge errors
	72	* 8 -> 9 PCI SCSI aic7xxx 0
	73	* 9 -> 10 PCI SCSI aic7xxx 1
	74	* 10 -> 11 PCI slot 0
	75	* 11 -> 12 unused (PCI slot 1)
	76	* 12 -> 13 unused (PCI slot 2)
	77	* 13 -> 14 unused (PCI shared 0)
	78	* 14 -> 15 unused (PCI shared 1)
	79	* 15 -> 16 unused (PCI shared 2)
	80	* 16 -> 17 GBE0 (E)
	81	* 17 -> 18 GBE1 (E)
	82	* 18 -> 19 GBE2 (E)
	83	* 19 -> 20 GBE3 (E)
	84	* 20 -> 21 CPU errors
	85	* 21 -> 22 Memory errors
	86	* 22 -> 23 RE empty edge (E)
	87	* 23 -> 24 RE full edge (E)
	88	* 24 -> 25 RE idle edge (E)
	89	* 25 -> 26 RE empty level
	90	* 26 -> 27 RE full level
	91	* 27 -> 28 RE idle level
	92	* 28 -> 29 unused (software 0) (E)
	93	* 29 -> 30 unused (software 1) (E)
	94	* 30 -> 31 unused (software 2) - crime 1.5 CPU SysCorError (E)
	95	* 31 -> 32 VICE
	96	*
	97	* S, M, A: Use the MACE ISA interrupt register
	98	* MACE_ISA_INT_STAT 31:0
	99	*
	100	* 0-7 -> 33-40 Audio
	101	* 8 -> 41 RTC
	102	* 9 -> 42 Keyboard
	103	* 10 -> X Keyboard polled
104	* 11 -> 44 Mouse
105	* 12 -> X Mouse polled
106	* 13-15 -> 46-48 Count/compare timers
107	* 16-19 -> 49-52 Parallel (16 E)
108	* 20-25 -> 53-58 Serial 1 (22 E)
109	* 26-31 -> 59-64 Serial 2 (28 E)
110	*
111	* Note that this means IRQs 5-7, 43, and 45 do not exist. This is a
112	* different IRQ map than IRIX uses, but that's OK as Linux irq handling
113	* is quite different anyway.
114	*/
115
1da177e4	116	/* Some initial interrupts to set up */
937a8015 RB	117	extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
937a8015 RB	118	extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
1da177e4	119
4e45171c TG	120	struct irqaction memerr_irq = {
	121	.handler = crime_memerr_intr,
	122	.flags = IRQF_DISABLED,
	123	.mask = CPU_MASK_NONE,
	124	.name = "CRIME memory error",
	125	};
	126	struct irqaction cpuerr_irq = {
	127	.handler = crime_cpuerr_intr,
	128	.flags = IRQF_DISABLED,
	129	.mask = CPU_MASK_NONE,
	130	.name = "CRIME CPU error",
	131	};
1da177e4	132
1da177e4 LT	133	/*
	134	* For interrupts wired from a single device to the CPU. Only the clock
	135	* uses this it seems, which is IRQ 0 and IP7.
	136	*/
	137
	138	static void enable_cpu_irq(unsigned int irq)
	139	{
	140	set_c0_status(STATUSF_IP7);
	141	}
	142
1da177e4 LT	143	static void disable_cpu_irq(unsigned int irq)
	144	{
	145	clear_c0_status(STATUSF_IP7);
	146	}
	147
	148	static void end_cpu_irq(unsigned int irq)
	149	{
	150	if (!(irq_desc[irq].status & (IRQ_DISABLED \| IRQ_INPROGRESS)))
	151	enable_cpu_irq (irq);
	152	}
	153
94dee171	154	static struct irq_chip ip32_cpu_interrupt = {
70d21cde	155	.name = "IP32 CPU",
1603b5ac AN	156	.ack = disable_cpu_irq,
	157	.mask = disable_cpu_irq,
	158	.mask_ack = disable_cpu_irq,
	159	.unmask = enable_cpu_irq,
8ab00b9a	160	.end = end_cpu_irq,
1da177e4 LT	161	};
	162
	163	/*
	164	* This is for pure CRIME interrupts - ie not MACE. The advantage?
	165	* We get to split the register in half and do faster lookups.
	166	*/
	167
	168	static uint64_t crime_mask;
	169
	170	static void enable_crime_irq(unsigned int irq)
	171	{
1da177e4 LT	172	crime_mask \|= 1 << (irq - 1);
1da177e4 LT	173	crime->imask = crime_mask;
1da177e4 LT	174	}
	175
	176	static void disable_crime_irq(unsigned int irq)
	177	{
1da177e4 LT	178	crime_mask &= ~(1 << (irq - 1));
	179	crime->imask = crime_mask;
	180	flush_crime_bus();
1da177e4 LT	181	}
	182
	183	static void mask_and_ack_crime_irq(unsigned int irq)
	184	{
1da177e4 LT	185	/* Edge triggered interrupts must be cleared. */
	186	if ((irq >= CRIME_GBE0_IRQ && irq <= CRIME_GBE3_IRQ)
	187	\|\| (irq >= CRIME_RE_EMPTY_E_IRQ && irq <= CRIME_RE_IDLE_E_IRQ)
	188	\|\| (irq >= CRIME_SOFT0_IRQ && irq <= CRIME_SOFT2_IRQ)) {
	189	uint64_t crime_int;
1da177e4 LT	190	crime_int = crime->hard_int;
	191	crime_int &= ~(1 << (irq - 1));
	192	crime->hard_int = crime_int;
1da177e4 LT	193	}
	194	disable_crime_irq(irq);
	195	}
	196
	197	static void end_crime_irq(unsigned int irq)
	198	{
	199	if (!(irq_desc[irq].status & (IRQ_DISABLED \| IRQ_INPROGRESS)))
	200	enable_crime_irq(irq);
	201	}
	202
94dee171	203	static struct irq_chip ip32_crime_interrupt = {
70d21cde	204	.name = "IP32 CRIME",
8ab00b9a	205	.ack = mask_and_ack_crime_irq,
1603b5ac AN	206	.mask = disable_crime_irq,
	207	.mask_ack = mask_and_ack_crime_irq,
	208	.unmask = enable_crime_irq,
8ab00b9a	209	.end = end_crime_irq,
1da177e4 LT	210	};
	211
	212	/*
	213	* This is for MACE PCI interrupts. We can decrease bus traffic by masking
	214	* as close to the source as possible. This also means we can take the
	215	* next chunk of the CRIME register in one piece.
	216	*/
	217
	218	static unsigned long macepci_mask;
	219
	220	static void enable_macepci_irq(unsigned int irq)
	221	{
1da177e4 LT	222	macepci_mask \|= MACEPCI_CONTROL_INT(irq - 9);
	223	mace->pci.control = macepci_mask;
	224	crime_mask \|= 1 << (irq - 1);
	225	crime->imask = crime_mask;
1da177e4 LT	226	}
	227
	228	static void disable_macepci_irq(unsigned int irq)
	229	{
1da177e4 LT	230	crime_mask &= ~(1 << (irq - 1));
	231	crime->imask = crime_mask;
	232	flush_crime_bus();
	233	macepci_mask &= ~MACEPCI_CONTROL_INT(irq - 9);
	234	mace->pci.control = macepci_mask;
	235	flush_mace_bus();
1da177e4 LT	236	}
	237
	238	static void end_macepci_irq(unsigned int irq)
	239	{
	240	if (!(irq_desc[irq].status & (IRQ_DISABLED\|IRQ_INPROGRESS)))
	241	enable_macepci_irq(irq);
	242	}
	243
94dee171	244	static struct irq_chip ip32_macepci_interrupt = {
70d21cde	245	.name = "IP32 MACE PCI",
1603b5ac AN	246	.ack = disable_macepci_irq,
	247	.mask = disable_macepci_irq,
	248	.mask_ack = disable_macepci_irq,
	249	.unmask = enable_macepci_irq,
8ab00b9a	250	.end = end_macepci_irq,
1da177e4 LT	251	};
	252
	253	/* This is used for MACE ISA interrupts. That means bits 4-6 in the
	254	* CRIME register.
	255	*/
	256
	257	#define MACEISA_AUDIO_INT (MACEISA_AUDIO_SW_INT \| \
	258	MACEISA_AUDIO_SC_INT \| \
	259	MACEISA_AUDIO1_DMAT_INT \| \
	260	MACEISA_AUDIO1_OF_INT \| \
	261	MACEISA_AUDIO2_DMAT_INT \| \
	262	MACEISA_AUDIO2_MERR_INT \| \
	263	MACEISA_AUDIO3_DMAT_INT \| \
	264	MACEISA_AUDIO3_MERR_INT)
	265	#define MACEISA_MISC_INT (MACEISA_RTC_INT \| \
	266	MACEISA_KEYB_INT \| \
	267	MACEISA_KEYB_POLL_INT \| \
	268	MACEISA_MOUSE_INT \| \
	269	MACEISA_MOUSE_POLL_INT \| \
cfbae5d3 TS	270	MACEISA_TIMER0_INT \| \
	271	MACEISA_TIMER1_INT \| \
	272	MACEISA_TIMER2_INT)
1da177e4 LT	273	#define MACEISA_SUPERIO_INT (MACEISA_PARALLEL_INT \| \
	274	MACEISA_PAR_CTXA_INT \| \
	275	MACEISA_PAR_CTXB_INT \| \
	276	MACEISA_PAR_MERR_INT \| \
	277	MACEISA_SERIAL1_INT \| \
	278	MACEISA_SERIAL1_TDMAT_INT \| \
	279	MACEISA_SERIAL1_TDMAPR_INT \| \
	280	MACEISA_SERIAL1_TDMAME_INT \| \
	281	MACEISA_SERIAL1_RDMAT_INT \| \
	282	MACEISA_SERIAL1_RDMAOR_INT \| \
	283	MACEISA_SERIAL2_INT \| \
	284	MACEISA_SERIAL2_TDMAT_INT \| \
	285	MACEISA_SERIAL2_TDMAPR_INT \| \
	286	MACEISA_SERIAL2_TDMAME_INT \| \
	287	MACEISA_SERIAL2_RDMAT_INT \| \
	288	MACEISA_SERIAL2_RDMAOR_INT)
	289
	290	static unsigned long maceisa_mask;
	291
	292	static void enable_maceisa_irq (unsigned int irq)
	293	{
	294	unsigned int crime_int = 0;
1da177e4 LT	295
	296	DBG ("maceisa enable: %u\n", irq);
	297
	298	switch (irq) {
	299	case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ:
	300	crime_int = MACE_AUDIO_INT;
	301	break;
cfbae5d3	302	case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ:
1da177e4 LT	303	crime_int = MACE_MISC_INT;
	304	break;
	305	case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ:
	306	crime_int = MACE_SUPERIO_INT;
	307	break;
	308	}
	309	DBG ("crime_int %08x enabled\n", crime_int);
1da177e4 LT	310	crime_mask \|= crime_int;
	311	crime->imask = crime_mask;
	312	maceisa_mask \|= 1 << (irq - 33);
	313	mace->perif.ctrl.imask = maceisa_mask;
1da177e4 LT	314	}
	315
	316	static void disable_maceisa_irq(unsigned int irq)
	317	{
	318	unsigned int crime_int = 0;
1da177e4	319
1da177e4 LT	320	maceisa_mask &= ~(1 << (irq - 33));
	321	if(!(maceisa_mask & MACEISA_AUDIO_INT))
	322	crime_int \|= MACE_AUDIO_INT;
	323	if(!(maceisa_mask & MACEISA_MISC_INT))
	324	crime_int \|= MACE_MISC_INT;
	325	if(!(maceisa_mask & MACEISA_SUPERIO_INT))
	326	crime_int \|= MACE_SUPERIO_INT;
	327	crime_mask &= ~crime_int;
	328	crime->imask = crime_mask;
	329	flush_crime_bus();
	330	mace->perif.ctrl.imask = maceisa_mask;
	331	flush_mace_bus();
1da177e4 LT	332	}
	333
	334	static void mask_and_ack_maceisa_irq(unsigned int irq)
	335	{
1603b5ac	336	unsigned long mace_int;
1da177e4 LT	337
	338	switch (irq) {
	339	case MACEISA_PARALLEL_IRQ:
	340	case MACEISA_SERIAL1_TDMAPR_IRQ:
	341	case MACEISA_SERIAL2_TDMAPR_IRQ:
	342	/* edge triggered */
1da177e4 LT	343	mace_int = mace->perif.ctrl.istat;
	344	mace_int &= ~(1 << (irq - 33));
	345	mace->perif.ctrl.istat = mace_int;
1da177e4 LT	346	break;
	347	}
	348	disable_maceisa_irq(irq);
	349	}
	350
	351	static void end_maceisa_irq(unsigned irq)
	352	{
	353	if (!(irq_desc[irq].status & (IRQ_DISABLED \| IRQ_INPROGRESS)))
	354	enable_maceisa_irq(irq);
	355	}
	356
94dee171	357	static struct irq_chip ip32_maceisa_interrupt = {
70d21cde	358	.name = "IP32 MACE ISA",
8ab00b9a	359	.ack = mask_and_ack_maceisa_irq,
1603b5ac AN	360	.mask = disable_maceisa_irq,
	361	.mask_ack = mask_and_ack_maceisa_irq,
	362	.unmask = enable_maceisa_irq,
8ab00b9a	363	.end = end_maceisa_irq,
1da177e4 LT	364	};
	365
	366	/* This is used for regular non-ISA, non-PCI MACE interrupts. That means
	367	* bits 0-3 and 7 in the CRIME register.
	368	*/
	369
	370	static void enable_mace_irq(unsigned int irq)
	371	{
1da177e4 LT	372	crime_mask \|= 1 << (irq - 1);
1da177e4 LT	373	crime->imask = crime_mask;
1da177e4 LT	374	}
	375
	376	static void disable_mace_irq(unsigned int irq)
	377	{
1da177e4 LT	378	crime_mask &= ~(1 << (irq - 1));
	379	crime->imask = crime_mask;
	380	flush_crime_bus();
1da177e4 LT	381	}
	382
	383	static void end_mace_irq(unsigned int irq)
	384	{
	385	if (!(irq_desc[irq].status & (IRQ_DISABLED\|IRQ_INPROGRESS)))
	386	enable_mace_irq(irq);
	387	}
	388
94dee171	389	static struct irq_chip ip32_mace_interrupt = {
70d21cde	390	.name = "IP32 MACE",
1603b5ac AN	391	.ack = disable_mace_irq,
	392	.mask = disable_mace_irq,
	393	.mask_ack = disable_mace_irq,
	394	.unmask = enable_mace_irq,
8ab00b9a	395	.end = end_mace_irq,
1da177e4 LT	396	};
1da177e4 LT	397
937a8015	398	static void ip32_unknown_interrupt(void)
1da177e4 LT	399	{
	400	printk ("Unknown interrupt occurred!\n");
	401	printk ("cp0_status: %08x\n", read_c0_status());
	402	printk ("cp0_cause: %08x\n", read_c0_cause());
	403	printk ("CRIME intr mask: %016lx\n", crime->imask);
	404	printk ("CRIME intr status: %016lx\n", crime->istat);
	405	printk ("CRIME hardware intr register: %016lx\n", crime->hard_int);
	406	printk ("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask);
	407	printk ("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat);
	408	printk ("MACE PCI control register: %08x\n", mace->pci.control);
	409
	410	printk("Register dump:\n");
937a8015	411	show_regs(get_irq_regs());
1da177e4 LT	412
	413	printk("Please mail this report to linux-mips@linux-mips.org\n");
	414	printk("Spinning...");
	415	while(1) ;
	416	}
	417
	418	/* CRIME 1.1 appears to deliver all interrupts to this one pin. */
	419	/* change this to loop over all edge-triggered irqs, exception masked out ones */
937a8015	420	static void ip32_irq0(void)
1da177e4 LT	421	{
	422	uint64_t crime_int;
	423	int irq = 0;
	424
	425	crime_int = crime->istat & crime_mask;
6f8782c4 AN	426	irq = __ffs(crime_int);
6f8782c4 AN	427	crime_int = 1 << irq;
1da177e4 LT	428
	429	if (crime_int & CRIME_MACEISA_INT_MASK) {
	430	unsigned long mace_int = mace->perif.ctrl.istat;
6f8782c4	431	irq = __ffs(mace_int & maceisa_mask) + 32;
1da177e4	432	}
6f8782c4	433	irq++;
1da177e4	434	DBG("irq %u\n", irq);
937a8015	435	do_IRQ(irq);
1da177e4 LT	436	}
1da177e4 LT	437
937a8015	438	static void ip32_irq1(void)
1da177e4	439	{
937a8015	440	ip32_unknown_interrupt();
1da177e4 LT	441	}
1da177e4 LT	442
937a8015	443	static void ip32_irq2(void)
1da177e4	444	{
937a8015	445	ip32_unknown_interrupt();
1da177e4 LT	446	}
1da177e4 LT	447
937a8015	448	static void ip32_irq3(void)
1da177e4	449	{
937a8015	450	ip32_unknown_interrupt();
1da177e4 LT	451	}
1da177e4 LT	452
937a8015	453	static void ip32_irq4(void)
1da177e4	454	{
937a8015	455	ip32_unknown_interrupt();
1da177e4 LT	456	}
1da177e4 LT	457
937a8015	458	static void ip32_irq5(void)
1da177e4	459	{
7bcf7717	460	do_IRQ(IP32_R4K_TIMER_IRQ);
1da177e4 LT	461	}
1da177e4 LT	462
937a8015	463	asmlinkage void plat_irq_dispatch(void)
e4ac58af	464	{
119537c0	465	unsigned int pending = read_c0_status() & read_c0_cause();
e4ac58af RB	466
e4ac58af RB	467	if (likely(pending & IE_IRQ0))
937a8015	468	ip32_irq0();
e4ac58af	469	else if (unlikely(pending & IE_IRQ1))
937a8015	470	ip32_irq1();
e4ac58af	471	else if (unlikely(pending & IE_IRQ2))
937a8015	472	ip32_irq2();
e4ac58af	473	else if (unlikely(pending & IE_IRQ3))
937a8015	474	ip32_irq3();
e4ac58af	475	else if (unlikely(pending & IE_IRQ4))
937a8015	476	ip32_irq4();
e4ac58af	477	else if (likely(pending & IE_IRQ5))
937a8015	478	ip32_irq5();
e4ac58af RB	479	}
e4ac58af RB	480
1da177e4 LT	481	void __init arch_init_irq(void)
	482	{
	483	unsigned int irq;
	484
	485	/* Install our interrupt handler, then clear and disable all
	486	* CRIME and MACE interrupts. */
	487	crime->imask = 0;
	488	crime->hard_int = 0;
	489	crime->soft_int = 0;
	490	mace->perif.ctrl.istat = 0;
	491	mace->perif.ctrl.imask = 0;
1da177e4 LT	492
1da177e4 LT	493	for (irq = 0; irq <= IP32_IRQ_MAX; irq++) {
94dee171	494	struct irq_chip *controller;
1da177e4 LT	495
	496	if (irq == IP32_R4K_TIMER_IRQ)
	497	controller = &ip32_cpu_interrupt;
	498	else if (irq <= MACE_PCI_BRIDGE_IRQ && irq >= MACE_VID_IN1_IRQ)
	499	controller = &ip32_mace_interrupt;
	500	else if (irq <= MACEPCI_SHARED2_IRQ && irq >= MACEPCI_SCSI0_IRQ)
	501	controller = &ip32_macepci_interrupt;
	502	else if (irq <= CRIME_VICE_IRQ && irq >= CRIME_GBE0_IRQ)
	503	controller = &ip32_crime_interrupt;
	504	else
	505	controller = &ip32_maceisa_interrupt;
	506
1603b5ac	507	set_irq_chip(irq, controller);
1da177e4 LT	508	}
	509	setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
	510	setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);
	511
	512	#define ALLINTS (IE_IRQ0 \| IE_IRQ1 \| IE_IRQ2 \| IE_IRQ3 \| IE_IRQ4 \| IE_IRQ5)
	513	change_c0_status(ST0_IM, ALLINTS);
	514	}