[deliverable/linux.git] / arch / mips / sgi-ip32 / ip32-irq.c

/*
 * Code to handle IP32 IRQs
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2000 Harald Koerfgen
 * Copyright (C) 2001 Keith M Wesolowski
 */
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/bitops.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/mm.h>
#include <linux/random.h>
#include <linux/sched.h>

#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <asm/signal.h>
#include <asm/system.h>
#include <asm/time.h>
#include <asm/ip32/crime.h>
#include <asm/ip32/mace.h>
#include <asm/ip32/ip32_ints.h>

/* issue a PIO read to make sure no PIO writes are pending */
static void inline flush_crime_bus(void)
{
	crime->control;
}

static void inline flush_mace_bus(void)
{
	mace->perif.ctrl.misc;
}

/*
 * O2 irq map
 *
 * IP0 -> software (ignored)
 * IP1 -> software (ignored)
 * IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ???
 * IP3 -> (irq1) X unknown
 * IP4 -> (irq2) X unknown
 * IP5 -> (irq3) X unknown
 * IP6 -> (irq4) X unknown
 * IP7 -> (irq5) 7 CPU count/compare timer (system timer)
 *
 * crime: (C)
 *
 * CRIME_INT_STAT 31:0:
 *
 * 0  ->  8  Video in 1
 * 1  ->  9 Video in 2
 * 2  -> 10  Video out
 * 3  -> 11  Mace ethernet
 * 4  -> S  SuperIO sub-interrupt
 * 5  -> M  Miscellaneous sub-interrupt
 * 6  -> A  Audio sub-interrupt
 * 7  -> 15  PCI bridge errors
 * 8  -> 16  PCI SCSI aic7xxx 0
 * 9  -> 17 PCI SCSI aic7xxx 1
 * 10 -> 18 PCI slot 0
 * 11 -> 19 unused (PCI slot 1)
 * 12 -> 20 unused (PCI slot 2)
 * 13 -> 21 unused (PCI shared 0)
 * 14 -> 22 unused (PCI shared 1)
 * 15 -> 23 unused (PCI shared 2)
 * 16 -> 24 GBE0 (E)
 * 17 -> 25 GBE1 (E)
 * 18 -> 26 GBE2 (E)
 * 19 -> 27 GBE3 (E)
 * 20 -> 28 CPU errors
 * 21 -> 29 Memory errors
 * 22 -> 30 RE empty edge (E)
 * 23 -> 31 RE full edge (E)
 * 24 -> 32 RE idle edge (E)
 * 25 -> 33 RE empty level
 * 26 -> 34 RE full level
 * 27 -> 35 RE idle level
 * 28 -> 36 unused (software 0) (E)
 * 29 -> 37 unused (software 1) (E)
 * 30 -> 38 unused (software 2) - crime 1.5 CPU SysCorError (E)
 * 31 -> 39 VICE
 *
 * S, M, A: Use the MACE ISA interrupt register
 * MACE_ISA_INT_STAT 31:0
 *
 * 0-7 -> 40-47 Audio
 * 8 -> 48 RTC
 * 9 -> 49 Keyboard
 * 10 -> X Keyboard polled
 * 11 -> 51 Mouse
 * 12 -> X Mouse polled
 * 13-15 -> 53-55 Count/compare timers
 * 16-19 -> 56-59 Parallel (16 E)
 * 20-25 -> 60-62 Serial 1 (22 E)
 * 26-31 -> 66-71 Serial 2 (28 E)
 *
 * Note that this means IRQs 12-14, 50, and 52 do not exist.  This is a
 * different IRQ map than IRIX uses, but that's OK as Linux irq handling
 * is quite different anyway.
 */

/* Some initial interrupts to set up */
extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);

struct irqaction memerr_irq = {
	.handler = crime_memerr_intr,
	.flags = IRQF_DISABLED,
	.name = "CRIME memory error",
};

struct irqaction cpuerr_irq = {
	.handler = crime_cpuerr_intr,
	.flags = IRQF_DISABLED,
	.name = "CRIME CPU error",
};

/*
 * This is for pure CRIME interrupts - ie not MACE.  The advantage?
 * We get to split the register in half and do faster lookups.
 */

static uint64_t crime_mask;

static inline void crime_enable_irq(unsigned int irq)
{
	unsigned int bit = irq - CRIME_IRQ_BASE;

	crime_mask |= 1 << bit;
	crime->imask = crime_mask;
}

static inline void crime_disable_irq(unsigned int irq)
{
	unsigned int bit = irq - CRIME_IRQ_BASE;

	crime_mask &= ~(1 << bit);
	crime->imask = crime_mask;
	flush_crime_bus();
}

static void crime_level_mask_and_ack_irq(unsigned int irq)
{
	crime_disable_irq(irq);
}

static void crime_level_end_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
		crime_enable_irq(irq);
}

static struct irq_chip crime_level_interrupt = {
	.name		= "IP32 CRIME",
	.ack		= crime_level_mask_and_ack_irq,
	.mask		= crime_disable_irq,
	.mask_ack	= crime_level_mask_and_ack_irq,
	.unmask		= crime_enable_irq,
	.end		= crime_level_end_irq,
};

static void crime_edge_mask_and_ack_irq(unsigned int irq)
{
	unsigned int bit = irq - CRIME_IRQ_BASE;
	uint64_t crime_int;

	/* Edge triggered interrupts must be cleared. */

	crime_int = crime->hard_int;
	crime_int &= ~(1 << bit);
	crime->hard_int = crime_int;

	crime_disable_irq(irq);
}

static void crime_edge_end_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
		crime_enable_irq(irq);
}

static struct irq_chip crime_edge_interrupt = {
	.name		= "IP32 CRIME",
	.ack		= crime_edge_mask_and_ack_irq,
	.mask		= crime_disable_irq,
	.mask_ack	= crime_edge_mask_and_ack_irq,
	.unmask		= crime_enable_irq,
	.end		= crime_edge_end_irq,
};

/*
 * This is for MACE PCI interrupts.  We can decrease bus traffic by masking
 * as close to the source as possible.  This also means we can take the
 * next chunk of the CRIME register in one piece.
 */

static unsigned long macepci_mask;

static void enable_macepci_irq(unsigned int irq)
{
	macepci_mask |= MACEPCI_CONTROL_INT(irq - MACEPCI_SCSI0_IRQ);
	mace->pci.control = macepci_mask;
	crime_mask |= 1 << (irq - CRIME_IRQ_BASE);
	crime->imask = crime_mask;
}

static void disable_macepci_irq(unsigned int irq)
{
	crime_mask &= ~(1 << (irq - CRIME_IRQ_BASE));
	crime->imask = crime_mask;
	flush_crime_bus();
	macepci_mask &= ~MACEPCI_CONTROL_INT(irq - MACEPCI_SCSI0_IRQ);
	mace->pci.control = macepci_mask;
	flush_mace_bus();
}

static void end_macepci_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
		enable_macepci_irq(irq);
}

static struct irq_chip ip32_macepci_interrupt = {
	.name = "IP32 MACE PCI",
	.ack = disable_macepci_irq,
	.mask = disable_macepci_irq,
	.mask_ack = disable_macepci_irq,
	.unmask = enable_macepci_irq,
	.end = end_macepci_irq,
};

/* This is used for MACE ISA interrupts.  That means bits 4-6 in the
 * CRIME register.
 */

#define MACEISA_AUDIO_INT	(MACEISA_AUDIO_SW_INT |		\
				 MACEISA_AUDIO_SC_INT |		\
				 MACEISA_AUDIO1_DMAT_INT |	\
				 MACEISA_AUDIO1_OF_INT |	\
				 MACEISA_AUDIO2_DMAT_INT |	\
				 MACEISA_AUDIO2_MERR_INT |	\
				 MACEISA_AUDIO3_DMAT_INT |	\
				 MACEISA_AUDIO3_MERR_INT)
#define MACEISA_MISC_INT	(MACEISA_RTC_INT |		\
				 MACEISA_KEYB_INT |		\
				 MACEISA_KEYB_POLL_INT |	\
				 MACEISA_MOUSE_INT |		\
				 MACEISA_MOUSE_POLL_INT |	\
				 MACEISA_TIMER0_INT |		\
				 MACEISA_TIMER1_INT |		\
				 MACEISA_TIMER2_INT)
#define MACEISA_SUPERIO_INT	(MACEISA_PARALLEL_INT |		\
				 MACEISA_PAR_CTXA_INT |		\
				 MACEISA_PAR_CTXB_INT |		\
				 MACEISA_PAR_MERR_INT |		\
				 MACEISA_SERIAL1_INT |		\
				 MACEISA_SERIAL1_TDMAT_INT |	\
				 MACEISA_SERIAL1_TDMAPR_INT |	\
				 MACEISA_SERIAL1_TDMAME_INT |	\
				 MACEISA_SERIAL1_RDMAT_INT |	\
				 MACEISA_SERIAL1_RDMAOR_INT |	\
				 MACEISA_SERIAL2_INT |		\
				 MACEISA_SERIAL2_TDMAT_INT |	\
				 MACEISA_SERIAL2_TDMAPR_INT |	\
				 MACEISA_SERIAL2_TDMAME_INT |	\
				 MACEISA_SERIAL2_RDMAT_INT |	\
				 MACEISA_SERIAL2_RDMAOR_INT)

static unsigned long maceisa_mask;

static void enable_maceisa_irq(unsigned int irq)
{
	unsigned int crime_int = 0;

	pr_debug("maceisa enable: %u\n", irq);

	switch (irq) {
	case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ:
		crime_int = MACE_AUDIO_INT;
		break;
	case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ:
		crime_int = MACE_MISC_INT;
		break;
	case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ:
		crime_int = MACE_SUPERIO_INT;
		break;
	}
	pr_debug("crime_int %08x enabled\n", crime_int);
	crime_mask |= crime_int;
	crime->imask = crime_mask;
	maceisa_mask |= 1 << (irq - MACEISA_AUDIO_SW_IRQ);
	mace->perif.ctrl.imask = maceisa_mask;
}

static void disable_maceisa_irq(unsigned int irq)
{
	unsigned int crime_int = 0;

	maceisa_mask &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ));
        if (!(maceisa_mask & MACEISA_AUDIO_INT))
		crime_int |= MACE_AUDIO_INT;
        if (!(maceisa_mask & MACEISA_MISC_INT))
		crime_int |= MACE_MISC_INT;
        if (!(maceisa_mask & MACEISA_SUPERIO_INT))
		crime_int |= MACE_SUPERIO_INT;
	crime_mask &= ~crime_int;
	crime->imask = crime_mask;
	flush_crime_bus();
	mace->perif.ctrl.imask = maceisa_mask;
	flush_mace_bus();
}

static void mask_and_ack_maceisa_irq(unsigned int irq)
{
	unsigned long mace_int;

	/* edge triggered */
	mace_int = mace->perif.ctrl.istat;
	mace_int &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ));
	mace->perif.ctrl.istat = mace_int;

	disable_maceisa_irq(irq);
}

static void end_maceisa_irq(unsigned irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
		enable_maceisa_irq(irq);
}

static struct irq_chip ip32_maceisa_level_interrupt = {
	.name		= "IP32 MACE ISA",
	.ack		= disable_maceisa_irq,
	.mask		= disable_maceisa_irq,
	.mask_ack	= disable_maceisa_irq,
	.unmask		= enable_maceisa_irq,
	.end		= end_maceisa_irq,
};

static struct irq_chip ip32_maceisa_edge_interrupt = {
	.name		= "IP32 MACE ISA",
	.ack		= mask_and_ack_maceisa_irq,
	.mask		= disable_maceisa_irq,
	.mask_ack	= mask_and_ack_maceisa_irq,
	.unmask		= enable_maceisa_irq,
	.end		= end_maceisa_irq,
};

/* This is used for regular non-ISA, non-PCI MACE interrupts.  That means
 * bits 0-3 and 7 in the CRIME register.
 */

static void enable_mace_irq(unsigned int irq)
{
	unsigned int bit = irq - CRIME_IRQ_BASE;

	crime_mask |= (1 << bit);
	crime->imask = crime_mask;
}

static void disable_mace_irq(unsigned int irq)
{
	unsigned int bit = irq - CRIME_IRQ_BASE;

	crime_mask &= ~(1 << bit);
	crime->imask = crime_mask;
	flush_crime_bus();
}

static void end_mace_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
		enable_mace_irq(irq);
}

static struct irq_chip ip32_mace_interrupt = {
	.name = "IP32 MACE",
	.ack = disable_mace_irq,
	.mask = disable_mace_irq,
	.mask_ack = disable_mace_irq,
	.unmask = enable_mace_irq,
	.end = end_mace_irq,
};

static void ip32_unknown_interrupt(void)
{
	printk("Unknown interrupt occurred!\n");
	printk("cp0_status: %08x\n", read_c0_status());
	printk("cp0_cause: %08x\n", read_c0_cause());
	printk("CRIME intr mask: %016lx\n", crime->imask);
	printk("CRIME intr status: %016lx\n", crime->istat);
	printk("CRIME hardware intr register: %016lx\n", crime->hard_int);
	printk("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask);
	printk("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat);
	printk("MACE PCI control register: %08x\n", mace->pci.control);

	printk("Register dump:\n");
	show_regs(get_irq_regs());

	printk("Please mail this report to linux-mips@linux-mips.org\n");
	printk("Spinning...");
	while(1) ;
}

/* CRIME 1.1 appears to deliver all interrupts to this one pin. */
/* change this to loop over all edge-triggered irqs, exception masked out ones */
static void ip32_irq0(void)
{
	uint64_t crime_int;
	int irq = 0;

	/*
	 * Sanity check interrupt numbering enum.
	 * MACE got 32 interrupts and there are 32 MACE ISA interrupts daisy
	 * chained.
	 */
	BUILD_BUG_ON(CRIME_VICE_IRQ - MACE_VID_IN1_IRQ != 31);
	BUILD_BUG_ON(MACEISA_SERIAL2_RDMAOR_IRQ - MACEISA_AUDIO_SW_IRQ != 31);

	crime_int = crime->istat & crime_mask;

	/* crime sometime delivers spurious interrupts, ignore them */
	if (unlikely(crime_int == 0))
		return;

	irq = MACE_VID_IN1_IRQ + __ffs(crime_int);

	if (crime_int & CRIME_MACEISA_INT_MASK) {
		unsigned long mace_int = mace->perif.ctrl.istat;
		irq = __ffs(mace_int & maceisa_mask) + MACEISA_AUDIO_SW_IRQ;
	}

	pr_debug("*irq %u*\n", irq);
	do_IRQ(irq);
}

static void ip32_irq1(void)
{
	ip32_unknown_interrupt();
}

static void ip32_irq2(void)
{
	ip32_unknown_interrupt();
}

static void ip32_irq3(void)
{
	ip32_unknown_interrupt();
}

static void ip32_irq4(void)
{
	ip32_unknown_interrupt();
}

static void ip32_irq5(void)
{
	do_IRQ(MIPS_CPU_IRQ_BASE + 7);
}

asmlinkage void plat_irq_dispatch(void)
{
	unsigned int pending = read_c0_status() & read_c0_cause();

	if (likely(pending & IE_IRQ0))
		ip32_irq0();
	else if (unlikely(pending & IE_IRQ1))
		ip32_irq1();
	else if (unlikely(pending & IE_IRQ2))
		ip32_irq2();
	else if (unlikely(pending & IE_IRQ3))
		ip32_irq3();
	else if (unlikely(pending & IE_IRQ4))
		ip32_irq4();
	else if (likely(pending & IE_IRQ5))
		ip32_irq5();
}

void __init arch_init_irq(void)
{
	unsigned int irq;

	/* Install our interrupt handler, then clear and disable all
	 * CRIME and MACE interrupts. */
	crime->imask = 0;
	crime->hard_int = 0;
	crime->soft_int = 0;
	mace->perif.ctrl.istat = 0;
	mace->perif.ctrl.imask = 0;

	mips_cpu_irq_init();
	for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) {
		switch (irq) {
		case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
			set_irq_chip_and_handler_name(irq,&ip32_mace_interrupt,
				handle_level_irq, "level");
			break;

		case MACEPCI_SCSI0_IRQ ...  MACEPCI_SHARED2_IRQ:
			set_irq_chip_and_handler_name(irq,
				&ip32_macepci_interrupt, handle_level_irq,
				"level");
			break;

		case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ:
			set_irq_chip_and_handler_name(irq,
				&crime_edge_interrupt, handle_edge_irq, "edge");
			break;
		case CRIME_CPUERR_IRQ:
		case CRIME_MEMERR_IRQ:
			set_irq_chip_and_handler_name(irq,
				&crime_level_interrupt, handle_level_irq,
				"level");
			break;

		case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ:
		case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ:
			set_irq_chip_and_handler_name(irq,
				&crime_edge_interrupt, handle_edge_irq, "edge");
			break;

		case CRIME_VICE_IRQ:
			set_irq_chip_and_handler_name(irq,
				&crime_edge_interrupt, handle_edge_irq, "edge");
			break;

		case MACEISA_PARALLEL_IRQ:
		case MACEISA_SERIAL1_TDMAPR_IRQ:
		case MACEISA_SERIAL2_TDMAPR_IRQ:
			set_irq_chip_and_handler_name(irq,
				&ip32_maceisa_edge_interrupt, handle_edge_irq,
				"edge");
			break;

		default:
			set_irq_chip_and_handler_name(irq,
				&ip32_maceisa_level_interrupt, handle_level_irq,
				"level");
			break;
		}
	}
	setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
	setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);

#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
	change_c0_status(ST0_IM, ALLINTS);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Code to handle IP32 IRQs
	3	*
	4	* This file is subject to the terms and conditions of the GNU General Public
	5	* License. See the file "COPYING" in the main directory of this archive
	6	* for more details.
	7	*
	8	* Copyright (C) 2000 Harald Koerfgen
	9	* Copyright (C) 2001 Keith M Wesolowski
	10	*/
	11	#include <linux/init.h>
	12	#include <linux/kernel_stat.h>
	13	#include <linux/types.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/irq.h>
	16	#include <linux/bitops.h>
	17	#include <linux/kernel.h>
	18	#include <linux/slab.h>
	19	#include <linux/mm.h>
	20	#include <linux/random.h>
	21	#include <linux/sched.h>
	22
dd67b155	23	#include <asm/irq_cpu.h>
1da177e4 LT	24	#include <asm/mipsregs.h>
	25	#include <asm/signal.h>
	26	#include <asm/system.h>
	27	#include <asm/time.h>
	28	#include <asm/ip32/crime.h>
	29	#include <asm/ip32/mace.h>
	30	#include <asm/ip32/ip32_ints.h>
	31
	32	/* issue a PIO read to make sure no PIO writes are pending */
	33	static void inline flush_crime_bus(void)
	34	{
b6d7c7a9	35	crime->control;
1da177e4 LT	36	}
	37
	38	static void inline flush_mace_bus(void)
	39	{
b6d7c7a9	40	mace->perif.ctrl.misc;
1da177e4 LT	41	}
1da177e4 LT	42
dd67b155 RB	43	/*
dd67b155 RB	44	* O2 irq map
1da177e4 LT	45	*
	46	* IP0 -> software (ignored)
	47	* IP1 -> software (ignored)
	48	* IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ???
	49	* IP3 -> (irq1) X unknown
	50	* IP4 -> (irq2) X unknown
	51	* IP5 -> (irq3) X unknown
	52	* IP6 -> (irq4) X unknown
dd67b155	53	* IP7 -> (irq5) 7 CPU count/compare timer (system timer)
1da177e4 LT	54	*
	55	* crime: (C)
	56	*
	57	* CRIME_INT_STAT 31:0:
	58	*
dd67b155 RB	59	* 0 -> 8 Video in 1
	60	* 1 -> 9 Video in 2
	61	* 2 -> 10 Video out
	62	* 3 -> 11 Mace ethernet
1da177e4 LT	63	* 4 -> S SuperIO sub-interrupt
	64	* 5 -> M Miscellaneous sub-interrupt
	65	* 6 -> A Audio sub-interrupt
dd67b155 RB	66	* 7 -> 15 PCI bridge errors
	67	* 8 -> 16 PCI SCSI aic7xxx 0
	68	* 9 -> 17 PCI SCSI aic7xxx 1
	69	* 10 -> 18 PCI slot 0
	70	* 11 -> 19 unused (PCI slot 1)
	71	* 12 -> 20 unused (PCI slot 2)
	72	* 13 -> 21 unused (PCI shared 0)
	73	* 14 -> 22 unused (PCI shared 1)
	74	* 15 -> 23 unused (PCI shared 2)
	75	* 16 -> 24 GBE0 (E)
	76	* 17 -> 25 GBE1 (E)
	77	* 18 -> 26 GBE2 (E)
	78	* 19 -> 27 GBE3 (E)
	79	* 20 -> 28 CPU errors
	80	* 21 -> 29 Memory errors
	81	* 22 -> 30 RE empty edge (E)
	82	* 23 -> 31 RE full edge (E)
	83	* 24 -> 32 RE idle edge (E)
	84	* 25 -> 33 RE empty level
	85	* 26 -> 34 RE full level
	86	* 27 -> 35 RE idle level
	87	* 28 -> 36 unused (software 0) (E)
	88	* 29 -> 37 unused (software 1) (E)
	89	* 30 -> 38 unused (software 2) - crime 1.5 CPU SysCorError (E)
	90	* 31 -> 39 VICE
1da177e4 LT	91	*
	92	* S, M, A: Use the MACE ISA interrupt register
	93	* MACE_ISA_INT_STAT 31:0
	94	*
dd67b155 RB	95	* 0-7 -> 40-47 Audio
	96	* 8 -> 48 RTC
	97	* 9 -> 49 Keyboard
1da177e4	98	* 10 -> X Keyboard polled
dd67b155	99	* 11 -> 51 Mouse
1da177e4	100	* 12 -> X Mouse polled
dd67b155 RB	101	* 13-15 -> 53-55 Count/compare timers
	102	* 16-19 -> 56-59 Parallel (16 E)
	103	* 20-25 -> 60-62 Serial 1 (22 E)
	104	* 26-31 -> 66-71 Serial 2 (28 E)
1da177e4	105	*
dd67b155	106	* Note that this means IRQs 12-14, 50, and 52 do not exist. This is a
1da177e4 LT	107	* different IRQ map than IRIX uses, but that's OK as Linux irq handling
	108	* is quite different anyway.
	109	*/
	110
1da177e4	111	/* Some initial interrupts to set up */
937a8015 RB	112	extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
937a8015 RB	113	extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
1da177e4	114
4e45171c TG	115	struct irqaction memerr_irq = {
	116	.handler = crime_memerr_intr,
	117	.flags = IRQF_DISABLED,
4e45171c TG	118	.name = "CRIME memory error",
4e45171c TG	119	};
8a13ecd7	120
4e45171c TG	121	struct irqaction cpuerr_irq = {
	122	.handler = crime_cpuerr_intr,
	123	.flags = IRQF_DISABLED,
4e45171c TG	124	.name = "CRIME CPU error",
4e45171c TG	125	};
1da177e4	126
1da177e4 LT	127	/*
	128	* This is for pure CRIME interrupts - ie not MACE. The advantage?
	129	* We get to split the register in half and do faster lookups.
	130	*/
	131
	132	static uint64_t crime_mask;
	133
8a13ecd7	134	static inline void crime_enable_irq(unsigned int irq)
1da177e4	135	{
8a13ecd7 RB	136	unsigned int bit = irq - CRIME_IRQ_BASE;
	137
	138	crime_mask \|= 1 << bit;
1da177e4	139	crime->imask = crime_mask;
1da177e4 LT	140	}
1da177e4 LT	141
8a13ecd7	142	static inline void crime_disable_irq(unsigned int irq)
1da177e4	143	{
8a13ecd7 RB	144	unsigned int bit = irq - CRIME_IRQ_BASE;
	145
	146	crime_mask &= ~(1 << bit);
1da177e4 LT	147	crime->imask = crime_mask;
1da177e4 LT	148	flush_crime_bus();
1da177e4 LT	149	}
1da177e4 LT	150
8a13ecd7 RB	151	static void crime_level_mask_and_ack_irq(unsigned int irq)
	152	{
	153	crime_disable_irq(irq);
	154	}
	155
	156	static void crime_level_end_irq(unsigned int irq)
	157	{
	158	if (!(irq_desc[irq].status & (IRQ_DISABLED \| IRQ_INPROGRESS)))
	159	crime_enable_irq(irq);
	160	}
	161
	162	static struct irq_chip crime_level_interrupt = {
	163	.name = "IP32 CRIME",
	164	.ack = crime_level_mask_and_ack_irq,
	165	.mask = crime_disable_irq,
	166	.mask_ack = crime_level_mask_and_ack_irq,
	167	.unmask = crime_enable_irq,
	168	.end = crime_level_end_irq,
	169	};
	170
	171	static void crime_edge_mask_and_ack_irq(unsigned int irq)
1da177e4	172	{
8a13ecd7 RB	173	unsigned int bit = irq - CRIME_IRQ_BASE;
	174	uint64_t crime_int;
	175
1da177e4	176	/* Edge triggered interrupts must be cleared. */
8a13ecd7 RB	177
	178	crime_int = crime->hard_int;
	179	crime_int &= ~(1 << bit);
	180	crime->hard_int = crime_int;
	181
	182	crime_disable_irq(irq);
1da177e4 LT	183	}
1da177e4 LT	184
8a13ecd7	185	static void crime_edge_end_irq(unsigned int irq)
1da177e4 LT	186	{
1da177e4 LT	187	if (!(irq_desc[irq].status & (IRQ_DISABLED \| IRQ_INPROGRESS)))
8a13ecd7	188	crime_enable_irq(irq);
1da177e4 LT	189	}
1da177e4 LT	190
8a13ecd7 RB	191	static struct irq_chip crime_edge_interrupt = {
	192	.name = "IP32 CRIME",
	193	.ack = crime_edge_mask_and_ack_irq,
	194	.mask = crime_disable_irq,
	195	.mask_ack = crime_edge_mask_and_ack_irq,
	196	.unmask = crime_enable_irq,
	197	.end = crime_edge_end_irq,
1da177e4 LT	198	};
	199
	200	/*
	201	* This is for MACE PCI interrupts. We can decrease bus traffic by masking
	202	* as close to the source as possible. This also means we can take the
	203	* next chunk of the CRIME register in one piece.
	204	*/
	205
	206	static unsigned long macepci_mask;
	207
	208	static void enable_macepci_irq(unsigned int irq)
	209	{
98ce4721	210	macepci_mask \|= MACEPCI_CONTROL_INT(irq - MACEPCI_SCSI0_IRQ);
1da177e4	211	mace->pci.control = macepci_mask;
98ce4721	212	crime_mask \|= 1 << (irq - CRIME_IRQ_BASE);
1da177e4	213	crime->imask = crime_mask;
1da177e4 LT	214	}
	215
	216	static void disable_macepci_irq(unsigned int irq)
	217	{
98ce4721	218	crime_mask &= ~(1 << (irq - CRIME_IRQ_BASE));
1da177e4 LT	219	crime->imask = crime_mask;
1da177e4 LT	220	flush_crime_bus();
98ce4721	221	macepci_mask &= ~MACEPCI_CONTROL_INT(irq - MACEPCI_SCSI0_IRQ);
1da177e4 LT	222	mace->pci.control = macepci_mask;
1da177e4 LT	223	flush_mace_bus();
1da177e4 LT	224	}
	225
	226	static void end_macepci_irq(unsigned int irq)
	227	{
	228	if (!(irq_desc[irq].status & (IRQ_DISABLED\|IRQ_INPROGRESS)))
	229	enable_macepci_irq(irq);
	230	}
	231
94dee171	232	static struct irq_chip ip32_macepci_interrupt = {
70d21cde	233	.name = "IP32 MACE PCI",
1603b5ac AN	234	.ack = disable_macepci_irq,
	235	.mask = disable_macepci_irq,
	236	.mask_ack = disable_macepci_irq,
	237	.unmask = enable_macepci_irq,
8ab00b9a	238	.end = end_macepci_irq,
1da177e4 LT	239	};
	240
	241	/* This is used for MACE ISA interrupts. That means bits 4-6 in the
	242	* CRIME register.
	243	*/
	244
	245	#define MACEISA_AUDIO_INT (MACEISA_AUDIO_SW_INT \| \
	246	MACEISA_AUDIO_SC_INT \| \
	247	MACEISA_AUDIO1_DMAT_INT \| \
	248	MACEISA_AUDIO1_OF_INT \| \
	249	MACEISA_AUDIO2_DMAT_INT \| \
	250	MACEISA_AUDIO2_MERR_INT \| \
	251	MACEISA_AUDIO3_DMAT_INT \| \
	252	MACEISA_AUDIO3_MERR_INT)
	253	#define MACEISA_MISC_INT (MACEISA_RTC_INT \| \
	254	MACEISA_KEYB_INT \| \
	255	MACEISA_KEYB_POLL_INT \| \
	256	MACEISA_MOUSE_INT \| \
	257	MACEISA_MOUSE_POLL_INT \| \
cfbae5d3 TS	258	MACEISA_TIMER0_INT \| \
	259	MACEISA_TIMER1_INT \| \
	260	MACEISA_TIMER2_INT)
1da177e4 LT	261	#define MACEISA_SUPERIO_INT (MACEISA_PARALLEL_INT \| \
	262	MACEISA_PAR_CTXA_INT \| \
	263	MACEISA_PAR_CTXB_INT \| \
	264	MACEISA_PAR_MERR_INT \| \
	265	MACEISA_SERIAL1_INT \| \
	266	MACEISA_SERIAL1_TDMAT_INT \| \
	267	MACEISA_SERIAL1_TDMAPR_INT \| \
	268	MACEISA_SERIAL1_TDMAME_INT \| \
	269	MACEISA_SERIAL1_RDMAT_INT \| \
	270	MACEISA_SERIAL1_RDMAOR_INT \| \
	271	MACEISA_SERIAL2_INT \| \
	272	MACEISA_SERIAL2_TDMAT_INT \| \
	273	MACEISA_SERIAL2_TDMAPR_INT \| \
	274	MACEISA_SERIAL2_TDMAME_INT \| \
	275	MACEISA_SERIAL2_RDMAT_INT \| \
	276	MACEISA_SERIAL2_RDMAOR_INT)
	277
	278	static unsigned long maceisa_mask;
	279
49a89efb	280	static void enable_maceisa_irq(unsigned int irq)
1da177e4 LT	281	{
1da177e4 LT	282	unsigned int crime_int = 0;
1da177e4	283
8a13ecd7	284	pr_debug("maceisa enable: %u\n", irq);
1da177e4 LT	285
	286	switch (irq) {
	287	case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ:
	288	crime_int = MACE_AUDIO_INT;
	289	break;
cfbae5d3	290	case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ:
1da177e4 LT	291	crime_int = MACE_MISC_INT;
	292	break;
	293	case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ:
	294	crime_int = MACE_SUPERIO_INT;
	295	break;
	296	}
8a13ecd7	297	pr_debug("crime_int %08x enabled\n", crime_int);
1da177e4 LT	298	crime_mask \|= crime_int;
1da177e4 LT	299	crime->imask = crime_mask;
98ce4721	300	maceisa_mask \|= 1 << (irq - MACEISA_AUDIO_SW_IRQ);
1da177e4	301	mace->perif.ctrl.imask = maceisa_mask;
1da177e4 LT	302	}
	303
	304	static void disable_maceisa_irq(unsigned int irq)
	305	{
	306	unsigned int crime_int = 0;
1da177e4	307
98ce4721	308	maceisa_mask &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ));
8a13ecd7	309	if (!(maceisa_mask & MACEISA_AUDIO_INT))
1da177e4	310	crime_int \|= MACE_AUDIO_INT;
8a13ecd7	311	if (!(maceisa_mask & MACEISA_MISC_INT))
1da177e4	312	crime_int \|= MACE_MISC_INT;
8a13ecd7	313	if (!(maceisa_mask & MACEISA_SUPERIO_INT))
1da177e4 LT	314	crime_int \|= MACE_SUPERIO_INT;
	315	crime_mask &= ~crime_int;
	316	crime->imask = crime_mask;
	317	flush_crime_bus();
	318	mace->perif.ctrl.imask = maceisa_mask;
	319	flush_mace_bus();
1da177e4 LT	320	}
	321
	322	static void mask_and_ack_maceisa_irq(unsigned int irq)
	323	{
1603b5ac	324	unsigned long mace_int;
1da177e4	325
c87e0909 RB	326	/* edge triggered */
	327	mace_int = mace->perif.ctrl.istat;
	328	mace_int &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ));
	329	mace->perif.ctrl.istat = mace_int;
	330
1da177e4 LT	331	disable_maceisa_irq(irq);
	332	}
	333
	334	static void end_maceisa_irq(unsigned irq)
	335	{
	336	if (!(irq_desc[irq].status & (IRQ_DISABLED \| IRQ_INPROGRESS)))
	337	enable_maceisa_irq(irq);
	338	}
	339
c87e0909 RB	340	static struct irq_chip ip32_maceisa_level_interrupt = {
	341	.name = "IP32 MACE ISA",
	342	.ack = disable_maceisa_irq,
	343	.mask = disable_maceisa_irq,
	344	.mask_ack = disable_maceisa_irq,
	345	.unmask = enable_maceisa_irq,
	346	.end = end_maceisa_irq,
	347	};
	348
	349	static struct irq_chip ip32_maceisa_edge_interrupt = {
8a13ecd7 RB	350	.name = "IP32 MACE ISA",
	351	.ack = mask_and_ack_maceisa_irq,
	352	.mask = disable_maceisa_irq,
	353	.mask_ack = mask_and_ack_maceisa_irq,
	354	.unmask = enable_maceisa_irq,
	355	.end = end_maceisa_irq,
1da177e4 LT	356	};
	357
	358	/* This is used for regular non-ISA, non-PCI MACE interrupts. That means
	359	* bits 0-3 and 7 in the CRIME register.
	360	*/
	361
	362	static void enable_mace_irq(unsigned int irq)
	363	{
98ce4721 RB	364	unsigned int bit = irq - CRIME_IRQ_BASE;
	365
	366	crime_mask \|= (1 << bit);
1da177e4	367	crime->imask = crime_mask;
1da177e4 LT	368	}
	369
	370	static void disable_mace_irq(unsigned int irq)
	371	{
98ce4721 RB	372	unsigned int bit = irq - CRIME_IRQ_BASE;
	373
	374	crime_mask &= ~(1 << bit);
1da177e4 LT	375	crime->imask = crime_mask;
1da177e4 LT	376	flush_crime_bus();
1da177e4 LT	377	}
	378
	379	static void end_mace_irq(unsigned int irq)
	380	{
	381	if (!(irq_desc[irq].status & (IRQ_DISABLED\|IRQ_INPROGRESS)))
	382	enable_mace_irq(irq);
	383	}
	384
94dee171	385	static struct irq_chip ip32_mace_interrupt = {
70d21cde	386	.name = "IP32 MACE",
1603b5ac AN	387	.ack = disable_mace_irq,
	388	.mask = disable_mace_irq,
	389	.mask_ack = disable_mace_irq,
	390	.unmask = enable_mace_irq,
8ab00b9a	391	.end = end_mace_irq,
1da177e4 LT	392	};
1da177e4 LT	393
937a8015	394	static void ip32_unknown_interrupt(void)
1da177e4	395	{
49a89efb RB	396	printk("Unknown interrupt occurred!\n");
	397	printk("cp0_status: %08x\n", read_c0_status());
	398	printk("cp0_cause: %08x\n", read_c0_cause());
	399	printk("CRIME intr mask: %016lx\n", crime->imask);
	400	printk("CRIME intr status: %016lx\n", crime->istat);
	401	printk("CRIME hardware intr register: %016lx\n", crime->hard_int);
	402	printk("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask);
	403	printk("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat);
	404	printk("MACE PCI control register: %08x\n", mace->pci.control);
1da177e4 LT	405
1da177e4 LT	406	printk("Register dump:\n");
937a8015	407	show_regs(get_irq_regs());
1da177e4 LT	408
	409	printk("Please mail this report to linux-mips@linux-mips.org\n");
	410	printk("Spinning...");
	411	while(1) ;
	412	}
	413
	414	/* CRIME 1.1 appears to deliver all interrupts to this one pin. */
	415	/* change this to loop over all edge-triggered irqs, exception masked out ones */
937a8015	416	static void ip32_irq0(void)
1da177e4 LT	417	{
	418	uint64_t crime_int;
	419	int irq = 0;
	420
dd67b155 RB	421	/*
	422	* Sanity check interrupt numbering enum.
	423	* MACE got 32 interrupts and there are 32 MACE ISA interrupts daisy
	424	* chained.
	425	*/
	426	BUILD_BUG_ON(CRIME_VICE_IRQ - MACE_VID_IN1_IRQ != 31);
	427	BUILD_BUG_ON(MACEISA_SERIAL2_RDMAOR_IRQ - MACEISA_AUDIO_SW_IRQ != 31);
	428
1da177e4	429	crime_int = crime->istat & crime_mask;
1faf7f25 TB	430
	431	/* crime sometime delivers spurious interrupts, ignore them */
	432	if (unlikely(crime_int == 0))
	433	return;
	434
dd67b155	435	irq = MACE_VID_IN1_IRQ + __ffs(crime_int);
1da177e4 LT	436
	437	if (crime_int & CRIME_MACEISA_INT_MASK) {
	438	unsigned long mace_int = mace->perif.ctrl.istat;
dd67b155	439	irq = __ffs(mace_int & maceisa_mask) + MACEISA_AUDIO_SW_IRQ;
1da177e4	440	}
dd67b155	441
8a13ecd7	442	pr_debug("irq %u\n", irq);
937a8015	443	do_IRQ(irq);
1da177e4 LT	444	}
1da177e4 LT	445
937a8015	446	static void ip32_irq1(void)
1da177e4	447	{
937a8015	448	ip32_unknown_interrupt();
1da177e4 LT	449	}
1da177e4 LT	450
937a8015	451	static void ip32_irq2(void)
1da177e4	452	{
937a8015	453	ip32_unknown_interrupt();
1da177e4 LT	454	}
1da177e4 LT	455
937a8015	456	static void ip32_irq3(void)
1da177e4	457	{
937a8015	458	ip32_unknown_interrupt();
1da177e4 LT	459	}
1da177e4 LT	460
937a8015	461	static void ip32_irq4(void)
1da177e4	462	{
937a8015	463	ip32_unknown_interrupt();
1da177e4 LT	464	}
1da177e4 LT	465
937a8015	466	static void ip32_irq5(void)
1da177e4	467	{
dd67b155	468	do_IRQ(MIPS_CPU_IRQ_BASE + 7);
1da177e4 LT	469	}
1da177e4 LT	470
937a8015	471	asmlinkage void plat_irq_dispatch(void)
e4ac58af	472	{
119537c0	473	unsigned int pending = read_c0_status() & read_c0_cause();
e4ac58af RB	474
e4ac58af RB	475	if (likely(pending & IE_IRQ0))
937a8015	476	ip32_irq0();
e4ac58af	477	else if (unlikely(pending & IE_IRQ1))
937a8015	478	ip32_irq1();
e4ac58af	479	else if (unlikely(pending & IE_IRQ2))
937a8015	480	ip32_irq2();
e4ac58af	481	else if (unlikely(pending & IE_IRQ3))
937a8015	482	ip32_irq3();
e4ac58af	483	else if (unlikely(pending & IE_IRQ4))
937a8015	484	ip32_irq4();
e4ac58af	485	else if (likely(pending & IE_IRQ5))
937a8015	486	ip32_irq5();
e4ac58af RB	487	}
e4ac58af RB	488
1da177e4 LT	489	void __init arch_init_irq(void)
	490	{
	491	unsigned int irq;
	492
	493	/* Install our interrupt handler, then clear and disable all
	494	* CRIME and MACE interrupts. */
	495	crime->imask = 0;
	496	crime->hard_int = 0;
	497	crime->soft_int = 0;
	498	mace->perif.ctrl.istat = 0;
	499	mace->perif.ctrl.imask = 0;
1da177e4	500
dd67b155	501	mips_cpu_irq_init();
98ce4721	502	for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) {
dd67b155 RB	503	switch (irq) {
dd67b155 RB	504	case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
c87e0909 RB	505	set_irq_chip_and_handler_name(irq,&ip32_mace_interrupt,
c87e0909 RB	506	handle_level_irq, "level");
dd67b155	507	break;
c87e0909	508
dd67b155	509	case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ:
c87e0909 RB	510	set_irq_chip_and_handler_name(irq,
	511	&ip32_macepci_interrupt, handle_level_irq,
	512	"level");
8a13ecd7	513	break;
c87e0909	514
8a13ecd7	515	case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ:
c87e0909 RB	516	set_irq_chip_and_handler_name(irq,
c87e0909 RB	517	&crime_edge_interrupt, handle_edge_irq, "edge");
8a13ecd7 RB	518	break;
	519	case CRIME_CPUERR_IRQ:
	520	case CRIME_MEMERR_IRQ:
c87e0909 RB	521	set_irq_chip_and_handler_name(irq,
	522	&crime_level_interrupt, handle_level_irq,
	523	"level");
dd67b155	524	break;
c87e0909	525
8a13ecd7 RB	526	case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ:
8a13ecd7 RB	527	case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ:
c87e0909 RB	528	set_irq_chip_and_handler_name(irq,
c87e0909 RB	529	&crime_edge_interrupt, handle_edge_irq, "edge");
8a13ecd7	530	break;
c87e0909	531
8a13ecd7	532	case CRIME_VICE_IRQ:
c87e0909 RB	533	set_irq_chip_and_handler_name(irq,
	534	&crime_edge_interrupt, handle_edge_irq, "edge");
	535	break;
	536
	537	case MACEISA_PARALLEL_IRQ:
	538	case MACEISA_SERIAL1_TDMAPR_IRQ:
	539	case MACEISA_SERIAL2_TDMAPR_IRQ:
	540	set_irq_chip_and_handler_name(irq,
	541	&ip32_maceisa_edge_interrupt, handle_edge_irq,
	542	"edge");
dd67b155	543	break;
c87e0909	544
dd67b155	545	default:
c87e0909 RB	546	set_irq_chip_and_handler_name(irq,
	547	&ip32_maceisa_level_interrupt, handle_level_irq,
	548	"level");
8a13ecd7	549	break;
dd67b155	550	}
1da177e4 LT	551	}
	552	setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
	553	setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);
	554
	555	#define ALLINTS (IE_IRQ0 \| IE_IRQ1 \| IE_IRQ2 \| IE_IRQ3 \| IE_IRQ4 \| IE_IRQ5)
	556	change_c0_status(ST0_IM, ALLINTS);
	557	}