[deliverable/linux.git] / arch / mips / sibyte / bcm1480 / irq.c

/*
 * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/linkage.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/kernel_stat.h>

#include <asm/errno.h>
#include <asm/irq_regs.h>
#include <asm/signal.h>
#include <asm/system.h>
#include <asm/io.h>

#include <asm/sibyte/bcm1480_regs.h>
#include <asm/sibyte/bcm1480_int.h>
#include <asm/sibyte/bcm1480_scd.h>

#include <asm/sibyte/sb1250_uart.h>
#include <asm/sibyte/sb1250.h>

/*
 * These are the routines that handle all the low level interrupt stuff.
 * Actions handled here are: initialization of the interrupt map, requesting of
 * interrupt lines by handlers, dispatching if interrupts to handlers, probing
 * for interrupt lines
 */


static void end_bcm1480_irq(unsigned int irq);
static void enable_bcm1480_irq(unsigned int irq);
static void disable_bcm1480_irq(unsigned int irq);
static void ack_bcm1480_irq(unsigned int irq);
#ifdef CONFIG_SMP
static int bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask);
#endif

#ifdef CONFIG_PCI
extern unsigned long ht_eoi_space;
#endif

static struct irq_chip bcm1480_irq_type = {
	.name = "BCM1480-IMR",
	.ack = ack_bcm1480_irq,
	.mask = disable_bcm1480_irq,
	.mask_ack = ack_bcm1480_irq,
	.unmask = enable_bcm1480_irq,
	.end = end_bcm1480_irq,
#ifdef CONFIG_SMP
	.set_affinity = bcm1480_set_affinity
#endif
};

/* Store the CPU id (not the logical number) */
int bcm1480_irq_owner[BCM1480_NR_IRQS];

DEFINE_SPINLOCK(bcm1480_imr_lock);

void bcm1480_mask_irq(int cpu, int irq)
{
	unsigned long flags, hl_spacing;
	u64 cur_ints;

	spin_lock_irqsave(&bcm1480_imr_lock, flags);
	hl_spacing = 0;
	if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) {
		hl_spacing = BCM1480_IMR_HL_SPACING;
		irq -= BCM1480_NR_IRQS_HALF;
	}
	cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
	cur_ints |= (((u64) 1) << irq);
	____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
	spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
}

void bcm1480_unmask_irq(int cpu, int irq)
{
	unsigned long flags, hl_spacing;
	u64 cur_ints;

	spin_lock_irqsave(&bcm1480_imr_lock, flags);
	hl_spacing = 0;
	if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) {
		hl_spacing = BCM1480_IMR_HL_SPACING;
		irq -= BCM1480_NR_IRQS_HALF;
	}
	cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
	cur_ints &= ~(((u64) 1) << irq);
	____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
	spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
}

#ifdef CONFIG_SMP
static int bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask)
{
	int i = 0, old_cpu, cpu, int_on, k;
	u64 cur_ints;
	unsigned long flags;
	unsigned int irq_dirty;

	if (cpumask_weight(mask) != 1) {
		printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
		return -1;
	}
	i = cpumask_first(mask);

	/* Convert logical CPU to physical CPU */
	cpu = cpu_logical_map(i);

	/* Protect against other affinity changers and IMR manipulation */
	spin_lock_irqsave(&bcm1480_imr_lock, flags);

	/* Swizzle each CPU's IMR (but leave the IP selection alone) */
	old_cpu = bcm1480_irq_owner[irq];
	irq_dirty = irq;
	if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) {
		irq_dirty -= BCM1480_NR_IRQS_HALF;
	}

	for (k=0; k<2; k++) { /* Loop through high and low interrupt mask register */
		cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
		int_on = !(cur_ints & (((u64) 1) << irq_dirty));
		if (int_on) {
			/* If it was on, mask it */
			cur_ints |= (((u64) 1) << irq_dirty);
			____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
		}
		bcm1480_irq_owner[irq] = cpu;
		if (int_on) {
			/* unmask for the new CPU */
			cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
			cur_ints &= ~(((u64) 1) << irq_dirty);
			____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
		}
	}
	spin_unlock_irqrestore(&bcm1480_imr_lock, flags);

	return 0;
}
#endif


/*****************************************************************************/

static void disable_bcm1480_irq(unsigned int irq)
{
	bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
}

static void enable_bcm1480_irq(unsigned int irq)
{
	bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
}


static void ack_bcm1480_irq(unsigned int irq)
{
	u64 pending;
	unsigned int irq_dirty;
	int k;

	/*
	 * If the interrupt was an HT interrupt, now is the time to
	 * clear it.  NOTE: we assume the HT bridge was set up to
	 * deliver the interrupts to all CPUs (which makes affinity
	 * changing easier for us)
	 */
	irq_dirty = irq;
	if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) {
		irq_dirty -= BCM1480_NR_IRQS_HALF;
	}
	for (k=0; k<2; k++) { /* Loop through high and low LDT interrupts */
		pending = __raw_readq(IOADDR(A_BCM1480_IMR_REGISTER(bcm1480_irq_owner[irq],
						R_BCM1480_IMR_LDT_INTERRUPT_H + (k*BCM1480_IMR_HL_SPACING))));
		pending &= ((u64)1 << (irq_dirty));
		if (pending) {
#ifdef CONFIG_SMP
			int i;
			for (i=0; i<NR_CPUS; i++) {
				/*
				 * Clear for all CPUs so an affinity switch
				 * doesn't find an old status
				 */
				__raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(cpu_logical_map(i),
								R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));
			}
#else
			__raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));
#endif

			/*
			 * Generate EOI.  For Pass 1 parts, EOI is a nop.  For
			 * Pass 2, the LDT world may be edge-triggered, but
			 * this EOI shouldn't hurt.  If they are
			 * level-sensitive, the EOI is required.
			 */
#ifdef CONFIG_PCI
			if (ht_eoi_space)
				*(uint32_t *)(ht_eoi_space+(irq<<16)+(7<<2)) = 0;
#endif
		}
	}
	bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
}


static void end_bcm1480_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
		bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
	}
}


void __init init_bcm1480_irqs(void)
{
	int i;

	for (i = 0; i < BCM1480_NR_IRQS; i++) {
		set_irq_chip_and_handler(i, &bcm1480_irq_type, handle_level_irq);
		bcm1480_irq_owner[i] = 0;
	}
}

/*
 *  init_IRQ is called early in the boot sequence from init/main.c.  It
 *  is responsible for setting up the interrupt mapper and installing the
 *  handler that will be responsible for dispatching interrupts to the
 *  "right" place.
 */
/*
 * For now, map all interrupts to IP[2].  We could save
 * some cycles by parceling out system interrupts to different
 * IP lines, but keep it simple for bringup.  We'll also direct
 * all interrupts to a single CPU; we should probably route
 * PCI and LDT to one cpu and everything else to the other
 * to balance the load a bit.
 *
 * On the second cpu, everything is set to IP5, which is
 * ignored, EXCEPT the mailbox interrupt.  That one is
 * set to IP[2] so it is handled.  This is needed so we
 * can do cross-cpu function calls, as requred by SMP
 */

#define IMR_IP2_VAL	K_BCM1480_INT_MAP_I0
#define IMR_IP3_VAL	K_BCM1480_INT_MAP_I1
#define IMR_IP4_VAL	K_BCM1480_INT_MAP_I2
#define IMR_IP5_VAL	K_BCM1480_INT_MAP_I3
#define IMR_IP6_VAL	K_BCM1480_INT_MAP_I4

void __init arch_init_irq(void)
{
	unsigned int i, cpu;
	u64 tmp;
	unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
		STATUSF_IP1 | STATUSF_IP0;

	/* Default everything to IP2 */
	/* Start with _high registers which has no bit 0 interrupt source */
	for (i = 1; i < BCM1480_NR_IRQS_HALF; i++) {	/* was I0 */
		for (cpu = 0; cpu < 4; cpu++) {
			__raw_writeq(IMR_IP2_VAL,
				     IOADDR(A_BCM1480_IMR_REGISTER(cpu,
								   R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (i << 3)));
		}
	}

	/* Now do _low registers */
	for (i = 0; i < BCM1480_NR_IRQS_HALF; i++) {
		for (cpu = 0; cpu < 4; cpu++) {
			__raw_writeq(IMR_IP2_VAL,
				     IOADDR(A_BCM1480_IMR_REGISTER(cpu,
								   R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) + (i << 3)));
		}
	}

	init_bcm1480_irqs();

	/*
	 * Map the high 16 bits of mailbox_0 registers to IP[3], for
	 * inter-cpu messages
	 */
	/* Was I1 */
	for (cpu = 0; cpu < 4; cpu++) {
		__raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
						 (K_BCM1480_INT_MBOX_0_0 << 3)));
        }


	/* Clear the mailboxes.  The firmware may leave them dirty */
	for (cpu = 0; cpu < 4; cpu++) {
		__raw_writeq(0xffffffffffffffffULL,
			     IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_0_CLR_CPU)));
		__raw_writeq(0xffffffffffffffffULL,
			     IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_1_CLR_CPU)));
	}


	/* Mask everything except the high 16 bit of mailbox_0 registers for all cpus */
	tmp = ~((u64) 0) ^ ( (((u64) 1) << K_BCM1480_INT_MBOX_0_0));
	for (cpu = 0; cpu < 4; cpu++) {
		__raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_H)));
	}
	tmp = ~((u64) 0);
	for (cpu = 0; cpu < 4; cpu++) {
		__raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L)));
	}

	/*
	 * Note that the timer interrupts are also mapped, but this is
	 * done in bcm1480_time_init().  Also, the profiling driver
	 * does its own management of IP7.
	 */

	/* Enable necessary IPs, disable the rest */
	change_c0_status(ST0_IM, imask);
}

extern void bcm1480_mailbox_interrupt(void);

static inline void dispatch_ip2(void)
{
	unsigned long long mask_h, mask_l;
	unsigned int cpu = smp_processor_id();
	unsigned long base;

	/*
	 * Default...we've hit an IP[2] interrupt, which means we've got to
	 * check the 1480 interrupt registers to figure out what to do.  Need
	 * to detect which CPU we're on, now that smp_affinity is supported.
	 */
	base = A_BCM1480_IMR_MAPPER(cpu);
	mask_h = __raw_readq(
		IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H));
	mask_l = __raw_readq(
		IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L));

	if (mask_h) {
		if (mask_h ^ 1)
			do_IRQ(fls64(mask_h) - 1);
		else if (mask_l)
			do_IRQ(63 + fls64(mask_l));
	}
}

asmlinkage void plat_irq_dispatch(void)
{
	unsigned int cpu = smp_processor_id();
	unsigned int pending;

#ifdef CONFIG_SIBYTE_BCM1480_PROF
	/* Set compare to count to silence count/compare timer interrupts */
	write_c0_compare(read_c0_count());
#endif

	pending = read_c0_cause() & read_c0_status();

#ifdef CONFIG_SIBYTE_BCM1480_PROF
	if (pending & CAUSEF_IP7)	/* Cpu performance counter interrupt */
		sbprof_cpu_intr();
	else
#endif

	if (pending & CAUSEF_IP4)
		do_IRQ(K_BCM1480_INT_TIMER_0 + cpu);
#ifdef CONFIG_SMP
	else if (pending & CAUSEF_IP3)
		bcm1480_mailbox_interrupt();
#endif

	else if (pending & CAUSEF_IP2)
		dispatch_ip2();
}
Commit	Line	Data
f137e463 AI	1	/*
	2	* Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version 2
	7	* of the License, or (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	17	*/
f137e463 AI	18	#include <linux/kernel.h>
	19	#include <linux/init.h>
	20	#include <linux/linkage.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/spinlock.h>
	23	#include <linux/mm.h>
	24	#include <linux/slab.h>
	25	#include <linux/kernel_stat.h>
	26
	27	#include <asm/errno.h>
937a8015	28	#include <asm/irq_regs.h>
f137e463 AI	29	#include <asm/signal.h>
f137e463 AI	30	#include <asm/system.h>
f137e463 AI	31	#include <asm/io.h>
	32
	33	#include <asm/sibyte/bcm1480_regs.h>
	34	#include <asm/sibyte/bcm1480_int.h>
	35	#include <asm/sibyte/bcm1480_scd.h>
	36
	37	#include <asm/sibyte/sb1250_uart.h>
	38	#include <asm/sibyte/sb1250.h>
	39
	40	/*
	41	* These are the routines that handle all the low level interrupt stuff.
	42	* Actions handled here are: initialization of the interrupt map, requesting of
	43	* interrupt lines by handlers, dispatching if interrupts to handlers, probing
	44	* for interrupt lines
	45	*/
	46
	47
f137e463 AI	48	static void end_bcm1480_irq(unsigned int irq);
	49	static void enable_bcm1480_irq(unsigned int irq);
	50	static void disable_bcm1480_irq(unsigned int irq);
f137e463 AI	51	static void ack_bcm1480_irq(unsigned int irq);
f137e463 AI	52	#ifdef CONFIG_SMP
d5dedd45	53	static int bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask);
f137e463 AI	54	#endif
	55
	56	#ifdef CONFIG_PCI
	57	extern unsigned long ht_eoi_space;
	58	#endif
	59
94dee171	60	static struct irq_chip bcm1480_irq_type = {
70d21cde	61	.name = "BCM1480-IMR",
f137e463	62	.ack = ack_bcm1480_irq,
1603b5ac AN	63	.mask = disable_bcm1480_irq,
	64	.mask_ack = ack_bcm1480_irq,
	65	.unmask = enable_bcm1480_irq,
f137e463 AI	66	.end = end_bcm1480_irq,
	67	#ifdef CONFIG_SMP
	68	.set_affinity = bcm1480_set_affinity
	69	#endif
	70	};
	71
	72	/* Store the CPU id (not the logical number) */
	73	int bcm1480_irq_owner[BCM1480_NR_IRQS];
	74
	75	DEFINE_SPINLOCK(bcm1480_imr_lock);
	76
	77	void bcm1480_mask_irq(int cpu, int irq)
	78	{
fbd0ed37 RB	79	unsigned long flags, hl_spacing;
fbd0ed37 RB	80	u64 cur_ints;
f137e463 AI	81
	82	spin_lock_irqsave(&bcm1480_imr_lock, flags);
	83	hl_spacing = 0;
	84	if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) {
	85	hl_spacing = BCM1480_IMR_HL_SPACING;
	86	irq -= BCM1480_NR_IRQS_HALF;
	87	}
	88	cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
	89	cur_ints \|= (((u64) 1) << irq);
	90	____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
	91	spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
	92	}
	93
	94	void bcm1480_unmask_irq(int cpu, int irq)
	95	{
fbd0ed37 RB	96	unsigned long flags, hl_spacing;
fbd0ed37 RB	97	u64 cur_ints;
f137e463 AI	98
	99	spin_lock_irqsave(&bcm1480_imr_lock, flags);
	100	hl_spacing = 0;
	101	if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) {
	102	hl_spacing = BCM1480_IMR_HL_SPACING;
	103	irq -= BCM1480_NR_IRQS_HALF;
	104	}
	105	cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
	106	cur_ints &= ~(((u64) 1) << irq);
	107	____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
	108	spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
	109	}
	110
	111	#ifdef CONFIG_SMP
d5dedd45	112	static int bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask)
f137e463	113	{
76e1daee	114	int i = 0, old_cpu, cpu, int_on, k;
f137e463	115	u64 cur_ints;
f137e463 AI	116	unsigned long flags;
	117	unsigned int irq_dirty;
	118
0de26520	119	if (cpumask_weight(mask) != 1) {
f137e463	120	printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
d5dedd45	121	return -1;
f137e463	122	}
0de26520	123	i = cpumask_first(mask);
f137e463 AI	124
	125	/* Convert logical CPU to physical CPU */
	126	cpu = cpu_logical_map(i);
	127
	128	/* Protect against other affinity changers and IMR manipulation */
5d81b83d	129	spin_lock_irqsave(&bcm1480_imr_lock, flags);
f137e463 AI	130
	131	/* Swizzle each CPU's IMR (but leave the IP selection alone) */
	132	old_cpu = bcm1480_irq_owner[irq];
	133	irq_dirty = irq;
	134	if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) {
	135	irq_dirty -= BCM1480_NR_IRQS_HALF;
	136	}
	137
f137e463 AI	138	for (k=0; k<2; k++) { /* Loop through high and low interrupt mask register */
	139	cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
	140	int_on = !(cur_ints & (((u64) 1) << irq_dirty));
	141	if (int_on) {
	142	/* If it was on, mask it */
	143	cur_ints \|= (((u64) 1) << irq_dirty);
	144	____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
	145	}
	146	bcm1480_irq_owner[irq] = cpu;
	147	if (int_on) {
	148	/* unmask for the new CPU */
	149	cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
	150	cur_ints &= ~(((u64) 1) << irq_dirty);
	151	____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
	152	}
	153	}
5d81b83d	154	spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
d5dedd45 YL	155
d5dedd45 YL	156	return 0;
f137e463 AI	157	}
	158	#endif
	159
	160
f137e463 AI	161	/*****************************************************************************/
f137e463 AI	162
f137e463 AI	163	static void disable_bcm1480_irq(unsigned int irq)
	164	{
	165	bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
	166	}
	167
	168	static void enable_bcm1480_irq(unsigned int irq)
	169	{
	170	bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
	171	}
	172
	173
	174	static void ack_bcm1480_irq(unsigned int irq)
	175	{
	176	u64 pending;
	177	unsigned int irq_dirty;
76e1daee	178	int k;
f137e463 AI	179
	180	/*
	181	* If the interrupt was an HT interrupt, now is the time to
	182	* clear it. NOTE: we assume the HT bridge was set up to
	183	* deliver the interrupts to all CPUs (which makes affinity
	184	* changing easier for us)
	185	*/
	186	irq_dirty = irq;
	187	if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) {
	188	irq_dirty -= BCM1480_NR_IRQS_HALF;
	189	}
f137e463 AI	190	for (k=0; k<2; k++) { /* Loop through high and low LDT interrupts */
	191	pending = __raw_readq(IOADDR(A_BCM1480_IMR_REGISTER(bcm1480_irq_owner[irq],
	192	R_BCM1480_IMR_LDT_INTERRUPT_H + (k*BCM1480_IMR_HL_SPACING))));
	193	pending &= ((u64)1 << (irq_dirty));
	194	if (pending) {
	195	#ifdef CONFIG_SMP
	196	int i;
	197	for (i=0; i<NR_CPUS; i++) {
	198	/*
	199	* Clear for all CPUs so an affinity switch
	200	* doesn't find an old status
	201	*/
	202	__raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(cpu_logical_map(i),
	203	R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));
	204	}
	205	#else
	206	__raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING))));
	207	#endif
	208
	209	/*
	210	* Generate EOI. For Pass 1 parts, EOI is a nop. For
	211	* Pass 2, the LDT world may be edge-triggered, but
	212	* this EOI shouldn't hurt. If they are
	213	* level-sensitive, the EOI is required.
	214	*/
	215	#ifdef CONFIG_PCI
	216	if (ht_eoi_space)
	217	(uint32_t )(ht_eoi_space+(irq<<16)+(7<<2)) = 0;
	218	#endif
	219	}
	220	}
	221	bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
	222	}
	223
	224
	225	static void end_bcm1480_irq(unsigned int irq)
	226	{
	227	if (!(irq_desc[irq].status & (IRQ_DISABLED \| IRQ_INPROGRESS))) {
	228	bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
	229	}
	230	}
	231
	232
	233	void __init init_bcm1480_irqs(void)
	234	{
	235	int i;
	236
1603b5ac	237	for (i = 0; i < BCM1480_NR_IRQS; i++) {
c87e0909	238	set_irq_chip_and_handler(i, &bcm1480_irq_type, handle_level_irq);
1603b5ac	239	bcm1480_irq_owner[i] = 0;
f137e463 AI	240	}
	241	}
	242
f137e463 AI	243	/*
	244	* init_IRQ is called early in the boot sequence from init/main.c. It
	245	* is responsible for setting up the interrupt mapper and installing the
	246	* handler that will be responsible for dispatching interrupts to the
	247	* "right" place.
	248	*/
	249	/*
	250	* For now, map all interrupts to IP[2]. We could save
	251	* some cycles by parceling out system interrupts to different
	252	* IP lines, but keep it simple for bringup. We'll also direct
	253	* all interrupts to a single CPU; we should probably route
	254	* PCI and LDT to one cpu and everything else to the other
	255	* to balance the load a bit.
	256	*
	257	* On the second cpu, everything is set to IP5, which is
	258	* ignored, EXCEPT the mailbox interrupt. That one is
	259	* set to IP[2] so it is handled. This is needed so we
	260	* can do cross-cpu function calls, as requred by SMP
	261	*/
	262
	263	#define IMR_IP2_VAL K_BCM1480_INT_MAP_I0
	264	#define IMR_IP3_VAL K_BCM1480_INT_MAP_I1
	265	#define IMR_IP4_VAL K_BCM1480_INT_MAP_I2
	266	#define IMR_IP5_VAL K_BCM1480_INT_MAP_I3
	267	#define IMR_IP6_VAL K_BCM1480_INT_MAP_I4
	268
	269	void __init arch_init_irq(void)
	270	{
f137e463 AI	271	unsigned int i, cpu;
	272	u64 tmp;
	273	unsigned int imask = STATUSF_IP4 \| STATUSF_IP3 \| STATUSF_IP2 \|
	274	STATUSF_IP1 \| STATUSF_IP0;
	275
	276	/* Default everything to IP2 */
	277	/* Start with _high registers which has no bit 0 interrupt source */
	278	for (i = 1; i < BCM1480_NR_IRQS_HALF; i++) { /* was I0 */
	279	for (cpu = 0; cpu < 4; cpu++) {
	280	__raw_writeq(IMR_IP2_VAL,
	281	IOADDR(A_BCM1480_IMR_REGISTER(cpu,
	282	R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (i << 3)));
	283	}
	284	}
	285
	286	/* Now do _low registers */
	287	for (i = 0; i < BCM1480_NR_IRQS_HALF; i++) {
	288	for (cpu = 0; cpu < 4; cpu++) {
	289	__raw_writeq(IMR_IP2_VAL,
	290	IOADDR(A_BCM1480_IMR_REGISTER(cpu,
	291	R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) + (i << 3)));
	292	}
	293	}
	294
	295	init_bcm1480_irqs();
	296
	297	/*
	298	* Map the high 16 bits of mailbox_0 registers to IP[3], for
	299	* inter-cpu messages
	300	*/
	301	/* Was I1 */
	302	for (cpu = 0; cpu < 4; cpu++) {
	303	__raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
	304	(K_BCM1480_INT_MBOX_0_0 << 3)));
	305	}
	306
	307
	308	/* Clear the mailboxes. The firmware may leave them dirty */
	309	for (cpu = 0; cpu < 4; cpu++) {
	310	__raw_writeq(0xffffffffffffffffULL,
	311	IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_0_CLR_CPU)));
	312	__raw_writeq(0xffffffffffffffffULL,
	313	IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_1_CLR_CPU)));
	314	}
	315
	316
	317	/* Mask everything except the high 16 bit of mailbox_0 registers for all cpus */
	318	tmp = ~((u64) 0) ^ ( (((u64) 1) << K_BCM1480_INT_MBOX_0_0));
	319	for (cpu = 0; cpu < 4; cpu++) {
	320	__raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_H)));
	321	}
	322	tmp = ~((u64) 0);
	323	for (cpu = 0; cpu < 4; cpu++) {
	324	__raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L)));
	325	}
	326
f137e463 AI	327	/*
	328	* Note that the timer interrupts are also mapped, but this is
	329	* done in bcm1480_time_init(). Also, the profiling driver
	330	* does its own management of IP7.
	331	*/
	332
f137e463 AI	333	/* Enable necessary IPs, disable the rest */
f137e463 AI	334	change_c0_status(ST0_IM, imask);
f137e463 AI	335	}
f137e463 AI	336
937a8015	337	extern void bcm1480_mailbox_interrupt(void);
e4ac58af	338
d0453365 RB	339	static inline void dispatch_ip2(void)
	340	{
	341	unsigned long long mask_h, mask_l;
	342	unsigned int cpu = smp_processor_id();
	343	unsigned long base;
	344
	345	/*
	346	* Default...we've hit an IP[2] interrupt, which means we've got to
	347	* check the 1480 interrupt registers to figure out what to do. Need
	348	* to detect which CPU we're on, now that smp_affinity is supported.
	349	*/
	350	base = A_BCM1480_IMR_MAPPER(cpu);
	351	mask_h = __raw_readq(
	352	IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H));
	353	mask_l = __raw_readq(
	354	IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L));
	355
	356	if (mask_h) {
	357	if (mask_h ^ 1)
	358	do_IRQ(fls64(mask_h) - 1);
	359	else if (mask_l)
	360	do_IRQ(63 + fls64(mask_l));
	361	}
	362	}
	363
937a8015	364	asmlinkage void plat_irq_dispatch(void)
e4ac58af	365	{
a8401fa5	366	unsigned int cpu = smp_processor_id();
e4ac58af RB	367	unsigned int pending;
	368
	369	#ifdef CONFIG_SIBYTE_BCM1480_PROF
	370	/* Set compare to count to silence count/compare timer interrupts */
	371	write_c0_compare(read_c0_count());
	372	#endif
	373
34c2dd01	374	pending = read_c0_cause() & read_c0_status();
e4ac58af RB	375
	376	#ifdef CONFIG_SIBYTE_BCM1480_PROF
	377	if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */
937a8015	378	sbprof_cpu_intr();
6e61e85b	379	else
e4ac58af RB	380	#endif
e4ac58af RB	381
d0453365	382	if (pending & CAUSEF_IP4)
a8401fa5	383	do_IRQ(K_BCM1480_INT_TIMER_0 + cpu);
e4ac58af	384	#ifdef CONFIG_SMP
6e61e85b	385	else if (pending & CAUSEF_IP3)
937a8015	386	bcm1480_mailbox_interrupt();
e4ac58af RB	387	#endif
e4ac58af RB	388
d0453365 RB	389	else if (pending & CAUSEF_IP2)
d0453365 RB	390	dispatch_ip2();
e4ac58af	391	}