[deliverable/linux.git] / arch / mips / sibyte / sb1250 / irq.c

/*
 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/linkage.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/smp.h>
#include <linux/mm.h>
#include <linux/kernel_stat.h>

#include <asm/errno.h>
#include <asm/signal.h>
#include <asm/time.h>
#include <asm/io.h>

#include <asm/sibyte/sb1250_regs.h>
#include <asm/sibyte/sb1250_int.h>
#include <asm/sibyte/sb1250_uart.h>
#include <asm/sibyte/sb1250_scd.h>
#include <asm/sibyte/sb1250.h>

/*
 * These are the routines that handle all the low level interrupt stuff.
 * Actions handled here are: initialization of the interrupt map, requesting of
 * interrupt lines by handlers, dispatching if interrupts to handlers, probing
 * for interrupt lines
 */

#ifdef CONFIG_SIBYTE_HAS_LDT
extern unsigned long ldt_eoi_space;
#endif

/* Store the CPU id (not the logical number) */
int sb1250_irq_owner[SB1250_NR_IRQS];

static DEFINE_RAW_SPINLOCK(sb1250_imr_lock);

void sb1250_mask_irq(int cpu, int irq)
{
	unsigned long flags;
	u64 cur_ints;

	raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
	cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
					R_IMR_INTERRUPT_MASK));
	cur_ints |= (((u64) 1) << irq);
	____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
					R_IMR_INTERRUPT_MASK));
	raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
}

void sb1250_unmask_irq(int cpu, int irq)
{
	unsigned long flags;
	u64 cur_ints;

	raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
	cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
					R_IMR_INTERRUPT_MASK));
	cur_ints &= ~(((u64) 1) << irq);
	____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
					R_IMR_INTERRUPT_MASK));
	raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
}

#ifdef CONFIG_SMP
static int sb1250_set_affinity(struct irq_data *d, const struct cpumask *mask,
			       bool force)
{
	int i = 0, old_cpu, cpu, int_on;
	unsigned int irq = d->irq;
	u64 cur_ints;
	unsigned long flags;

	i = cpumask_first_and(mask, cpu_online_mask);

	/* Convert logical CPU to physical CPU */
	cpu = cpu_logical_map(i);

	/* Protect against other affinity changers and IMR manipulation */
	raw_spin_lock_irqsave(&sb1250_imr_lock, flags);

	/* Swizzle each CPU's IMR (but leave the IP selection alone) */
	old_cpu = sb1250_irq_owner[irq];
	cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
					R_IMR_INTERRUPT_MASK));
	int_on = !(cur_ints & (((u64) 1) << irq));
	if (int_on) {
		/* If it was on, mask it */
		cur_ints |= (((u64) 1) << irq);
		____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
					R_IMR_INTERRUPT_MASK));
	}
	sb1250_irq_owner[irq] = cpu;
	if (int_on) {
		/* unmask for the new CPU */
		cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
					R_IMR_INTERRUPT_MASK));
		cur_ints &= ~(((u64) 1) << irq);
		____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
					R_IMR_INTERRUPT_MASK));
	}
	raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);

	return 0;
}
#endif

static void disable_sb1250_irq(struct irq_data *d)
{
	unsigned int irq = d->irq;

	sb1250_mask_irq(sb1250_irq_owner[irq], irq);
}

static void enable_sb1250_irq(struct irq_data *d)
{
	unsigned int irq = d->irq;

	sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
}


static void ack_sb1250_irq(struct irq_data *d)
{
	unsigned int irq = d->irq;
#ifdef CONFIG_SIBYTE_HAS_LDT
	u64 pending;

	/*
	 * If the interrupt was an HT interrupt, now is the time to
	 * clear it.  NOTE: we assume the HT bridge was set up to
	 * deliver the interrupts to all CPUs (which makes affinity
	 * changing easier for us)
	 */
	pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
						    R_IMR_LDT_INTERRUPT)));
	pending &= ((u64)1 << (irq));
	if (pending) {
		int i;
		for (i=0; i<NR_CPUS; i++) {
			int cpu;
#ifdef CONFIG_SMP
			cpu = cpu_logical_map(i);
#else
			cpu = i;
#endif
			/*
			 * Clear for all CPUs so an affinity switch
			 * doesn't find an old status
			 */
			__raw_writeq(pending,
				     IOADDR(A_IMR_REGISTER(cpu,
						R_IMR_LDT_INTERRUPT_CLR)));
		}

		/*
		 * Generate EOI.  For Pass 1 parts, EOI is a nop.  For
		 * Pass 2, the LDT world may be edge-triggered, but
		 * this EOI shouldn't hurt.  If they are
		 * level-sensitive, the EOI is required.
		 */
		*(uint32_t *)(ldt_eoi_space+(irq<<16)+(7<<2)) = 0;
	}
#endif
	sb1250_mask_irq(sb1250_irq_owner[irq], irq);
}

static struct irq_chip sb1250_irq_type = {
	.name = "SB1250-IMR",
	.irq_mask_ack = ack_sb1250_irq,
	.irq_unmask = enable_sb1250_irq,
	.irq_mask = disable_sb1250_irq,
#ifdef CONFIG_SMP
	.irq_set_affinity = sb1250_set_affinity
#endif
};

void __init init_sb1250_irqs(void)
{
	int i;

	for (i = 0; i < SB1250_NR_IRQS; i++) {
		irq_set_chip_and_handler(i, &sb1250_irq_type,
					 handle_level_irq);
		sb1250_irq_owner[i] = 0;
	}
}


/*
 *  arch_init_irq is called early in the boot sequence from init/main.c via
 *  init_IRQ.  It is responsible for setting up the interrupt mapper and
 *  installing the handler that will be responsible for dispatching interrupts
 *  to the "right" place.
 */
/*
 * For now, map all interrupts to IP[2].  We could save
 * some cycles by parceling out system interrupts to different
 * IP lines, but keep it simple for bringup.  We'll also direct
 * all interrupts to a single CPU; we should probably route
 * PCI and LDT to one cpu and everything else to the other
 * to balance the load a bit.
 *
 * On the second cpu, everything is set to IP5, which is
 * ignored, EXCEPT the mailbox interrupt.  That one is
 * set to IP[2] so it is handled.  This is needed so we
 * can do cross-cpu function calls, as required by SMP
 */

#define IMR_IP2_VAL	K_INT_MAP_I0
#define IMR_IP3_VAL	K_INT_MAP_I1
#define IMR_IP4_VAL	K_INT_MAP_I2
#define IMR_IP5_VAL	K_INT_MAP_I3
#define IMR_IP6_VAL	K_INT_MAP_I4

void __init arch_init_irq(void)
{

	unsigned int i;
	u64 tmp;
	unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
		STATUSF_IP1 | STATUSF_IP0;

	/* Default everything to IP2 */
	for (i = 0; i < SB1250_NR_IRQS; i++) {	/* was I0 */
		__raw_writeq(IMR_IP2_VAL,
			     IOADDR(A_IMR_REGISTER(0,
						   R_IMR_INTERRUPT_MAP_BASE) +
				    (i << 3)));
		__raw_writeq(IMR_IP2_VAL,
			     IOADDR(A_IMR_REGISTER(1,
						   R_IMR_INTERRUPT_MAP_BASE) +
				    (i << 3)));
	}

	init_sb1250_irqs();

	/*
	 * Map the high 16 bits of the mailbox registers to IP[3], for
	 * inter-cpu messages
	 */
	/* Was I1 */
	__raw_writeq(IMR_IP3_VAL,
		     IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
			    (K_INT_MBOX_0 << 3)));
	__raw_writeq(IMR_IP3_VAL,
		     IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
			    (K_INT_MBOX_0 << 3)));

	/* Clear the mailboxes.	 The firmware may leave them dirty */
	__raw_writeq(0xffffffffffffffffULL,
		     IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
	__raw_writeq(0xffffffffffffffffULL,
		     IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));

	/* Mask everything except the mailbox registers for both cpus */
	tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
	__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
	__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));

	/*
	 * Note that the timer interrupts are also mapped, but this is
	 * done in sb1250_time_init().	Also, the profiling driver
	 * does its own management of IP7.
	 */

	/* Enable necessary IPs, disable the rest */
	change_c0_status(ST0_IM, imask);
}

extern void sb1250_mailbox_interrupt(void);

static inline void dispatch_ip2(void)
{
	unsigned int cpu = smp_processor_id();
	unsigned long long mask;

	/*
	 * Default...we've hit an IP[2] interrupt, which means we've got to
	 * check the 1250 interrupt registers to figure out what to do.	 Need
	 * to detect which CPU we're on, now that smp_affinity is supported.
	 */
	mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu,
				  R_IMR_INTERRUPT_STATUS_BASE)));
	if (mask)
		do_IRQ(fls64(mask) - 1);
}

asmlinkage void plat_irq_dispatch(void)
{
	unsigned int cpu = smp_processor_id();
	unsigned int pending;

	/*
	 * What a pain. We have to be really careful saving the upper 32 bits
	 * of any * register across function calls if we don't want them
	 * trashed--since were running in -o32, the calling routing never saves
	 * the full 64 bits of a register across a function call.  Being the
	 * interrupt handler, we're guaranteed that interrupts are disabled
	 * during this code so we don't have to worry about random interrupts
	 * blasting the high 32 bits.
	 */

	pending = read_c0_cause() & read_c0_status() & ST0_IM;

	if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */
		do_IRQ(MIPS_CPU_IRQ_BASE + 7);
	else if (pending & CAUSEF_IP4)
		do_IRQ(K_INT_TIMER_0 + cpu);	/* sb1250_timer_interrupt() */

#ifdef CONFIG_SMP
	else if (pending & CAUSEF_IP3)
		sb1250_mailbox_interrupt();
#endif

	else if (pending & CAUSEF_IP2)
		dispatch_ip2();
	else
		spurious_interrupt();
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version 2
	7	* of the License, or (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	17	*/
1da177e4 LT	18	#include <linux/kernel.h>
	19	#include <linux/init.h>
	20	#include <linux/linkage.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/spinlock.h>
	23	#include <linux/smp.h>
	24	#include <linux/mm.h>
1da177e4 LT	25	#include <linux/kernel_stat.h>
	26
	27	#include <asm/errno.h>
	28	#include <asm/signal.h>
7bcf7717	29	#include <asm/time.h>
1da177e4 LT	30	#include <asm/io.h>
	31
	32	#include <asm/sibyte/sb1250_regs.h>
	33	#include <asm/sibyte/sb1250_int.h>
	34	#include <asm/sibyte/sb1250_uart.h>
	35	#include <asm/sibyte/sb1250_scd.h>
	36	#include <asm/sibyte/sb1250.h>
	37
	38	/*
	39	* These are the routines that handle all the low level interrupt stuff.
	40	* Actions handled here are: initialization of the interrupt map, requesting of
	41	* interrupt lines by handlers, dispatching if interrupts to handlers, probing
	42	* for interrupt lines
	43	*/
	44
1da177e4 LT	45	#ifdef CONFIG_SIBYTE_HAS_LDT
	46	extern unsigned long ldt_eoi_space;
	47	#endif
	48
1da177e4 LT	49	/* Store the CPU id (not the logical number) */
	50	int sb1250_irq_owner[SB1250_NR_IRQS];
	51
5772f6de	52	static DEFINE_RAW_SPINLOCK(sb1250_imr_lock);
1da177e4 LT	53
	54	void sb1250_mask_irq(int cpu, int irq)
	55	{
	56	unsigned long flags;
	57	u64 cur_ints;
	58
5772f6de	59	raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
65bda1a9 MR	60	cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
65bda1a9 MR	61	R_IMR_INTERRUPT_MASK));
1da177e4	62	cur_ints \|= (((u64) 1) << irq);
65bda1a9 MR	63	____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
65bda1a9 MR	64	R_IMR_INTERRUPT_MASK));
5772f6de	65	raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
1da177e4 LT	66	}
	67
	68	void sb1250_unmask_irq(int cpu, int irq)
	69	{
	70	unsigned long flags;
	71	u64 cur_ints;
	72
5772f6de	73	raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
65bda1a9 MR	74	cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
65bda1a9 MR	75	R_IMR_INTERRUPT_MASK));
1da177e4	76	cur_ints &= ~(((u64) 1) << irq);
65bda1a9 MR	77	____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
65bda1a9 MR	78	R_IMR_INTERRUPT_MASK));
5772f6de	79	raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
1da177e4 LT	80	}
	81
	82	#ifdef CONFIG_SMP
d6d5d5c4 TG	83	static int sb1250_set_affinity(struct irq_data d, const struct cpumask mask,
d6d5d5c4 TG	84	bool force)
1da177e4 LT	85	{
1da177e4 LT	86	int i = 0, old_cpu, cpu, int_on;
d6d5d5c4	87	unsigned int irq = d->irq;
1da177e4	88	u64 cur_ints;
1da177e4 LT	89	unsigned long flags;
1da177e4 LT	90
421d1563	91	i = cpumask_first_and(mask, cpu_online_mask);
1da177e4	92
1da177e4 LT	93	/* Convert logical CPU to physical CPU */
	94	cpu = cpu_logical_map(i);
	95
	96	/* Protect against other affinity changers and IMR manipulation */
5772f6de	97	raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
1da177e4 LT	98
	99	/* Swizzle each CPU's IMR (but leave the IP selection alone) */
	100	old_cpu = sb1250_irq_owner[irq];
65bda1a9 MR	101	cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
65bda1a9 MR	102	R_IMR_INTERRUPT_MASK));
1da177e4 LT	103	int_on = !(cur_ints & (((u64) 1) << irq));
	104	if (int_on) {
	105	/* If it was on, mask it */
	106	cur_ints \|= (((u64) 1) << irq);
65bda1a9 MR	107	____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
65bda1a9 MR	108	R_IMR_INTERRUPT_MASK));
1da177e4 LT	109	}
	110	sb1250_irq_owner[irq] = cpu;
	111	if (int_on) {
	112	/* unmask for the new CPU */
65bda1a9 MR	113	cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
65bda1a9 MR	114	R_IMR_INTERRUPT_MASK));
1da177e4	115	cur_ints &= ~(((u64) 1) << irq);
65bda1a9 MR	116	____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
65bda1a9 MR	117	R_IMR_INTERRUPT_MASK));
1da177e4	118	}
5772f6de	119	raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
d5dedd45 YL	120
d5dedd45 YL	121	return 0;
1da177e4 LT	122	}
	123	#endif
	124
1544129d TG	125	static void disable_sb1250_irq(struct irq_data *d)
	126	{
	127	unsigned int irq = d->irq;
	128
	129	sb1250_mask_irq(sb1250_irq_owner[irq], irq);
	130	}
	131
d6d5d5c4	132	static void enable_sb1250_irq(struct irq_data *d)
1da177e4	133	{
d6d5d5c4	134	unsigned int irq = d->irq;
1da177e4	135
1da177e4 LT	136	sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
	137	}
	138
	139
d6d5d5c4	140	static void ack_sb1250_irq(struct irq_data *d)
1da177e4	141	{
d6d5d5c4	142	unsigned int irq = d->irq;
1da177e4 LT	143	#ifdef CONFIG_SIBYTE_HAS_LDT
	144	u64 pending;
	145
	146	/*
	147	* If the interrupt was an HT interrupt, now is the time to
	148	* clear it. NOTE: we assume the HT bridge was set up to
	149	* deliver the interrupts to all CPUs (which makes affinity
	150	* changing easier for us)
	151	*/
65bda1a9 MR	152	pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
65bda1a9 MR	153	R_IMR_LDT_INTERRUPT)));
1da177e4 LT	154	pending &= ((u64)1 << (irq));
	155	if (pending) {
	156	int i;
	157	for (i=0; i<NR_CPUS; i++) {
	158	int cpu;
	159	#ifdef CONFIG_SMP
	160	cpu = cpu_logical_map(i);
	161	#else
	162	cpu = i;
	163	#endif
	164	/*
	165	* Clear for all CPUs so an affinity switch
	166	* doesn't find an old status
	167	*/
65bda1a9 MR	168	__raw_writeq(pending,
65bda1a9 MR	169	IOADDR(A_IMR_REGISTER(cpu,
1da177e4 LT	170	R_IMR_LDT_INTERRUPT_CLR)));
	171	}
	172
	173	/*
	174	* Generate EOI. For Pass 1 parts, EOI is a nop. For
	175	* Pass 2, the LDT world may be edge-triggered, but
	176	* this EOI shouldn't hurt. If they are
	177	* level-sensitive, the EOI is required.
	178	*/
	179	(uint32_t )(ldt_eoi_space+(irq<<16)+(7<<2)) = 0;
	180	}
	181	#endif
	182	sb1250_mask_irq(sb1250_irq_owner[irq], irq);
	183	}
	184
d6d5d5c4 TG	185	static struct irq_chip sb1250_irq_type = {
	186	.name = "SB1250-IMR",
	187	.irq_mask_ack = ack_sb1250_irq,
	188	.irq_unmask = enable_sb1250_irq,
1544129d	189	.irq_mask = disable_sb1250_irq,
d6d5d5c4 TG	190	#ifdef CONFIG_SMP
	191	.irq_set_affinity = sb1250_set_affinity
	192	#endif
	193	};
1da177e4 LT	194
	195	void __init init_sb1250_irqs(void)
	196	{
	197	int i;
	198
1603b5ac	199	for (i = 0; i < SB1250_NR_IRQS; i++) {
e4ec7989 TG	200	irq_set_chip_and_handler(i, &sb1250_irq_type,
e4ec7989 TG	201	handle_level_irq);
1603b5ac	202	sb1250_irq_owner[i] = 0;
1da177e4 LT	203	}
	204	}
	205
	206
1da177e4 LT	207	/*
	208	* arch_init_irq is called early in the boot sequence from init/main.c via
	209	* init_IRQ. It is responsible for setting up the interrupt mapper and
	210	* installing the handler that will be responsible for dispatching interrupts
	211	* to the "right" place.
	212	*/
	213	/*
	214	* For now, map all interrupts to IP[2]. We could save
	215	* some cycles by parceling out system interrupts to different
	216	* IP lines, but keep it simple for bringup. We'll also direct
	217	* all interrupts to a single CPU; we should probably route
	218	* PCI and LDT to one cpu and everything else to the other
	219	* to balance the load a bit.
	220	*
	221	* On the second cpu, everything is set to IP5, which is
	222	* ignored, EXCEPT the mailbox interrupt. That one is
	223	* set to IP[2] so it is handled. This is needed so we
f77f13e2	224	* can do cross-cpu function calls, as required by SMP
1da177e4 LT	225	*/
	226
	227	#define IMR_IP2_VAL K_INT_MAP_I0
	228	#define IMR_IP3_VAL K_INT_MAP_I1
	229	#define IMR_IP4_VAL K_INT_MAP_I2
	230	#define IMR_IP5_VAL K_INT_MAP_I3
	231	#define IMR_IP6_VAL K_INT_MAP_I4
	232
	233	void __init arch_init_irq(void)
	234	{
	235
	236	unsigned int i;
	237	u64 tmp;
	238	unsigned int imask = STATUSF_IP4 \| STATUSF_IP3 \| STATUSF_IP2 \|
	239	STATUSF_IP1 \| STATUSF_IP0;
	240
	241	/* Default everything to IP2 */
	242	for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */
65bda1a9 MR	243	__raw_writeq(IMR_IP2_VAL,
	244	IOADDR(A_IMR_REGISTER(0,
	245	R_IMR_INTERRUPT_MAP_BASE) +
	246	(i << 3)));
	247	__raw_writeq(IMR_IP2_VAL,
	248	IOADDR(A_IMR_REGISTER(1,
	249	R_IMR_INTERRUPT_MAP_BASE) +
	250	(i << 3)));
1da177e4 LT	251	}
	252
	253	init_sb1250_irqs();
	254
	255	/*
	256	* Map the high 16 bits of the mailbox registers to IP[3], for
	257	* inter-cpu messages
	258	*/
	259	/* Was I1 */
65bda1a9 MR	260	__raw_writeq(IMR_IP3_VAL,
	261	IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
	262	(K_INT_MBOX_0 << 3)));
	263	__raw_writeq(IMR_IP3_VAL,
	264	IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
	265	(K_INT_MBOX_0 << 3)));
1da177e4	266
70342287	267	/* Clear the mailboxes. The firmware may leave them dirty */
65bda1a9 MR	268	__raw_writeq(0xffffffffffffffffULL,
	269	IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
	270	__raw_writeq(0xffffffffffffffffULL,
	271	IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
1da177e4 LT	272
	273	/* Mask everything except the mailbox registers for both cpus */
	274	tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
65bda1a9 MR	275	__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
65bda1a9 MR	276	__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
1da177e4	277
1da177e4 LT	278	/*
1da177e4 LT	279	* Note that the timer interrupts are also mapped, but this is
70342287	280	* done in sb1250_time_init(). Also, the profiling driver
1da177e4 LT	281	* does its own management of IP7.
	282	*/
	283
1da177e4 LT	284	/* Enable necessary IPs, disable the rest */
1da177e4 LT	285	change_c0_status(ST0_IM, imask);
1da177e4 LT	286	}
1da177e4 LT	287
937a8015	288	extern void sb1250_mailbox_interrupt(void);
4fb60a4b	289
d0453365 RB	290	static inline void dispatch_ip2(void)
	291	{
	292	unsigned int cpu = smp_processor_id();
	293	unsigned long long mask;
	294
	295	/*
	296	* Default...we've hit an IP[2] interrupt, which means we've got to
70342287	297	* check the 1250 interrupt registers to figure out what to do. Need
d0453365 RB	298	* to detect which CPU we're on, now that smp_affinity is supported.
	299	*/
	300	mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu,
	301	R_IMR_INTERRUPT_STATUS_BASE)));
	302	if (mask)
	303	do_IRQ(fls64(mask) - 1);
	304	}
	305
937a8015	306	asmlinkage void plat_irq_dispatch(void)
e4ac58af	307	{
d527eef5	308	unsigned int cpu = smp_processor_id();
e4ac58af RB	309	unsigned int pending;
e4ac58af RB	310
e4ac58af RB	311	/*
	312	* What a pain. We have to be really careful saving the upper 32 bits
	313	* of any * register across function calls if we don't want them
	314	* trashed--since were running in -o32, the calling routing never saves
	315	* the full 64 bits of a register across a function call. Being the
	316	* interrupt handler, we're guaranteed that interrupts are disabled
	317	* during this code so we don't have to worry about random interrupts
	318	* blasting the high 32 bits.
	319	*/
	320
119537c0	321	pending = read_c0_cause() & read_c0_status() & ST0_IM;
e4ac58af	322
7bcf7717 RB	323	if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */
	324	do_IRQ(MIPS_CPU_IRQ_BASE + 7);
	325	else if (pending & CAUSEF_IP4)
70342287	326	do_IRQ(K_INT_TIMER_0 + cpu); /* sb1250_timer_interrupt() */
e4ac58af RB	327
e4ac58af RB	328	#ifdef CONFIG_SMP
6e61e85b	329	else if (pending & CAUSEF_IP3)
937a8015	330	sb1250_mailbox_interrupt();
e4ac58af RB	331	#endif
e4ac58af RB	332
d0453365 RB	333	else if (pending & CAUSEF_IP2)
	334	dispatch_ip2();
	335	else
937a8015	336	spurious_interrupt();
e4ac58af	337	}