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1da177e4 LT |
1 | /* |
2 | * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version 2 | |
7 | * of the License, or (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
17 | */ | |
1da177e4 LT |
18 | #include <linux/kernel.h> |
19 | #include <linux/init.h> | |
20 | #include <linux/linkage.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/smp.h> | |
24 | #include <linux/mm.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/kernel_stat.h> | |
27 | ||
28 | #include <asm/errno.h> | |
29 | #include <asm/signal.h> | |
30 | #include <asm/system.h> | |
7bcf7717 | 31 | #include <asm/time.h> |
1da177e4 LT |
32 | #include <asm/io.h> |
33 | ||
34 | #include <asm/sibyte/sb1250_regs.h> | |
35 | #include <asm/sibyte/sb1250_int.h> | |
36 | #include <asm/sibyte/sb1250_uart.h> | |
37 | #include <asm/sibyte/sb1250_scd.h> | |
38 | #include <asm/sibyte/sb1250.h> | |
39 | ||
40 | /* | |
41 | * These are the routines that handle all the low level interrupt stuff. | |
42 | * Actions handled here are: initialization of the interrupt map, requesting of | |
43 | * interrupt lines by handlers, dispatching if interrupts to handlers, probing | |
44 | * for interrupt lines | |
45 | */ | |
46 | ||
47 | ||
1da177e4 LT |
48 | static void end_sb1250_irq(unsigned int irq); |
49 | static void enable_sb1250_irq(unsigned int irq); | |
50 | static void disable_sb1250_irq(unsigned int irq); | |
1da177e4 LT |
51 | static void ack_sb1250_irq(unsigned int irq); |
52 | #ifdef CONFIG_SMP | |
d5dedd45 | 53 | static int sb1250_set_affinity(unsigned int irq, const struct cpumask *mask); |
1da177e4 LT |
54 | #endif |
55 | ||
56 | #ifdef CONFIG_SIBYTE_HAS_LDT | |
57 | extern unsigned long ldt_eoi_space; | |
58 | #endif | |
59 | ||
94dee171 | 60 | static struct irq_chip sb1250_irq_type = { |
70d21cde | 61 | .name = "SB1250-IMR", |
8ab00b9a | 62 | .ack = ack_sb1250_irq, |
1603b5ac AN |
63 | .mask = disable_sb1250_irq, |
64 | .mask_ack = ack_sb1250_irq, | |
65 | .unmask = enable_sb1250_irq, | |
8ab00b9a | 66 | .end = end_sb1250_irq, |
1da177e4 | 67 | #ifdef CONFIG_SMP |
8ab00b9a | 68 | .set_affinity = sb1250_set_affinity |
1da177e4 LT |
69 | #endif |
70 | }; | |
71 | ||
72 | /* Store the CPU id (not the logical number) */ | |
73 | int sb1250_irq_owner[SB1250_NR_IRQS]; | |
74 | ||
75 | DEFINE_SPINLOCK(sb1250_imr_lock); | |
76 | ||
77 | void sb1250_mask_irq(int cpu, int irq) | |
78 | { | |
79 | unsigned long flags; | |
80 | u64 cur_ints; | |
81 | ||
82 | spin_lock_irqsave(&sb1250_imr_lock, flags); | |
65bda1a9 MR |
83 | cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + |
84 | R_IMR_INTERRUPT_MASK)); | |
1da177e4 | 85 | cur_ints |= (((u64) 1) << irq); |
65bda1a9 MR |
86 | ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + |
87 | R_IMR_INTERRUPT_MASK)); | |
1da177e4 LT |
88 | spin_unlock_irqrestore(&sb1250_imr_lock, flags); |
89 | } | |
90 | ||
91 | void sb1250_unmask_irq(int cpu, int irq) | |
92 | { | |
93 | unsigned long flags; | |
94 | u64 cur_ints; | |
95 | ||
96 | spin_lock_irqsave(&sb1250_imr_lock, flags); | |
65bda1a9 MR |
97 | cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + |
98 | R_IMR_INTERRUPT_MASK)); | |
1da177e4 | 99 | cur_ints &= ~(((u64) 1) << irq); |
65bda1a9 MR |
100 | ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + |
101 | R_IMR_INTERRUPT_MASK)); | |
1da177e4 LT |
102 | spin_unlock_irqrestore(&sb1250_imr_lock, flags); |
103 | } | |
104 | ||
105 | #ifdef CONFIG_SMP | |
d5dedd45 | 106 | static int sb1250_set_affinity(unsigned int irq, const struct cpumask *mask) |
1da177e4 LT |
107 | { |
108 | int i = 0, old_cpu, cpu, int_on; | |
109 | u64 cur_ints; | |
94dee171 | 110 | struct irq_desc *desc = irq_desc + irq; |
1da177e4 LT |
111 | unsigned long flags; |
112 | ||
0de26520 | 113 | i = cpumask_first(mask); |
1da177e4 | 114 | |
0de26520 | 115 | if (cpumask_weight(mask) > 1) { |
1da177e4 | 116 | printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq); |
d5dedd45 | 117 | return -1; |
1da177e4 LT |
118 | } |
119 | ||
120 | /* Convert logical CPU to physical CPU */ | |
121 | cpu = cpu_logical_map(i); | |
122 | ||
123 | /* Protect against other affinity changers and IMR manipulation */ | |
124 | spin_lock_irqsave(&desc->lock, flags); | |
125 | spin_lock(&sb1250_imr_lock); | |
126 | ||
127 | /* Swizzle each CPU's IMR (but leave the IP selection alone) */ | |
128 | old_cpu = sb1250_irq_owner[irq]; | |
65bda1a9 MR |
129 | cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) + |
130 | R_IMR_INTERRUPT_MASK)); | |
1da177e4 LT |
131 | int_on = !(cur_ints & (((u64) 1) << irq)); |
132 | if (int_on) { | |
133 | /* If it was on, mask it */ | |
134 | cur_ints |= (((u64) 1) << irq); | |
65bda1a9 MR |
135 | ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) + |
136 | R_IMR_INTERRUPT_MASK)); | |
1da177e4 LT |
137 | } |
138 | sb1250_irq_owner[irq] = cpu; | |
139 | if (int_on) { | |
140 | /* unmask for the new CPU */ | |
65bda1a9 MR |
141 | cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + |
142 | R_IMR_INTERRUPT_MASK)); | |
1da177e4 | 143 | cur_ints &= ~(((u64) 1) << irq); |
65bda1a9 MR |
144 | ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + |
145 | R_IMR_INTERRUPT_MASK)); | |
1da177e4 LT |
146 | } |
147 | spin_unlock(&sb1250_imr_lock); | |
148 | spin_unlock_irqrestore(&desc->lock, flags); | |
d5dedd45 YL |
149 | |
150 | return 0; | |
1da177e4 LT |
151 | } |
152 | #endif | |
153 | ||
1da177e4 LT |
154 | /*****************************************************************************/ |
155 | ||
1da177e4 LT |
156 | static void disable_sb1250_irq(unsigned int irq) |
157 | { | |
158 | sb1250_mask_irq(sb1250_irq_owner[irq], irq); | |
159 | } | |
160 | ||
161 | static void enable_sb1250_irq(unsigned int irq) | |
162 | { | |
163 | sb1250_unmask_irq(sb1250_irq_owner[irq], irq); | |
164 | } | |
165 | ||
166 | ||
167 | static void ack_sb1250_irq(unsigned int irq) | |
168 | { | |
169 | #ifdef CONFIG_SIBYTE_HAS_LDT | |
170 | u64 pending; | |
171 | ||
172 | /* | |
173 | * If the interrupt was an HT interrupt, now is the time to | |
174 | * clear it. NOTE: we assume the HT bridge was set up to | |
175 | * deliver the interrupts to all CPUs (which makes affinity | |
176 | * changing easier for us) | |
177 | */ | |
65bda1a9 MR |
178 | pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq], |
179 | R_IMR_LDT_INTERRUPT))); | |
1da177e4 LT |
180 | pending &= ((u64)1 << (irq)); |
181 | if (pending) { | |
182 | int i; | |
183 | for (i=0; i<NR_CPUS; i++) { | |
184 | int cpu; | |
185 | #ifdef CONFIG_SMP | |
186 | cpu = cpu_logical_map(i); | |
187 | #else | |
188 | cpu = i; | |
189 | #endif | |
190 | /* | |
191 | * Clear for all CPUs so an affinity switch | |
192 | * doesn't find an old status | |
193 | */ | |
65bda1a9 MR |
194 | __raw_writeq(pending, |
195 | IOADDR(A_IMR_REGISTER(cpu, | |
1da177e4 LT |
196 | R_IMR_LDT_INTERRUPT_CLR))); |
197 | } | |
198 | ||
199 | /* | |
200 | * Generate EOI. For Pass 1 parts, EOI is a nop. For | |
201 | * Pass 2, the LDT world may be edge-triggered, but | |
202 | * this EOI shouldn't hurt. If they are | |
203 | * level-sensitive, the EOI is required. | |
204 | */ | |
205 | *(uint32_t *)(ldt_eoi_space+(irq<<16)+(7<<2)) = 0; | |
206 | } | |
207 | #endif | |
208 | sb1250_mask_irq(sb1250_irq_owner[irq], irq); | |
209 | } | |
210 | ||
211 | ||
212 | static void end_sb1250_irq(unsigned int irq) | |
213 | { | |
214 | if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { | |
215 | sb1250_unmask_irq(sb1250_irq_owner[irq], irq); | |
216 | } | |
217 | } | |
218 | ||
219 | ||
220 | void __init init_sb1250_irqs(void) | |
221 | { | |
222 | int i; | |
223 | ||
1603b5ac | 224 | for (i = 0; i < SB1250_NR_IRQS; i++) { |
c87e0909 | 225 | set_irq_chip_and_handler(i, &sb1250_irq_type, handle_level_irq); |
1603b5ac | 226 | sb1250_irq_owner[i] = 0; |
1da177e4 LT |
227 | } |
228 | } | |
229 | ||
230 | ||
1da177e4 LT |
231 | /* |
232 | * arch_init_irq is called early in the boot sequence from init/main.c via | |
233 | * init_IRQ. It is responsible for setting up the interrupt mapper and | |
234 | * installing the handler that will be responsible for dispatching interrupts | |
235 | * to the "right" place. | |
236 | */ | |
237 | /* | |
238 | * For now, map all interrupts to IP[2]. We could save | |
239 | * some cycles by parceling out system interrupts to different | |
240 | * IP lines, but keep it simple for bringup. We'll also direct | |
241 | * all interrupts to a single CPU; we should probably route | |
242 | * PCI and LDT to one cpu and everything else to the other | |
243 | * to balance the load a bit. | |
244 | * | |
245 | * On the second cpu, everything is set to IP5, which is | |
246 | * ignored, EXCEPT the mailbox interrupt. That one is | |
247 | * set to IP[2] so it is handled. This is needed so we | |
248 | * can do cross-cpu function calls, as requred by SMP | |
249 | */ | |
250 | ||
251 | #define IMR_IP2_VAL K_INT_MAP_I0 | |
252 | #define IMR_IP3_VAL K_INT_MAP_I1 | |
253 | #define IMR_IP4_VAL K_INT_MAP_I2 | |
254 | #define IMR_IP5_VAL K_INT_MAP_I3 | |
255 | #define IMR_IP6_VAL K_INT_MAP_I4 | |
256 | ||
257 | void __init arch_init_irq(void) | |
258 | { | |
259 | ||
260 | unsigned int i; | |
261 | u64 tmp; | |
262 | unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 | | |
263 | STATUSF_IP1 | STATUSF_IP0; | |
264 | ||
265 | /* Default everything to IP2 */ | |
266 | for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */ | |
65bda1a9 MR |
267 | __raw_writeq(IMR_IP2_VAL, |
268 | IOADDR(A_IMR_REGISTER(0, | |
269 | R_IMR_INTERRUPT_MAP_BASE) + | |
270 | (i << 3))); | |
271 | __raw_writeq(IMR_IP2_VAL, | |
272 | IOADDR(A_IMR_REGISTER(1, | |
273 | R_IMR_INTERRUPT_MAP_BASE) + | |
274 | (i << 3))); | |
1da177e4 LT |
275 | } |
276 | ||
277 | init_sb1250_irqs(); | |
278 | ||
279 | /* | |
280 | * Map the high 16 bits of the mailbox registers to IP[3], for | |
281 | * inter-cpu messages | |
282 | */ | |
283 | /* Was I1 */ | |
65bda1a9 MR |
284 | __raw_writeq(IMR_IP3_VAL, |
285 | IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + | |
286 | (K_INT_MBOX_0 << 3))); | |
287 | __raw_writeq(IMR_IP3_VAL, | |
288 | IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) + | |
289 | (K_INT_MBOX_0 << 3))); | |
1da177e4 LT |
290 | |
291 | /* Clear the mailboxes. The firmware may leave them dirty */ | |
65bda1a9 MR |
292 | __raw_writeq(0xffffffffffffffffULL, |
293 | IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU))); | |
294 | __raw_writeq(0xffffffffffffffffULL, | |
295 | IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU))); | |
1da177e4 LT |
296 | |
297 | /* Mask everything except the mailbox registers for both cpus */ | |
298 | tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0); | |
65bda1a9 MR |
299 | __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK))); |
300 | __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK))); | |
1da177e4 | 301 | |
1da177e4 LT |
302 | /* |
303 | * Note that the timer interrupts are also mapped, but this is | |
42a3b4f2 | 304 | * done in sb1250_time_init(). Also, the profiling driver |
1da177e4 LT |
305 | * does its own management of IP7. |
306 | */ | |
307 | ||
1da177e4 LT |
308 | /* Enable necessary IPs, disable the rest */ |
309 | change_c0_status(ST0_IM, imask); | |
1da177e4 LT |
310 | } |
311 | ||
937a8015 | 312 | extern void sb1250_mailbox_interrupt(void); |
4fb60a4b | 313 | |
d0453365 RB |
314 | static inline void dispatch_ip2(void) |
315 | { | |
316 | unsigned int cpu = smp_processor_id(); | |
317 | unsigned long long mask; | |
318 | ||
319 | /* | |
320 | * Default...we've hit an IP[2] interrupt, which means we've got to | |
321 | * check the 1250 interrupt registers to figure out what to do. Need | |
322 | * to detect which CPU we're on, now that smp_affinity is supported. | |
323 | */ | |
324 | mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu, | |
325 | R_IMR_INTERRUPT_STATUS_BASE))); | |
326 | if (mask) | |
327 | do_IRQ(fls64(mask) - 1); | |
328 | } | |
329 | ||
937a8015 | 330 | asmlinkage void plat_irq_dispatch(void) |
e4ac58af | 331 | { |
d527eef5 | 332 | unsigned int cpu = smp_processor_id(); |
e4ac58af RB |
333 | unsigned int pending; |
334 | ||
e4ac58af RB |
335 | /* |
336 | * What a pain. We have to be really careful saving the upper 32 bits | |
337 | * of any * register across function calls if we don't want them | |
338 | * trashed--since were running in -o32, the calling routing never saves | |
339 | * the full 64 bits of a register across a function call. Being the | |
340 | * interrupt handler, we're guaranteed that interrupts are disabled | |
341 | * during this code so we don't have to worry about random interrupts | |
342 | * blasting the high 32 bits. | |
343 | */ | |
344 | ||
119537c0 | 345 | pending = read_c0_cause() & read_c0_status() & ST0_IM; |
e4ac58af | 346 | |
7bcf7717 RB |
347 | if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */ |
348 | do_IRQ(MIPS_CPU_IRQ_BASE + 7); | |
349 | else if (pending & CAUSEF_IP4) | |
d527eef5 | 350 | do_IRQ(K_INT_TIMER_0 + cpu); /* sb1250_timer_interrupt() */ |
e4ac58af RB |
351 | |
352 | #ifdef CONFIG_SMP | |
6e61e85b | 353 | else if (pending & CAUSEF_IP3) |
937a8015 | 354 | sb1250_mailbox_interrupt(); |
e4ac58af RB |
355 | #endif |
356 | ||
d0453365 RB |
357 | else if (pending & CAUSEF_IP2) |
358 | dispatch_ip2(); | |
359 | else | |
937a8015 | 360 | spurious_interrupt(); |
e4ac58af | 361 | } |