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1da177e4 LT |
1 | /* |
2 | * Copyright (C) 2001, 2002, 2003 Broadcom Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version 2 | |
7 | * of the License, or (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
17 | */ | |
18 | ||
19 | #include <linux/init.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/smp.h> | |
23 | #include <linux/kernel_stat.h> | |
24 | ||
25 | #include <asm/mmu_context.h> | |
26 | #include <asm/io.h> | |
87353d8a | 27 | #include <asm/fw/cfe/cfe_api.h> |
1da177e4 LT |
28 | #include <asm/sibyte/sb1250.h> |
29 | #include <asm/sibyte/sb1250_regs.h> | |
30 | #include <asm/sibyte/sb1250_int.h> | |
31 | ||
32 | static void *mailbox_set_regs[] = { | |
65bda1a9 MR |
33 | IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_SET_CPU), |
34 | IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU) | |
1da177e4 LT |
35 | }; |
36 | ||
37 | static void *mailbox_clear_regs[] = { | |
65bda1a9 MR |
38 | IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU), |
39 | IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU) | |
1da177e4 LT |
40 | }; |
41 | ||
42 | static void *mailbox_regs[] = { | |
65bda1a9 MR |
43 | IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU), |
44 | IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU) | |
1da177e4 LT |
45 | }; |
46 | ||
47 | /* | |
48 | * SMP init and finish on secondary CPUs | |
49 | */ | |
d0453365 | 50 | void __cpuinit sb1250_smp_init(void) |
1da177e4 LT |
51 | { |
52 | unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 | | |
53 | STATUSF_IP1 | STATUSF_IP0; | |
54 | ||
55 | /* Set interrupt mask, but don't enable */ | |
56 | change_c0_status(ST0_IM, imask); | |
57 | } | |
58 | ||
87353d8a RB |
59 | /* |
60 | * These are routines for dealing with the sb1250 smp capabilities | |
61 | * independent of board/firmware | |
62 | */ | |
63 | ||
64 | /* | |
65 | * Simple enough; everything is set up, so just poke the appropriate mailbox | |
66 | * register, and we should be set | |
67 | */ | |
68 | static void sb1250_send_ipi_single(int cpu, unsigned int action) | |
69 | { | |
70 | __raw_writeq((((u64)action) << 48), mailbox_set_regs[cpu]); | |
71 | } | |
72 | ||
73 | static inline void sb1250_send_ipi_mask(cpumask_t mask, unsigned int action) | |
74 | { | |
75 | unsigned int i; | |
76 | ||
77 | for_each_cpu_mask(i, mask) | |
78 | sb1250_send_ipi_single(i, action); | |
79 | } | |
80 | ||
81 | /* | |
82 | * Code to run on secondary just after probing the CPU | |
83 | */ | |
84 | static void __cpuinit sb1250_init_secondary(void) | |
85 | { | |
86 | extern void sb1250_smp_init(void); | |
87 | ||
88 | sb1250_smp_init(); | |
89 | } | |
90 | ||
91 | /* | |
92 | * Do any tidying up before marking online and running the idle | |
93 | * loop | |
94 | */ | |
95 | static void __cpuinit sb1250_smp_finish(void) | |
1da177e4 | 96 | { |
d527eef5 RB |
97 | extern void sb1250_clockevent_init(void); |
98 | ||
99 | sb1250_clockevent_init(); | |
1da177e4 LT |
100 | local_irq_enable(); |
101 | } | |
102 | ||
103 | /* | |
87353d8a | 104 | * Final cleanup after all secondaries booted |
1da177e4 | 105 | */ |
87353d8a RB |
106 | static void sb1250_cpus_done(void) |
107 | { | |
108 | } | |
1da177e4 LT |
109 | |
110 | /* | |
87353d8a RB |
111 | * Setup the PC, SP, and GP of a secondary processor and start it |
112 | * running! | |
1da177e4 | 113 | */ |
87353d8a | 114 | static void __cpuinit sb1250_boot_secondary(int cpu, struct task_struct *idle) |
1da177e4 | 115 | { |
87353d8a RB |
116 | int retval; |
117 | ||
118 | retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap, | |
119 | __KSTK_TOS(idle), | |
120 | (unsigned long)task_thread_info(idle), 0); | |
121 | if (retval != 0) | |
122 | printk("cfe_start_cpu(%i) returned %i\n" , cpu, retval); | |
1da177e4 LT |
123 | } |
124 | ||
87353d8a RB |
125 | /* |
126 | * Use CFE to find out how many CPUs are available, setting up | |
98a79d6a | 127 | * cpu_possible_map and the logical/physical mappings. |
87353d8a RB |
128 | * XXXKW will the boot CPU ever not be physical 0? |
129 | * | |
130 | * Common setup before any secondaries are started | |
131 | */ | |
132 | static void __init sb1250_smp_setup(void) | |
133 | { | |
134 | int i, num; | |
135 | ||
98a79d6a RR |
136 | cpus_clear(cpu_possible_map); |
137 | cpu_set(0, cpu_possible_map); | |
87353d8a RB |
138 | __cpu_number_map[0] = 0; |
139 | __cpu_logical_map[0] = 0; | |
140 | ||
141 | for (i = 1, num = 0; i < NR_CPUS; i++) { | |
142 | if (cfe_cpu_stop(i) == 0) { | |
98a79d6a | 143 | cpu_set(i, cpu_possible_map); |
87353d8a RB |
144 | __cpu_number_map[i] = ++num; |
145 | __cpu_logical_map[num] = i; | |
146 | } | |
147 | } | |
148 | printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num); | |
149 | } | |
150 | ||
151 | static void __init sb1250_prepare_cpus(unsigned int max_cpus) | |
152 | { | |
153 | } | |
154 | ||
155 | struct plat_smp_ops sb_smp_ops = { | |
156 | .send_ipi_single = sb1250_send_ipi_single, | |
157 | .send_ipi_mask = sb1250_send_ipi_mask, | |
158 | .init_secondary = sb1250_init_secondary, | |
159 | .smp_finish = sb1250_smp_finish, | |
160 | .cpus_done = sb1250_cpus_done, | |
161 | .boot_secondary = sb1250_boot_secondary, | |
162 | .smp_setup = sb1250_smp_setup, | |
163 | .prepare_cpus = sb1250_prepare_cpus, | |
164 | }; | |
165 | ||
937a8015 | 166 | void sb1250_mailbox_interrupt(void) |
1da177e4 LT |
167 | { |
168 | int cpu = smp_processor_id(); | |
169 | unsigned int action; | |
170 | ||
171 | kstat_this_cpu.irqs[K_INT_MBOX_0]++; | |
172 | /* Load the mailbox register to figure out what we're supposed to do */ | |
65bda1a9 | 173 | action = (____raw_readq(mailbox_regs[cpu]) >> 48) & 0xffff; |
1da177e4 LT |
174 | |
175 | /* Clear the mailbox to clear the interrupt */ | |
65bda1a9 | 176 | ____raw_writeq(((u64)action) << 48, mailbox_clear_regs[cpu]); |
1da177e4 LT |
177 | |
178 | /* | |
179 | * Nothing to do for SMP_RESCHEDULE_YOURSELF; returning from the | |
180 | * interrupt will do the reschedule for us | |
181 | */ | |
182 | ||
183 | if (action & SMP_CALL_FUNCTION) | |
184 | smp_call_function_interrupt(); | |
185 | } |