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c066a32a TB |
1 | /* |
2 | * PCI Tower specific code | |
3 | * | |
4 | * This file is subject to the terms and conditions of the GNU General Public | |
5 | * License. See the file "COPYING" in the main directory of this archive | |
6 | * for more details. | |
7 | * | |
8 | * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de) | |
9 | */ | |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/interrupt.h> | |
ca4d3e67 | 13 | #include <linux/irq.h> |
c066a32a TB |
14 | #include <linux/pci.h> |
15 | #include <linux/serial_8250.h> | |
16 | ||
c066a32a TB |
17 | #include <asm/sni.h> |
18 | #include <asm/time.h> | |
19 | #include <asm/irq_cpu.h> | |
20 | ||
21 | ||
22 | #define PORT(_base,_irq) \ | |
23 | { \ | |
24 | .iobase = _base, \ | |
25 | .irq = _irq, \ | |
26 | .uartclk = 1843200, \ | |
27 | .iotype = UPIO_PORT, \ | |
28 | .flags = UPF_BOOT_AUTOCONF, \ | |
29 | } | |
30 | ||
31 | static struct plat_serial8250_port pcit_data[] = { | |
32 | PORT(0x3f8, 0), | |
33 | PORT(0x2f8, 3), | |
34 | { }, | |
35 | }; | |
36 | ||
37 | static struct platform_device pcit_serial8250_device = { | |
38 | .name = "serial8250", | |
39 | .id = PLAT8250_DEV_PLATFORM, | |
40 | .dev = { | |
41 | .platform_data = pcit_data, | |
42 | }, | |
43 | }; | |
44 | ||
45 | static struct plat_serial8250_port pcit_cplus_data[] = { | |
bea77175 | 46 | PORT(0x3f8, 0), |
c066a32a TB |
47 | PORT(0x2f8, 3), |
48 | PORT(0x3e8, 4), | |
49 | PORT(0x2e8, 3), | |
50 | { }, | |
51 | }; | |
52 | ||
53 | static struct platform_device pcit_cplus_serial8250_device = { | |
54 | .name = "serial8250", | |
55 | .id = PLAT8250_DEV_PLATFORM, | |
56 | .dev = { | |
57 | .platform_data = pcit_cplus_data, | |
58 | }, | |
59 | }; | |
60 | ||
06cf5583 | 61 | static struct resource pcit_cmos_rsrc[] = { |
70342287 RB |
62 | { |
63 | .start = 0x70, | |
64 | .end = 0x71, | |
65 | .flags = IORESOURCE_IO | |
66 | }, | |
67 | { | |
68 | .start = 8, | |
69 | .end = 8, | |
70 | .flags = IORESOURCE_IRQ | |
71 | } | |
06cf5583 TB |
72 | }; |
73 | ||
74 | static struct platform_device pcit_cmos_device = { | |
70342287 RB |
75 | .name = "rtc_cmos", |
76 | .num_resources = ARRAY_SIZE(pcit_cmos_rsrc), | |
77 | .resource = pcit_cmos_rsrc | |
06cf5583 TB |
78 | }; |
79 | ||
19388fb0 RB |
80 | static struct platform_device pcit_pcspeaker_pdev = { |
81 | .name = "pcspkr", | |
82 | .id = -1, | |
83 | }; | |
84 | ||
c066a32a | 85 | static struct resource sni_io_resource = { |
bea77175 | 86 | .start = 0x00000000UL, |
c066a32a | 87 | .end = 0x03bfffffUL, |
bea77175 | 88 | .name = "PCIT IO", |
c066a32a TB |
89 | .flags = IORESOURCE_IO, |
90 | }; | |
91 | ||
92 | static struct resource pcit_io_resources[] = { | |
93 | { | |
94 | .start = 0x00, | |
95 | .end = 0x1f, | |
96 | .name = "dma1", | |
97 | .flags = IORESOURCE_BUSY | |
98 | }, { | |
99 | .start = 0x40, | |
100 | .end = 0x5f, | |
101 | .name = "timer", | |
102 | .flags = IORESOURCE_BUSY | |
103 | }, { | |
104 | .start = 0x60, | |
105 | .end = 0x6f, | |
106 | .name = "keyboard", | |
107 | .flags = IORESOURCE_BUSY | |
108 | }, { | |
109 | .start = 0x80, | |
110 | .end = 0x8f, | |
111 | .name = "dma page reg", | |
112 | .flags = IORESOURCE_BUSY | |
113 | }, { | |
114 | .start = 0xc0, | |
115 | .end = 0xdf, | |
116 | .name = "dma2", | |
117 | .flags = IORESOURCE_BUSY | |
bea77175 TB |
118 | }, { |
119 | .start = 0xcf8, | |
120 | .end = 0xcfb, | |
121 | .name = "PCI config addr", | |
122 | .flags = IORESOURCE_BUSY | |
c066a32a TB |
123 | }, { |
124 | .start = 0xcfc, | |
125 | .end = 0xcff, | |
126 | .name = "PCI config data", | |
127 | .flags = IORESOURCE_BUSY | |
128 | } | |
129 | }; | |
130 | ||
c066a32a TB |
131 | static void __init sni_pcit_resource_init(void) |
132 | { | |
133 | int i; | |
134 | ||
135 | /* request I/O space for devices used on all i[345]86 PCs */ | |
136 | for (i = 0; i < ARRAY_SIZE(pcit_io_resources); i++) | |
bea77175 | 137 | request_resource(&sni_io_resource, pcit_io_resources + i); |
c066a32a TB |
138 | } |
139 | ||
140 | ||
141 | extern struct pci_ops sni_pcit_ops; | |
142 | ||
6a72015d RB |
143 | #ifdef CONFIG_PCI |
144 | static struct resource sni_mem_resource = { | |
145 | .start = 0x18000000UL, | |
146 | .end = 0x1fbfffffUL, | |
147 | .name = "PCIT PCI MEM", | |
148 | .flags = IORESOURCE_MEM | |
149 | }; | |
150 | ||
c066a32a TB |
151 | static struct pci_controller sni_pcit_controller = { |
152 | .pci_ops = &sni_pcit_ops, | |
153 | .mem_resource = &sni_mem_resource, | |
bea77175 | 154 | .mem_offset = 0x00000000UL, |
c066a32a | 155 | .io_resource = &sni_io_resource, |
bea77175 | 156 | .io_offset = 0x00000000UL, |
70342287 | 157 | .io_map_base = SNI_PORT_BASE |
c066a32a | 158 | }; |
6a72015d | 159 | #endif /* CONFIG_PCI */ |
c066a32a | 160 | |
0b888c7f | 161 | static void enable_pcit_irq(struct irq_data *d) |
c066a32a | 162 | { |
0b888c7f | 163 | u32 mask = 1 << (d->irq - SNI_PCIT_INT_START + 24); |
c066a32a TB |
164 | |
165 | *(volatile u32 *)SNI_PCIT_INT_REG |= mask; | |
166 | } | |
167 | ||
0b888c7f | 168 | void disable_pcit_irq(struct irq_data *d) |
c066a32a | 169 | { |
0b888c7f | 170 | u32 mask = 1 << (d->irq - SNI_PCIT_INT_START + 24); |
c066a32a TB |
171 | |
172 | *(volatile u32 *)SNI_PCIT_INT_REG &= ~mask; | |
173 | } | |
174 | ||
c066a32a | 175 | static struct irq_chip pcit_irq_type = { |
8922f79e | 176 | .name = "PCIT", |
0b888c7f TG |
177 | .irq_mask = disable_pcit_irq, |
178 | .irq_unmask = enable_pcit_irq, | |
c066a32a TB |
179 | }; |
180 | ||
181 | static void pcit_hwint1(void) | |
182 | { | |
183 | u32 pending = *(volatile u32 *)SNI_PCIT_INT_REG; | |
184 | int irq; | |
185 | ||
186 | clear_c0_status(IE_IRQ1); | |
187 | irq = ffs((pending >> 16) & 0x7f); | |
188 | ||
189 | if (likely(irq > 0)) | |
49a89efb RB |
190 | do_IRQ(irq + SNI_PCIT_INT_START - 1); |
191 | set_c0_status(IE_IRQ1); | |
c066a32a TB |
192 | } |
193 | ||
194 | static void pcit_hwint0(void) | |
195 | { | |
196 | u32 pending = *(volatile u32 *)SNI_PCIT_INT_REG; | |
197 | int irq; | |
198 | ||
199 | clear_c0_status(IE_IRQ0); | |
bea77175 | 200 | irq = ffs((pending >> 16) & 0x3f); |
c066a32a TB |
201 | |
202 | if (likely(irq > 0)) | |
49a89efb RB |
203 | do_IRQ(irq + SNI_PCIT_INT_START - 1); |
204 | set_c0_status(IE_IRQ0); | |
c066a32a TB |
205 | } |
206 | ||
207 | static void sni_pcit_hwint(void) | |
208 | { | |
119537c0 | 209 | u32 pending = read_c0_cause() & read_c0_status(); |
c066a32a TB |
210 | |
211 | if (pending & C_IRQ1) | |
212 | pcit_hwint1(); | |
213 | else if (pending & C_IRQ2) | |
49a89efb | 214 | do_IRQ(MIPS_CPU_IRQ_BASE + 4); |
c066a32a | 215 | else if (pending & C_IRQ3) |
49a89efb | 216 | do_IRQ(MIPS_CPU_IRQ_BASE + 5); |
c066a32a | 217 | else if (pending & C_IRQ5) |
49a89efb | 218 | do_IRQ(MIPS_CPU_IRQ_BASE + 7); |
c066a32a TB |
219 | } |
220 | ||
221 | static void sni_pcit_hwint_cplus(void) | |
222 | { | |
119537c0 | 223 | u32 pending = read_c0_cause() & read_c0_status(); |
c066a32a TB |
224 | |
225 | if (pending & C_IRQ0) | |
226 | pcit_hwint0(); | |
bea77175 | 227 | else if (pending & C_IRQ1) |
49a89efb | 228 | do_IRQ(MIPS_CPU_IRQ_BASE + 3); |
c066a32a | 229 | else if (pending & C_IRQ2) |
49a89efb | 230 | do_IRQ(MIPS_CPU_IRQ_BASE + 4); |
c066a32a | 231 | else if (pending & C_IRQ3) |
49a89efb | 232 | do_IRQ(MIPS_CPU_IRQ_BASE + 5); |
c066a32a | 233 | else if (pending & C_IRQ5) |
49a89efb | 234 | do_IRQ(MIPS_CPU_IRQ_BASE + 7); |
c066a32a TB |
235 | } |
236 | ||
237 | void __init sni_pcit_irq_init(void) | |
238 | { | |
239 | int i; | |
240 | ||
241 | mips_cpu_irq_init(); | |
242 | for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++) | |
e4ec7989 | 243 | irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq); |
c066a32a TB |
244 | *(volatile u32 *)SNI_PCIT_INT_REG = 0; |
245 | sni_hwint = sni_pcit_hwint; | |
246 | change_c0_status(ST0_IM, IE_IRQ1); | |
49a89efb | 247 | setup_irq(SNI_PCIT_INT_START + 6, &sni_isa_irq); |
c066a32a TB |
248 | } |
249 | ||
250 | void __init sni_pcit_cplus_irq_init(void) | |
251 | { | |
252 | int i; | |
253 | ||
254 | mips_cpu_irq_init(); | |
255 | for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++) | |
e4ec7989 | 256 | irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq); |
bea77175 | 257 | *(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000; |
c066a32a TB |
258 | sni_hwint = sni_pcit_hwint_cplus; |
259 | change_c0_status(ST0_IM, IE_IRQ0); | |
49a89efb | 260 | setup_irq(MIPS_CPU_IRQ_BASE + 3, &sni_isa_irq); |
c066a32a TB |
261 | } |
262 | ||
06cf5583 | 263 | void __init sni_pcit_init(void) |
c066a32a | 264 | { |
bea77175 | 265 | ioport_resource.end = sni_io_resource.end; |
c066a32a | 266 | #ifdef CONFIG_PCI |
bea77175 | 267 | PCIBIOS_MIN_IO = 0x9000; |
c066a32a TB |
268 | register_pci_controller(&sni_pcit_controller); |
269 | #endif | |
bea77175 | 270 | sni_pcit_resource_init(); |
c066a32a TB |
271 | } |
272 | ||
273 | static int __init snirm_pcit_setup_devinit(void) | |
274 | { | |
275 | switch (sni_brd_type) { | |
276 | case SNI_BRD_PCI_TOWER: | |
70342287 RB |
277 | platform_device_register(&pcit_serial8250_device); |
278 | platform_device_register(&pcit_cmos_device); | |
19388fb0 | 279 | platform_device_register(&pcit_pcspeaker_pdev); |
70342287 | 280 | break; |
c066a32a TB |
281 | |
282 | case SNI_BRD_PCI_TOWER_CPLUS: | |
70342287 RB |
283 | platform_device_register(&pcit_cplus_serial8250_device); |
284 | platform_device_register(&pcit_cmos_device); | |
19388fb0 | 285 | platform_device_register(&pcit_pcspeaker_pdev); |
70342287 | 286 | break; |
c066a32a TB |
287 | } |
288 | return 0; | |
289 | } | |
290 | ||
291 | device_initcall(snirm_pcit_setup_devinit); |