Commit | Line | Data |
---|---|---|
c066a32a TB |
1 | /* |
2 | * RM200 specific code | |
3 | * | |
4 | * This file is subject to the terms and conditions of the GNU General Public | |
5 | * License. See the file "COPYING" in the main directory of this archive | |
6 | * for more details. | |
7 | * | |
231a35d3 TB |
8 | * Copyright (C) 2006,2007 Thomas Bogendoerfer (tsbogend@alpha.franken.de) |
9 | * | |
10 | * i8259 parts ripped out of arch/mips/kernel/i8259.c | |
c066a32a TB |
11 | */ |
12 | ||
231a35d3 | 13 | #include <linux/delay.h> |
c066a32a TB |
14 | #include <linux/init.h> |
15 | #include <linux/interrupt.h> | |
ca4d3e67 | 16 | #include <linux/irq.h> |
c066a32a TB |
17 | #include <linux/platform_device.h> |
18 | #include <linux/serial_8250.h> | |
231a35d3 | 19 | #include <linux/io.h> |
c066a32a TB |
20 | |
21 | #include <asm/sni.h> | |
22 | #include <asm/time.h> | |
c066a32a TB |
23 | #include <asm/irq_cpu.h> |
24 | ||
231a35d3 TB |
25 | #define RM200_I8259A_IRQ_BASE 32 |
26 | ||
27 | #define MEMPORT(_base,_irq) \ | |
c066a32a | 28 | { \ |
231a35d3 | 29 | .mapbase = _base, \ |
c066a32a TB |
30 | .irq = _irq, \ |
31 | .uartclk = 1843200, \ | |
231a35d3 TB |
32 | .iotype = UPIO_MEM, \ |
33 | .flags = UPF_BOOT_AUTOCONF|UPF_IOREMAP, \ | |
c066a32a TB |
34 | } |
35 | ||
36 | static struct plat_serial8250_port rm200_data[] = { | |
231a35d3 TB |
37 | MEMPORT(0x160003f8, RM200_I8259A_IRQ_BASE + 4), |
38 | MEMPORT(0x160002f8, RM200_I8259A_IRQ_BASE + 3), | |
c066a32a TB |
39 | { }, |
40 | }; | |
41 | ||
42 | static struct platform_device rm200_serial8250_device = { | |
43 | .name = "serial8250", | |
44 | .id = PLAT8250_DEV_PLATFORM, | |
45 | .dev = { | |
46 | .platform_data = rm200_data, | |
47 | }, | |
48 | }; | |
49 | ||
06cf5583 | 50 | static struct resource rm200_ds1216_rsrc[] = { |
70342287 RB |
51 | { |
52 | .start = 0x1cd41ffc, | |
53 | .end = 0x1cd41fff, | |
54 | .flags = IORESOURCE_MEM | |
55 | } | |
06cf5583 TB |
56 | }; |
57 | ||
58 | static struct platform_device rm200_ds1216_device = { | |
70342287 RB |
59 | .name = "rtc-ds1216", |
60 | .num_resources = ARRAY_SIZE(rm200_ds1216_rsrc), | |
61 | .resource = rm200_ds1216_rsrc | |
06cf5583 TB |
62 | }; |
63 | ||
c066a32a TB |
64 | static struct resource snirm_82596_rm200_rsrc[] = { |
65 | { | |
06cf5583 TB |
66 | .start = 0x18000000, |
67 | .end = 0x180fffff, | |
c066a32a TB |
68 | .flags = IORESOURCE_MEM |
69 | }, | |
70 | { | |
06cf5583 TB |
71 | .start = 0x1b000000, |
72 | .end = 0x1b000004, | |
c066a32a TB |
73 | .flags = IORESOURCE_MEM |
74 | }, | |
75 | { | |
06cf5583 TB |
76 | .start = 0x1ff00000, |
77 | .end = 0x1ff00020, | |
c066a32a TB |
78 | .flags = IORESOURCE_MEM |
79 | }, | |
80 | { | |
81 | .start = 27, | |
82 | .end = 27, | |
83 | .flags = IORESOURCE_IRQ | |
84 | }, | |
85 | { | |
86 | .flags = 0x00 | |
87 | } | |
88 | }; | |
89 | ||
90 | static struct platform_device snirm_82596_rm200_pdev = { | |
70342287 RB |
91 | .name = "snirm_82596", |
92 | .num_resources = ARRAY_SIZE(snirm_82596_rm200_rsrc), | |
93 | .resource = snirm_82596_rm200_rsrc | |
c066a32a TB |
94 | }; |
95 | ||
96 | static struct resource snirm_53c710_rm200_rsrc[] = { | |
97 | { | |
9815778a TB |
98 | .start = 0x19000000, |
99 | .end = 0x190fffff, | |
c066a32a TB |
100 | .flags = IORESOURCE_MEM |
101 | }, | |
102 | { | |
103 | .start = 26, | |
104 | .end = 26, | |
105 | .flags = IORESOURCE_IRQ | |
106 | } | |
107 | }; | |
108 | ||
109 | static struct platform_device snirm_53c710_rm200_pdev = { | |
70342287 RB |
110 | .name = "snirm_53c710", |
111 | .num_resources = ARRAY_SIZE(snirm_53c710_rm200_rsrc), | |
112 | .resource = snirm_53c710_rm200_rsrc | |
c066a32a TB |
113 | }; |
114 | ||
115 | static int __init snirm_setup_devinit(void) | |
116 | { | |
117 | if (sni_brd_type == SNI_BRD_RM200) { | |
118 | platform_device_register(&rm200_serial8250_device); | |
06cf5583 | 119 | platform_device_register(&rm200_ds1216_device); |
c066a32a TB |
120 | platform_device_register(&snirm_82596_rm200_pdev); |
121 | platform_device_register(&snirm_53c710_rm200_pdev); | |
231a35d3 | 122 | sni_eisa_root_init(); |
c066a32a TB |
123 | } |
124 | return 0; | |
125 | } | |
126 | ||
127 | device_initcall(snirm_setup_devinit); | |
128 | ||
231a35d3 TB |
129 | /* |
130 | * RM200 has an ISA and an EISA bus. The iSA bus is only used | |
131 | * for onboard devices and also has twi i8259 PICs. Since these | |
132 | * PICs are no accessible via inb/outb the following code uses | |
133 | * readb/writeb to access them | |
134 | */ | |
135 | ||
36946d73 | 136 | static DEFINE_RAW_SPINLOCK(sni_rm200_i8259A_lock); |
70342287 RB |
137 | #define PIC_CMD 0x00 |
138 | #define PIC_IMR 0x01 | |
139 | #define PIC_ISR PIC_CMD | |
231a35d3 TB |
140 | #define PIC_POLL PIC_ISR |
141 | #define PIC_OCW3 PIC_ISR | |
142 | ||
143 | /* i8259A PIC related value */ | |
144 | #define PIC_CASCADE_IR 2 | |
145 | #define MASTER_ICW4_DEFAULT 0x01 | |
146 | #define SLAVE_ICW4_DEFAULT 0x01 | |
147 | ||
148 | /* | |
149 | * This contains the irq mask for both 8259A irq controllers, | |
150 | */ | |
151 | static unsigned int rm200_cached_irq_mask = 0xffff; | |
152 | static __iomem u8 *rm200_pic_master; | |
153 | static __iomem u8 *rm200_pic_slave; | |
154 | ||
155 | #define cached_master_mask (rm200_cached_irq_mask) | |
156 | #define cached_slave_mask (rm200_cached_irq_mask >> 8) | |
157 | ||
0b888c7f | 158 | static void sni_rm200_disable_8259A_irq(struct irq_data *d) |
231a35d3 | 159 | { |
0b888c7f | 160 | unsigned int mask, irq = d->irq - RM200_I8259A_IRQ_BASE; |
231a35d3 TB |
161 | unsigned long flags; |
162 | ||
231a35d3 | 163 | mask = 1 << irq; |
36946d73 | 164 | raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags); |
231a35d3 TB |
165 | rm200_cached_irq_mask |= mask; |
166 | if (irq & 8) | |
167 | writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR); | |
168 | else | |
169 | writeb(cached_master_mask, rm200_pic_master + PIC_IMR); | |
36946d73 | 170 | raw_spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags); |
231a35d3 TB |
171 | } |
172 | ||
0b888c7f | 173 | static void sni_rm200_enable_8259A_irq(struct irq_data *d) |
231a35d3 | 174 | { |
0b888c7f | 175 | unsigned int mask, irq = d->irq - RM200_I8259A_IRQ_BASE; |
231a35d3 TB |
176 | unsigned long flags; |
177 | ||
231a35d3 | 178 | mask = ~(1 << irq); |
36946d73 | 179 | raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags); |
231a35d3 TB |
180 | rm200_cached_irq_mask &= mask; |
181 | if (irq & 8) | |
182 | writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR); | |
183 | else | |
184 | writeb(cached_master_mask, rm200_pic_master + PIC_IMR); | |
36946d73 | 185 | raw_spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags); |
231a35d3 TB |
186 | } |
187 | ||
188 | static inline int sni_rm200_i8259A_irq_real(unsigned int irq) | |
189 | { | |
190 | int value; | |
191 | int irqmask = 1 << irq; | |
192 | ||
193 | if (irq < 8) { | |
194 | writeb(0x0B, rm200_pic_master + PIC_CMD); | |
195 | value = readb(rm200_pic_master + PIC_CMD) & irqmask; | |
196 | writeb(0x0A, rm200_pic_master + PIC_CMD); | |
197 | return value; | |
198 | } | |
199 | writeb(0x0B, rm200_pic_slave + PIC_CMD); /* ISR register */ | |
200 | value = readb(rm200_pic_slave + PIC_CMD) & (irqmask >> 8); | |
201 | writeb(0x0A, rm200_pic_slave + PIC_CMD); | |
202 | return value; | |
203 | } | |
204 | ||
205 | /* | |
206 | * Careful! The 8259A is a fragile beast, it pretty | |
207 | * much _has_ to be done exactly like this (mask it | |
208 | * first, _then_ send the EOI, and the order of EOI | |
209 | * to the two 8259s is important! | |
210 | */ | |
0b888c7f | 211 | void sni_rm200_mask_and_ack_8259A(struct irq_data *d) |
231a35d3 | 212 | { |
0b888c7f | 213 | unsigned int irqmask, irq = d->irq - RM200_I8259A_IRQ_BASE; |
231a35d3 TB |
214 | unsigned long flags; |
215 | ||
231a35d3 | 216 | irqmask = 1 << irq; |
36946d73 | 217 | raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags); |
231a35d3 TB |
218 | /* |
219 | * Lightweight spurious IRQ detection. We do not want | |
220 | * to overdo spurious IRQ handling - it's usually a sign | |
221 | * of hardware problems, so we only do the checks we can | |
222 | * do without slowing down good hardware unnecessarily. | |
223 | * | |
224 | * Note that IRQ7 and IRQ15 (the two spurious IRQs | |
225 | * usually resulting from the 8259A-1|2 PICs) occur | |
226 | * even if the IRQ is masked in the 8259A. Thus we | |
227 | * can check spurious 8259A IRQs without doing the | |
228 | * quite slow i8259A_irq_real() call for every IRQ. | |
229 | * This does not cover 100% of spurious interrupts, | |
230 | * but should be enough to warn the user that there | |
231 | * is something bad going on ... | |
232 | */ | |
233 | if (rm200_cached_irq_mask & irqmask) | |
234 | goto spurious_8259A_irq; | |
235 | rm200_cached_irq_mask |= irqmask; | |
236 | ||
237 | handle_real_irq: | |
238 | if (irq & 8) { | |
239 | readb(rm200_pic_slave + PIC_IMR); | |
240 | writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR); | |
241 | writeb(0x60+(irq & 7), rm200_pic_slave + PIC_CMD); | |
242 | writeb(0x60+PIC_CASCADE_IR, rm200_pic_master + PIC_CMD); | |
243 | } else { | |
244 | readb(rm200_pic_master + PIC_IMR); | |
245 | writeb(cached_master_mask, rm200_pic_master + PIC_IMR); | |
246 | writeb(0x60+irq, rm200_pic_master + PIC_CMD); | |
247 | } | |
36946d73 | 248 | raw_spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags); |
231a35d3 TB |
249 | return; |
250 | ||
251 | spurious_8259A_irq: | |
252 | /* | |
253 | * this is the slow path - should happen rarely. | |
254 | */ | |
255 | if (sni_rm200_i8259A_irq_real(irq)) | |
256 | /* | |
257 | * oops, the IRQ _is_ in service according to the | |
258 | * 8259A - not spurious, go handle it. | |
259 | */ | |
260 | goto handle_real_irq; | |
261 | ||
262 | { | |
263 | static int spurious_irq_mask; | |
264 | /* | |
265 | * At this point we can be sure the IRQ is spurious, | |
4939788e | 266 | * let's ACK and report it. [once per IRQ] |
231a35d3 TB |
267 | */ |
268 | if (!(spurious_irq_mask & irqmask)) { | |
269 | printk(KERN_DEBUG | |
270 | "spurious RM200 8259A interrupt: IRQ%d.\n", irq); | |
271 | spurious_irq_mask |= irqmask; | |
272 | } | |
273 | atomic_inc(&irq_err_count); | |
274 | /* | |
275 | * Theoretically we do not have to handle this IRQ, | |
276 | * but in Linux this does not cause problems and is | |
277 | * simpler for us. | |
278 | */ | |
279 | goto handle_real_irq; | |
280 | } | |
281 | } | |
282 | ||
283 | static struct irq_chip sni_rm200_i8259A_chip = { | |
284 | .name = "RM200-XT-PIC", | |
0b888c7f TG |
285 | .irq_mask = sni_rm200_disable_8259A_irq, |
286 | .irq_unmask = sni_rm200_enable_8259A_irq, | |
287 | .irq_mask_ack = sni_rm200_mask_and_ack_8259A, | |
231a35d3 TB |
288 | }; |
289 | ||
290 | /* | |
291 | * Do the traditional i8259 interrupt polling thing. This is for the few | |
292 | * cases where no better interrupt acknowledge method is available and we | |
293 | * absolutely must touch the i8259. | |
294 | */ | |
295 | static inline int sni_rm200_i8259_irq(void) | |
296 | { | |
297 | int irq; | |
298 | ||
36946d73 | 299 | raw_spin_lock(&sni_rm200_i8259A_lock); |
231a35d3 TB |
300 | |
301 | /* Perform an interrupt acknowledge cycle on controller 1. */ | |
302 | writeb(0x0C, rm200_pic_master + PIC_CMD); /* prepare for poll */ | |
303 | irq = readb(rm200_pic_master + PIC_CMD) & 7; | |
304 | if (irq == PIC_CASCADE_IR) { | |
305 | /* | |
306 | * Interrupt is cascaded so perform interrupt | |
307 | * acknowledge on controller 2. | |
308 | */ | |
309 | writeb(0x0C, rm200_pic_slave + PIC_CMD); /* prepare for poll */ | |
310 | irq = (readb(rm200_pic_slave + PIC_CMD) & 7) + 8; | |
311 | } | |
312 | ||
313 | if (unlikely(irq == 7)) { | |
314 | /* | |
315 | * This may be a spurious interrupt. | |
316 | * | |
317 | * Read the interrupt status register (ISR). If the most | |
318 | * significant bit is not set then there is no valid | |
319 | * interrupt. | |
320 | */ | |
321 | writeb(0x0B, rm200_pic_master + PIC_ISR); /* ISR register */ | |
322 | if (~readb(rm200_pic_master + PIC_ISR) & 0x80) | |
323 | irq = -1; | |
324 | } | |
325 | ||
36946d73 | 326 | raw_spin_unlock(&sni_rm200_i8259A_lock); |
231a35d3 TB |
327 | |
328 | return likely(irq >= 0) ? irq + RM200_I8259A_IRQ_BASE : irq; | |
329 | } | |
330 | ||
331 | void sni_rm200_init_8259A(void) | |
332 | { | |
333 | unsigned long flags; | |
334 | ||
36946d73 | 335 | raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags); |
231a35d3 TB |
336 | |
337 | writeb(0xff, rm200_pic_master + PIC_IMR); | |
338 | writeb(0xff, rm200_pic_slave + PIC_IMR); | |
339 | ||
340 | writeb(0x11, rm200_pic_master + PIC_CMD); | |
341 | writeb(0, rm200_pic_master + PIC_IMR); | |
342 | writeb(1U << PIC_CASCADE_IR, rm200_pic_master + PIC_IMR); | |
343 | writeb(MASTER_ICW4_DEFAULT, rm200_pic_master + PIC_IMR); | |
344 | writeb(0x11, rm200_pic_slave + PIC_CMD); | |
345 | writeb(8, rm200_pic_slave + PIC_IMR); | |
346 | writeb(PIC_CASCADE_IR, rm200_pic_slave + PIC_IMR); | |
347 | writeb(SLAVE_ICW4_DEFAULT, rm200_pic_slave + PIC_IMR); | |
348 | udelay(100); /* wait for 8259A to initialize */ | |
349 | ||
350 | writeb(cached_master_mask, rm200_pic_master + PIC_IMR); | |
351 | writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR); | |
352 | ||
36946d73 | 353 | raw_spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags); |
231a35d3 TB |
354 | } |
355 | ||
356 | /* | |
357 | * IRQ2 is cascade interrupt to second interrupt controller | |
358 | */ | |
359 | static struct irqaction sni_rm200_irq2 = { | |
1a8a5100 RR |
360 | .handler = no_action, |
361 | .name = "cascade", | |
5a4a4ad8 | 362 | .flags = IRQF_NO_THREAD, |
231a35d3 TB |
363 | }; |
364 | ||
365 | static struct resource sni_rm200_pic1_resource = { | |
366 | .name = "onboard ISA pic1", | |
367 | .start = 0x16000020, | |
368 | .end = 0x16000023, | |
369 | .flags = IORESOURCE_BUSY | |
370 | }; | |
371 | ||
372 | static struct resource sni_rm200_pic2_resource = { | |
373 | .name = "onboard ISA pic2", | |
374 | .start = 0x160000a0, | |
375 | .end = 0x160000a3, | |
376 | .flags = IORESOURCE_BUSY | |
377 | }; | |
378 | ||
379 | /* ISA irq handler */ | |
380 | static irqreturn_t sni_rm200_i8259A_irq_handler(int dummy, void *p) | |
381 | { | |
382 | int irq; | |
383 | ||
384 | irq = sni_rm200_i8259_irq(); | |
385 | if (unlikely(irq < 0)) | |
386 | return IRQ_NONE; | |
387 | ||
388 | do_IRQ(irq); | |
389 | return IRQ_HANDLED; | |
390 | } | |
391 | ||
392 | struct irqaction sni_rm200_i8259A_irq = { | |
393 | .handler = sni_rm200_i8259A_irq_handler, | |
394 | .name = "onboard ISA", | |
395 | .flags = IRQF_SHARED | |
396 | }; | |
397 | ||
398 | void __init sni_rm200_i8259_irqs(void) | |
399 | { | |
400 | int i; | |
401 | ||
402 | rm200_pic_master = ioremap_nocache(0x16000020, 4); | |
403 | if (!rm200_pic_master) | |
404 | return; | |
405 | rm200_pic_slave = ioremap_nocache(0x160000a0, 4); | |
c2d5b5e5 | 406 | if (!rm200_pic_slave) { |
231a35d3 TB |
407 | iounmap(rm200_pic_master); |
408 | return; | |
409 | } | |
410 | ||
411 | insert_resource(&iomem_resource, &sni_rm200_pic1_resource); | |
412 | insert_resource(&iomem_resource, &sni_rm200_pic2_resource); | |
413 | ||
414 | sni_rm200_init_8259A(); | |
415 | ||
416 | for (i = RM200_I8259A_IRQ_BASE; i < RM200_I8259A_IRQ_BASE + 16; i++) | |
e4ec7989 | 417 | irq_set_chip_and_handler(i, &sni_rm200_i8259A_chip, |
231a35d3 TB |
418 | handle_level_irq); |
419 | ||
420 | setup_irq(RM200_I8259A_IRQ_BASE + PIC_CASCADE_IR, &sni_rm200_irq2); | |
421 | } | |
422 | ||
c066a32a | 423 | |
70342287 RB |
424 | #define SNI_RM200_INT_STAT_REG CKSEG1ADDR(0xbc000000) |
425 | #define SNI_RM200_INT_ENA_REG CKSEG1ADDR(0xbc080000) | |
c066a32a TB |
426 | |
427 | #define SNI_RM200_INT_START 24 | |
428 | #define SNI_RM200_INT_END 28 | |
429 | ||
0b888c7f | 430 | static void enable_rm200_irq(struct irq_data *d) |
c066a32a | 431 | { |
0b888c7f | 432 | unsigned int mask = 1 << (d->irq - SNI_RM200_INT_START); |
c066a32a TB |
433 | |
434 | *(volatile u8 *)SNI_RM200_INT_ENA_REG &= ~mask; | |
435 | } | |
436 | ||
0b888c7f | 437 | void disable_rm200_irq(struct irq_data *d) |
c066a32a | 438 | { |
0b888c7f | 439 | unsigned int mask = 1 << (d->irq - SNI_RM200_INT_START); |
c066a32a TB |
440 | |
441 | *(volatile u8 *)SNI_RM200_INT_ENA_REG |= mask; | |
442 | } | |
443 | ||
c066a32a | 444 | static struct irq_chip rm200_irq_type = { |
8922f79e | 445 | .name = "RM200", |
0b888c7f TG |
446 | .irq_mask = disable_rm200_irq, |
447 | .irq_unmask = enable_rm200_irq, | |
c066a32a TB |
448 | }; |
449 | ||
450 | static void sni_rm200_hwint(void) | |
451 | { | |
452 | u32 pending = read_c0_cause() & read_c0_status(); | |
453 | u8 mask; | |
454 | u8 stat; | |
455 | int irq; | |
456 | ||
457 | if (pending & C_IRQ5) | |
49a89efb | 458 | do_IRQ(MIPS_CPU_IRQ_BASE + 7); |
c066a32a | 459 | else if (pending & C_IRQ0) { |
49a89efb | 460 | clear_c0_status(IE_IRQ0); |
c066a32a TB |
461 | mask = *(volatile u8 *)SNI_RM200_INT_ENA_REG ^ 0x1f; |
462 | stat = *(volatile u8 *)SNI_RM200_INT_STAT_REG ^ 0x14; | |
463 | irq = ffs(stat & mask & 0x1f); | |
464 | ||
465 | if (likely(irq > 0)) | |
49a89efb RB |
466 | do_IRQ(irq + SNI_RM200_INT_START - 1); |
467 | set_c0_status(IE_IRQ0); | |
c066a32a TB |
468 | } |
469 | } | |
470 | ||
471 | void __init sni_rm200_irq_init(void) | |
472 | { | |
473 | int i; | |
474 | ||
475 | * (volatile u8 *)SNI_RM200_INT_ENA_REG = 0x1f; | |
476 | ||
231a35d3 | 477 | sni_rm200_i8259_irqs(); |
c066a32a TB |
478 | mips_cpu_irq_init(); |
479 | /* Actually we've got more interrupts to handle ... */ | |
480 | for (i = SNI_RM200_INT_START; i <= SNI_RM200_INT_END; i++) | |
e4ec7989 | 481 | irq_set_chip_and_handler(i, &rm200_irq_type, handle_level_irq); |
c066a32a TB |
482 | sni_hwint = sni_rm200_hwint; |
483 | change_c0_status(ST0_IM, IE_IRQ0); | |
231a35d3 TB |
484 | setup_irq(SNI_RM200_INT_START + 0, &sni_rm200_i8259A_irq); |
485 | setup_irq(SNI_RM200_INT_START + 1, &sni_isa_irq); | |
c066a32a TB |
486 | } |
487 | ||
06cf5583 | 488 | void __init sni_rm200_init(void) |
c066a32a | 489 | { |
c066a32a | 490 | } |