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c066a32a TB |
1 | #include <linux/types.h> |
2 | #include <linux/interrupt.h> | |
3 | #include <linux/time.h> | |
4 | ||
d865bea4 | 5 | #include <asm/i8253.h> |
c066a32a TB |
6 | #include <asm/sni.h> |
7 | #include <asm/time.h> | |
4b550488 | 8 | #include <asm-generic/rtc.h> |
c066a32a TB |
9 | |
10 | #define SNI_CLOCK_TICK_RATE 3686400 | |
11 | #define SNI_COUNTER2_DIV 64 | |
12 | #define SNI_COUNTER0_DIV ((SNI_CLOCK_TICK_RATE / SNI_COUNTER2_DIV) / HZ) | |
13 | ||
84953b39 RB |
14 | static void a20r_set_mode(enum clock_event_mode mode, |
15 | struct clock_event_device *evt) | |
c066a32a | 16 | { |
84953b39 RB |
17 | switch (mode) { |
18 | case CLOCK_EVT_MODE_PERIODIC: | |
19 | *(volatile u8 *)(A20R_PT_CLOCK_BASE + 12) = 0x34; | |
20 | wmb(); | |
21 | *(volatile u8 *)(A20R_PT_CLOCK_BASE + 0) = SNI_COUNTER0_DIV; | |
22 | wmb(); | |
23 | *(volatile u8 *)(A20R_PT_CLOCK_BASE + 0) = SNI_COUNTER0_DIV >> 8; | |
24 | wmb(); | |
25 | ||
26 | *(volatile u8 *)(A20R_PT_CLOCK_BASE + 12) = 0xb4; | |
27 | wmb(); | |
28 | *(volatile u8 *)(A20R_PT_CLOCK_BASE + 8) = SNI_COUNTER2_DIV; | |
29 | wmb(); | |
30 | *(volatile u8 *)(A20R_PT_CLOCK_BASE + 8) = SNI_COUNTER2_DIV >> 8; | |
31 | wmb(); | |
32 | ||
33 | break; | |
34 | case CLOCK_EVT_MODE_ONESHOT: | |
35 | case CLOCK_EVT_MODE_UNUSED: | |
36 | case CLOCK_EVT_MODE_SHUTDOWN: | |
37 | break; | |
38 | case CLOCK_EVT_MODE_RESUME: | |
39 | break; | |
40 | } | |
c066a32a TB |
41 | } |
42 | ||
84953b39 RB |
43 | static struct clock_event_device a20r_clockevent_device = { |
44 | .name = "a20r-timer", | |
45 | .features = CLOCK_EVT_FEAT_PERIODIC, | |
46 | ||
47 | /* .mult, .shift, .max_delta_ns and .min_delta_ns left uninitialized */ | |
48 | ||
49 | .rating = 300, | |
50 | .irq = SNI_A20R_IRQ_TIMER, | |
51 | .set_mode = a20r_set_mode, | |
52 | }; | |
53 | ||
54 | static irqreturn_t a20r_interrupt(int irq, void *dev_id) | |
55 | { | |
56 | struct clock_event_device *cd = dev_id; | |
57 | ||
58 | *(volatile u8 *)A20R_PT_TIM0_ACK = 0; | |
59 | wmb(); | |
60 | ||
61 | cd->event_handler(cd); | |
62 | ||
63 | return IRQ_HANDLED; | |
64 | } | |
65 | ||
66 | static struct irqaction a20r_irqaction = { | |
67 | .handler = a20r_interrupt, | |
68 | .flags = IRQF_DISABLED | IRQF_PERCPU, | |
69 | .name = "a20r-timer", | |
70 | }; | |
71 | ||
c066a32a TB |
72 | /* |
73 | * a20r platform uses 2 counters to divide the input frequency. | |
74 | * Counter 2 output is connected to Counter 0 & 1 input. | |
75 | */ | |
84953b39 | 76 | static void __init sni_a20r_timer_setup(void) |
c066a32a | 77 | { |
84953b39 RB |
78 | struct clock_event_device *cd = &a20r_clockevent_device; |
79 | struct irqaction *action = &a20r_irqaction; | |
80 | unsigned int cpu = smp_processor_id(); | |
c066a32a | 81 | |
84953b39 | 82 | cd->cpumask = cpumask_of_cpu(cpu); |
c066a32a | 83 | |
84953b39 RB |
84 | action->dev_id = cd; |
85 | setup_irq(SNI_A20R_IRQ_TIMER, &a20r_irqaction); | |
c066a32a TB |
86 | } |
87 | ||
88 | #define SNI_8254_TICK_RATE 1193182UL | |
89 | ||
90 | #define SNI_8254_TCSAMP_COUNTER ((SNI_8254_TICK_RATE / HZ) + 255) | |
91 | ||
92 | static __init unsigned long dosample(void) | |
93 | { | |
94 | u32 ct0, ct1; | |
95 | volatile u8 msb, lsb; | |
96 | ||
97 | /* Start the counter. */ | |
49a89efb | 98 | outb_p(0x34, 0x43); |
c066a32a | 99 | outb_p(SNI_8254_TCSAMP_COUNTER & 0xff, 0x40); |
49a89efb | 100 | outb(SNI_8254_TCSAMP_COUNTER >> 8, 0x40); |
c066a32a TB |
101 | |
102 | /* Get initial counter invariant */ | |
103 | ct0 = read_c0_count(); | |
104 | ||
105 | /* Latch and spin until top byte of counter0 is zero */ | |
106 | do { | |
49a89efb RB |
107 | outb(0x00, 0x43); |
108 | lsb = inb(0x40); | |
109 | msb = inb(0x40); | |
c066a32a TB |
110 | ct1 = read_c0_count(); |
111 | } while (msb); | |
112 | ||
113 | /* Stop the counter. */ | |
49a89efb | 114 | outb(0x38, 0x43); |
c066a32a TB |
115 | /* |
116 | * Return the difference, this is how far the r4k counter increments | |
117 | * for every 1/HZ seconds. We round off the nearest 1 MHz of master | |
118 | * clock (= 1000000 / HZ / 2). | |
119 | */ | |
120 | /*return (ct1 - ct0 + (500000/HZ/2)) / (500000/HZ) * (500000/HZ);*/ | |
121 | return (ct1 - ct0) / (500000/HZ) * (500000/HZ); | |
122 | } | |
123 | ||
124 | /* | |
125 | * Here we need to calibrate the cycle counter to at least be close. | |
126 | */ | |
4b550488 | 127 | void __init plat_time_init(void) |
c066a32a TB |
128 | { |
129 | unsigned long r4k_ticks[3]; | |
130 | unsigned long r4k_tick; | |
131 | ||
132 | /* | |
133 | * Figure out the r4k offset, the algorithm is very simple and works in | |
134 | * _all_ cases as long as the 8254 counter register itself works ok (as | |
135 | * an interrupt driving timer it does not because of bug, this is why | |
136 | * we are using the onchip r4k counter/compare register to serve this | |
137 | * purpose, but for r4k_offset calculation it will work ok for us). | |
138 | * There are other very complicated ways of performing this calculation | |
139 | * but this one works just fine so I am not going to futz around. ;-) | |
140 | */ | |
141 | printk(KERN_INFO "Calibrating system timer... "); | |
142 | dosample(); /* Prime cache. */ | |
143 | dosample(); /* Prime cache. */ | |
144 | /* Zero is NOT an option. */ | |
145 | do { | |
146 | r4k_ticks[0] = dosample(); | |
147 | } while (!r4k_ticks[0]); | |
148 | do { | |
149 | r4k_ticks[1] = dosample(); | |
150 | } while (!r4k_ticks[1]); | |
151 | ||
152 | if (r4k_ticks[0] != r4k_ticks[1]) { | |
153 | printk("warning: timer counts differ, retrying... "); | |
154 | r4k_ticks[2] = dosample(); | |
155 | if (r4k_ticks[2] == r4k_ticks[0] | |
156 | || r4k_ticks[2] == r4k_ticks[1]) | |
157 | r4k_tick = r4k_ticks[2]; | |
158 | else { | |
159 | printk("disagreement, using average... "); | |
160 | r4k_tick = (r4k_ticks[0] + r4k_ticks[1] | |
161 | + r4k_ticks[2]) / 3; | |
162 | } | |
163 | } else | |
164 | r4k_tick = r4k_ticks[0]; | |
165 | ||
166 | printk("%d [%d.%04d MHz CPU]\n", (int) r4k_tick, | |
167 | (int) (r4k_tick / (500000 / HZ)), | |
168 | (int) (r4k_tick % (500000 / HZ))); | |
169 | ||
170 | mips_hpt_frequency = r4k_tick * HZ; | |
d865bea4 RB |
171 | |
172 | setup_pit_timer(); | |
c066a32a | 173 | |
c066a32a TB |
174 | switch (sni_brd_type) { |
175 | case SNI_BRD_10: | |
176 | case SNI_BRD_10NEW: | |
177 | case SNI_BRD_TOWER_OASIC: | |
178 | case SNI_BRD_MINITOWER: | |
84953b39 RB |
179 | sni_a20r_timer_setup(); |
180 | break; | |
c066a32a TB |
181 | } |
182 | } | |
4b550488 RB |
183 | |
184 | unsigned long read_persistent_clock(void) | |
185 | { | |
186 | return -1; | |
187 | } |