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Merge remote-tracking branch 'blackfin/for-linus'
[deliverable/linux.git] / arch / mips / txx9 / generic / setup.c
CommitLineData
89d63fe1 1/*
89d63fe1
AN		 2 * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
3 * and RBTX49xx patch from CELF patch archive.
4 *
5 * 2003-2005 (c) MontaVista Software, Inc.
6 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/types.h>
edcaf1a6
AN		 15#include <linux/interrupt.h>
16#include <linux/string.h>
17#include <linux/module.h>
18#include <linux/clk.h>
19#include <linux/err.h>
be7658f7 20#include <linux/gpio/driver.h>
68314725 21#include <linux/platform_device.h>
7779a5e0 22#include <linux/serial_core.h>
51f607c7 23#include <linux/mtd/physmap.h>
ae027ead 24#include <linux/leds.h>
269a3eb1 25#include <linux/device.h>
5a0e3ad6 26#include <linux/slab.h>
ca4d3e67 27#include <linux/irq.h>
edcaf1a6 28#include <asm/bootinfo.h>
bdc92d74 29#include <asm/idle.h>
e0eb7307 30#include <asm/time.h>
a49297e8 31#include <asm/reboot.h>
d10e025f 32#include <asm/r4kcache.h>
b6263ff2 33#include <asm/sections.h>
89d63fe1 34#include <asm/txx9/generic.h>
07517529 35#include <asm/txx9/pci.h>
496a3b5c 36#include <asm/txx9tmr.h>
a591f5d3 37#include <asm/txx9/ndfmc.h>
f48c8c95 38#include <asm/txx9/dmac.h>
edcaf1a6
AN		 39#ifdef CONFIG_CPU_TX49XX
40#include <asm/txx9/tx4938.h>
41#endif
89d63fe1
AN		 42
43/* EBUSC settings of TX4927, etc. */
44struct resource txx9_ce_res[8];
45static char txx9_ce_res_name[8][4]; /* "CEn" */
46
47/* pcode, internal register */
94a4c329 48unsigned int txx9_pcode;
89d63fe1
AN		 49char txx9_pcode_str[8];
50static struct resource txx9_reg_res = {
51 .name = txx9_pcode_str,
52 .flags = IORESOURCE_MEM,
53};
54void __init
55txx9_reg_res_init(unsigned int pcode, unsigned long base, unsigned long size)
56{
57 int i;
58
59 for (i = 0; i < ARRAY_SIZE(txx9_ce_res); i++) {
60 sprintf(txx9_ce_res_name[i], "CE%d", i);
61 txx9_ce_res[i].flags = IORESOURCE_MEM;
62 txx9_ce_res[i].name = txx9_ce_res_name[i];
63 }
64
073828d0 65 txx9_pcode = pcode;
89d63fe1
AN		 66 sprintf(txx9_pcode_str, "TX%x", pcode);
67 if (base) {
68 txx9_reg_res.start = base & 0xfffffffffULL;
69 txx9_reg_res.end = (base & 0xfffffffffULL) + (size - 1);
70 request_resource(&iomem_resource, &txx9_reg_res);
71 }
72}
73
74/* clocks */
75unsigned int txx9_master_clock;
76unsigned int txx9_cpu_clock;
77unsigned int txx9_gbus_clock;
edcaf1a6 78
c7b95bcb
AN		 79#ifdef CONFIG_CPU_TX39XX
80/* don't enable by default - see errata */
81int txx9_ccfg_toeon __initdata;
82#else
94a4c329 83int txx9_ccfg_toeon __initdata = 1;
c7b95bcb 84#endif
edcaf1a6
AN		 85
86/* Minimum CLK support */
87
88struct clk *clk_get(struct device *dev, const char *id)
89{
90 if (!strcmp(id, "spi-baseclk"))
fcc152f3 91 return (struct clk *)((unsigned long)txx9_gbus_clock / 2 / 2);
edcaf1a6 92 if (!strcmp(id, "imbus_clk"))
94a4c329 93 return (struct clk *)((unsigned long)txx9_gbus_clock / 2);
edcaf1a6
AN		 94 return ERR_PTR(-ENOENT);
95}
96EXPORT_SYMBOL(clk_get);
97
98int clk_enable(struct clk *clk)
99{
100 return 0;
101}
102EXPORT_SYMBOL(clk_enable);
103
104void clk_disable(struct clk *clk)
105{
106}
107EXPORT_SYMBOL(clk_disable);
108
109unsigned long clk_get_rate(struct clk *clk)
110{
111 return (unsigned long)clk;
112}
113EXPORT_SYMBOL(clk_get_rate);
114
115void clk_put(struct clk *clk)
116{
117}
118EXPORT_SYMBOL(clk_put);
119
860e546c
AN		 120#define BOARD_VEC(board) extern struct txx9_board_vec board;
121#include <asm/txx9/boards.h>
122#undef BOARD_VEC
edcaf1a6 123
edcaf1a6
AN		 124struct txx9_board_vec *txx9_board_vec __initdata;
125static char txx9_system_type[32];
126
860e546c
AN		 127static struct txx9_board_vec *board_vecs[] __initdata = {
128#define BOARD_VEC(board) &board,
129#include <asm/txx9/boards.h>
130#undef BOARD_VEC
131};
132
133static struct txx9_board_vec *__init find_board_byname(const char *name)
134{
135 int i;
136
137 /* search board_vecs table */
138 for (i = 0; i < ARRAY_SIZE(board_vecs); i++) {
139 if (strstr(board_vecs[i]->system, name))
140 return board_vecs[i];
141 }
142 return NULL;
143}
144
e0dfb20c 145static void __init prom_init_cmdline(void)
edcaf1a6 146{
97b0511c
GU		 147 int argc;
148 int *argv32;
edcaf1a6
AN		 149 int i; /* Always ignore the "-c" at argv[0] */
150
97b0511c
GU		 151 if (fw_arg0 >= CKSEG0 || fw_arg1 < CKSEG0) {
152 /*
153 * argc is not a valid number, or argv32 is not a valid
154 * pointer
155 */
156 argc = 0;
157 argv32 = NULL;
158 } else {
159 argc = (int)fw_arg0;
160 argv32 = (int *)fw_arg1;
161 }
162
e0dfb20c 163 arcs_cmdline[0] = '\0';
edcaf1a6
AN		 164
165 for (i = 1; i < argc; i++) {
e0dfb20c 166 char *str = (char *)(long)argv32[i];
edcaf1a6
AN		 167 if (i != 1)
168 strcat(arcs_cmdline, " ");
e0dfb20c
AN		 169 if (strchr(str, ' ')) {
170 strcat(arcs_cmdline, "\"");
171 strcat(arcs_cmdline, str);
172 strcat(arcs_cmdline, "\"");
173 } else
174 strcat(arcs_cmdline, str);
175 }
edcaf1a6
AN		 176}
177
d10e025f
AN		 178static int txx9_ic_disable __initdata;
179static int txx9_dc_disable __initdata;
180
181#if defined(CONFIG_CPU_TX49XX)
182/* flush all cache on very early stage (before 4k_cache_init) */
183static void __init early_flush_dcache(void)
184{
185 unsigned int conf = read_c0_config();
186 unsigned int dc_size = 1 << (12 + ((conf & CONF_DC) >> 6));
187 unsigned int linesz = 32;
188 unsigned long addr, end;
189
190 end = INDEX_BASE + dc_size / 4;
191 /* 4way, waybit=0 */
192 for (addr = INDEX_BASE; addr < end; addr += linesz) {
193 cache_op(Index_Writeback_Inv_D, addr | 0);
194 cache_op(Index_Writeback_Inv_D, addr | 1);
195 cache_op(Index_Writeback_Inv_D, addr | 2);
196 cache_op(Index_Writeback_Inv_D, addr | 3);
197 }
198}
199
200static void __init txx9_cache_fixup(void)
201{
202 unsigned int conf;
203
204 conf = read_c0_config();
205 /* flush and disable */
206 if (txx9_ic_disable) {
207 conf |= TX49_CONF_IC;
208 write_c0_config(conf);
209 }
210 if (txx9_dc_disable) {
211 early_flush_dcache();
212 conf |= TX49_CONF_DC;
213 write_c0_config(conf);
214 }
215
216 /* enable cache */
217 conf = read_c0_config();
218 if (!txx9_ic_disable)
219 conf &= ~TX49_CONF_IC;
220 if (!txx9_dc_disable)
221 conf &= ~TX49_CONF_DC;
222 write_c0_config(conf);
223
224 if (conf & TX49_CONF_IC)
225 pr_info("TX49XX I-Cache disabled.\n");
226 if (conf & TX49_CONF_DC)
227 pr_info("TX49XX D-Cache disabled.\n");
228}
229#elif defined(CONFIG_CPU_TX39XX)
230/* flush all cache on very early stage (before tx39_cache_init) */
231static void __init early_flush_dcache(void)
232{
233 unsigned int conf = read_c0_config();
234 unsigned int dc_size = 1 << (10 + ((conf & TX39_CONF_DCS_MASK) >>
235 TX39_CONF_DCS_SHIFT));
236 unsigned int linesz = 16;
237 unsigned long addr, end;
238
239 end = INDEX_BASE + dc_size / 2;
240 /* 2way, waybit=0 */
241 for (addr = INDEX_BASE; addr < end; addr += linesz) {
242 cache_op(Index_Writeback_Inv_D, addr | 0);
243 cache_op(Index_Writeback_Inv_D, addr | 1);
244 }
245}
246
247static void __init txx9_cache_fixup(void)
248{
249 unsigned int conf;
250
251 conf = read_c0_config();
252 /* flush and disable */
253 if (txx9_ic_disable) {
254 conf &= ~TX39_CONF_ICE;
255 write_c0_config(conf);
256 }
257 if (txx9_dc_disable) {
258 early_flush_dcache();
259 conf &= ~TX39_CONF_DCE;
260 write_c0_config(conf);
261 }
262
263 /* enable cache */
264 conf = read_c0_config();
265 if (!txx9_ic_disable)
266 conf |= TX39_CONF_ICE;
267 if (!txx9_dc_disable)
268 conf |= TX39_CONF_DCE;
269 write_c0_config(conf);
270
271 if (!(conf & TX39_CONF_ICE))
272 pr_info("TX39XX I-Cache disabled.\n");
273 if (!(conf & TX39_CONF_DCE))
274 pr_info("TX39XX D-Cache disabled.\n");
275}
276#else
277static inline void txx9_cache_fixup(void)
278{
279}
280#endif
281
860e546c 282static void __init preprocess_cmdline(void)
edcaf1a6 283{
7580c9c3 284 static char cmdline[COMMAND_LINE_SIZE] __initdata;
860e546c
AN		 285 char *s;
286
287 strcpy(cmdline, arcs_cmdline);
288 s = cmdline;
289 arcs_cmdline[0] = '\0';
290 while (s && *s) {
291 char *str = strsep(&s, " ");
292 if (strncmp(str, "board=", 6) == 0) {
293 txx9_board_vec = find_board_byname(str + 6);
294 continue;
295 } else if (strncmp(str, "masterclk=", 10) == 0) {
8e9ecbc5
DW		 296 unsigned int val;
297 if (kstrtouint(str + 10, 10, &val) == 0)
860e546c
AN		 298 txx9_master_clock = val;
299 continue;
d10e025f
AN		 300 } else if (strcmp(str, "icdisable") == 0) {
301 txx9_ic_disable = 1;
302 continue;
303 } else if (strcmp(str, "dcdisable") == 0) {
304 txx9_dc_disable = 1;
305 continue;
c7b95bcb
AN		 306 } else if (strcmp(str, "toeoff") == 0) {
307 txx9_ccfg_toeon = 0;
308 continue;
309 } else if (strcmp(str, "toeon") == 0) {
310 txx9_ccfg_toeon = 1;
311 continue;
860e546c
AN		 312 }
313 if (arcs_cmdline[0])
314 strcat(arcs_cmdline, " ");
315 strcat(arcs_cmdline, str);
316 }
d10e025f
AN		 317
318 txx9_cache_fixup();
860e546c
AN		 319}
320
321static void __init select_board(void)
322{
323 const char *envstr;
324
325 /* first, determine by "board=" argument in preprocess_cmdline() */
326 if (txx9_board_vec)
327 return;
328 /* next, determine by "board" envvar */
329 envstr = prom_getenv("board");
330 if (envstr) {
331 txx9_board_vec = find_board_byname(envstr);
332 if (txx9_board_vec)
333 return;
334 }
335
336 /* select "default" board */
c8acd40d 337#ifdef CONFIG_TOSHIBA_JMR3927
7a1fdf19 338 txx9_board_vec = &jmr3927_vec;
edcaf1a6
AN		 339#endif
340#ifdef CONFIG_CPU_TX49XX
341 switch (TX4938_REV_PCODE()) {
8d795f2a 342#ifdef CONFIG_TOSHIBA_RBTX4927
edcaf1a6 343 case 0x4927:
7a1fdf19 344 txx9_board_vec = &rbtx4927_vec;
edcaf1a6
AN		 345 break;
346 case 0x4937:
7a1fdf19 347 txx9_board_vec = &rbtx4937_vec;
edcaf1a6 348 break;
8d795f2a
AN		 349#endif
350#ifdef CONFIG_TOSHIBA_RBTX4938
edcaf1a6 351 case 0x4938:
7a1fdf19 352 txx9_board_vec = &rbtx4938_vec;
edcaf1a6 353 break;
b27311e1
AN		 354#endif
355#ifdef CONFIG_TOSHIBA_RBTX4939
356 case 0x4939:
357 txx9_board_vec = &rbtx4939_vec;
358 break;
8d795f2a 359#endif
edcaf1a6
AN		 360 }
361#endif
860e546c
AN		 362}
363
364void __init prom_init(void)
365{
366 prom_init_cmdline();
367 preprocess_cmdline();
368 select_board();
7a1fdf19
YY		 369
370 strcpy(txx9_system_type, txx9_board_vec->system);
371
7b226094 372 txx9_board_vec->prom_init();
edcaf1a6
AN		 373}
374
375void __init prom_free_prom_memory(void)
376{
b6263ff2
AN		 377 unsigned long saddr = PAGE_SIZE;
378 unsigned long eaddr = __pa_symbol(&_text);
379
380 if (saddr < eaddr)
381 free_init_pages("prom memory", saddr, eaddr);
edcaf1a6
AN		 382}
383
384const char *get_system_type(void)
385{
386 return txx9_system_type;
387}
388
265b89db
AN		 389const char *__init prom_getenv(const char *name)
390{
97b0511c 391 const s32 *str;
265b89db 392
97b0511c 393 if (fw_arg2 < CKSEG0)
265b89db 394 return NULL;
97b0511c
GU		 395
396 str = (const s32 *)fw_arg2;
265b89db
AN		 397 /* YAMON style ("name", "value" pairs) */
398 while (str[0] && str[1]) {
399 if (!strcmp((const char *)(unsigned long)str[0], name))
400 return (const char *)(unsigned long)str[1];
401 str += 2;
402 }
403 return NULL;
404}
405
a49297e8
AN		 406static void __noreturn txx9_machine_halt(void)
407{
408 local_irq_disable();
409 clear_c0_status(ST0_IM);
410 while (1) {
411 if (cpu_wait) {
412 (*cpu_wait)();
413 if (cpu_has_counter) {
414 /*
415 * Clear counter interrupt while it
416 * breaks WAIT instruction even if
417 * masked.
418 */
419 write_c0_compare(0);
420 }
421 }
422 }
423}
424
68314725
AN		 425/* Watchdog support */
426void __init txx9_wdt_init(unsigned long base)
427{
428 struct resource res = {
429 .start = base,
430 .end = base + 0x100 - 1,
431 .flags = IORESOURCE_MEM,
432 };
433 platform_device_register_simple("txx9wdt", -1, &res, 1);
434}
435
496a3b5c
AN		 436void txx9_wdt_now(unsigned long base)
437{
438 struct txx9_tmr_reg __iomem *tmrptr =
439 ioremap(base, sizeof(struct txx9_tmr_reg));
440 /* disable watch dog timer */
441 __raw_writel(TXx9_TMWTMR_WDIS | TXx9_TMWTMR_TWC, &tmrptr->wtmr);
442 __raw_writel(0, &tmrptr->tcr);
443 /* kick watchdog */
444 __raw_writel(TXx9_TMWTMR_TWIE, &tmrptr->wtmr);
445 __raw_writel(1, &tmrptr->cpra); /* immediate */
446 __raw_writel(TXx9_TMTCR_TCE | TXx9_TMTCR_CCDE | TXx9_TMTCR_TMODE_WDOG,
447 &tmrptr->tcr);
448}
449
c49f91f5
AN		 450/* SPI support */
451void __init txx9_spi_init(int busid, unsigned long base, int irq)
452{
453 struct resource res[] = {
454 {
455 .start = base,
456 .end = base + 0x20 - 1,
457 .flags = IORESOURCE_MEM,
458 }, {
459 .start = irq,
460 .flags = IORESOURCE_IRQ,
461 },
462 };
463 platform_device_register_simple("spi_txx9", busid,
464 res, ARRAY_SIZE(res));
465}
466
467void __init txx9_ethaddr_init(unsigned int id, unsigned char *ethaddr)
468{
469 struct platform_device *pdev =
470 platform_device_alloc("tc35815-mac", id);
471 if (!pdev ||
472 platform_device_add_data(pdev, ethaddr, 6) ||
473 platform_device_add(pdev))
474 platform_device_put(pdev);
475}
476
7779a5e0
AN		 477void __init txx9_sio_init(unsigned long baseaddr, int irq,
478 unsigned int line, unsigned int sclk, int nocts)
479{
480#ifdef CONFIG_SERIAL_TXX9
481 struct uart_port req;
482
483 memset(&req, 0, sizeof(req));
484 req.line = line;
485 req.iotype = UPIO_MEM;
486 req.membase = ioremap(baseaddr, 0x24);
487 req.mapbase = baseaddr;
488 req.irq = irq;
489 if (!nocts)
490 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
491 if (sclk) {
492 req.flags |= UPF_MAGIC_MULTIPLIER /*USE_SCLK*/;
493 req.uartclk = sclk;
494 } else
495 req.uartclk = TXX9_IMCLK;
496 early_serial_txx9_setup(&req);
497#endif /* CONFIG_SERIAL_TXX9 */
498}
499
e352953c 500#ifdef CONFIG_EARLY_PRINTK
f7be4e75 501static void null_prom_putchar(char c)
e352953c
AN		 502{
503}
f7be4e75 504void (*txx9_prom_putchar)(char c) = null_prom_putchar;
e352953c 505
f7be4e75 506void prom_putchar(char c)
e352953c
AN		 507{
508 txx9_prom_putchar(c);
509}
510
511static void __iomem *early_txx9_sio_port;
512
f7be4e75 513static void early_txx9_sio_putchar(char c)
e352953c
AN		 514{
515#define TXX9_SICISR 0x0c
516#define TXX9_SITFIFO 0x1c
517#define TXX9_SICISR_TXALS 0x00000002
518 while (!(__raw_readl(early_txx9_sio_port + TXX9_SICISR) &
519 TXX9_SICISR_TXALS))
520 ;
521 __raw_writel(c, early_txx9_sio_port + TXX9_SITFIFO);
522}
523
524void __init txx9_sio_putchar_init(unsigned long baseaddr)
525{
526 early_txx9_sio_port = ioremap(baseaddr, 0x24);
527 txx9_prom_putchar = early_txx9_sio_putchar;
528}
529#endif /* CONFIG_EARLY_PRINTK */
530
edcaf1a6
AN		 531/* wrappers */
532void __init plat_mem_setup(void)
533{
94a4c329
AN		 534 ioport_resource.start = 0;
535 ioport_resource.end = ~0UL; /* no limit */
536 iomem_resource.start = 0;
537 iomem_resource.end = ~0UL; /* no limit */
a49297e8
AN		 538
539 /* fallback restart/halt routines */
540 _machine_restart = (void (*)(char *))txx9_machine_halt;
541 _machine_halt = txx9_machine_halt;
542 pm_power_off = txx9_machine_halt;
543
07517529
AN		 544#ifdef CONFIG_PCI
545 pcibios_plat_setup = txx9_pcibios_setup;
546#endif
edcaf1a6
AN		 547 txx9_board_vec->mem_setup();
548}
549
550void __init arch_init_irq(void)
551{
552 txx9_board_vec->irq_setup();
553}
554
555void __init plat_time_init(void)
556{
1374d084
AN		 557#ifdef CONFIG_CPU_TX49XX
558 mips_hpt_frequency = txx9_cpu_clock / 2;
559#endif
edcaf1a6
AN		 560 txx9_board_vec->time_init();
561}
562
563static int __init _txx9_arch_init(void)
564{
565 if (txx9_board_vec->arch_init)
566 txx9_board_vec->arch_init();
567 return 0;
568}
569arch_initcall(_txx9_arch_init);
570
571static int __init _txx9_device_init(void)
572{
573 if (txx9_board_vec->device_init)
574 txx9_board_vec->device_init();
575 return 0;
576}
577device_initcall(_txx9_device_init);
578
579int (*txx9_irq_dispatch)(int pending);
580asmlinkage void plat_irq_dispatch(void)
581{
582 int pending = read_c0_status() & read_c0_cause() & ST0_IM;
583 int irq = txx9_irq_dispatch(pending);
584
585 if (likely(irq >= 0))
586 do_IRQ(irq);
587 else
588 spurious_interrupt();
589}
4c642f3f
AN		 590
591/* see include/asm-mips/mach-tx39xx/mangle-port.h, for example. */
592#ifdef NEEDS_TXX9_SWIZZLE_ADDR_B
593static unsigned long __swizzle_addr_none(unsigned long port)
594{
595 return port;
596}
597unsigned long (*__swizzle_addr_b)(unsigned long port) = __swizzle_addr_none;
598EXPORT_SYMBOL(__swizzle_addr_b);
599#endif
51f607c7 600
1ba5a176
AN		 601#ifdef NEEDS_TXX9_IOSWABW
602static u16 ioswabw_default(volatile u16 *a, u16 x)
603{
604 return le16_to_cpu(x);
605}
606static u16 __mem_ioswabw_default(volatile u16 *a, u16 x)
607{
608 return x;
609}
610u16 (*ioswabw)(volatile u16 *a, u16 x) = ioswabw_default;
611EXPORT_SYMBOL(ioswabw);
612u16 (*__mem_ioswabw)(volatile u16 *a, u16 x) = __mem_ioswabw_default;
613EXPORT_SYMBOL(__mem_ioswabw);
614#endif
615
51f607c7
AN		 616void __init txx9_physmap_flash_init(int no, unsigned long addr,
617 unsigned long size,
618 const struct physmap_flash_data *pdata)
619{
b33b4407 620#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
51f607c7
AN		 621 struct resource res = {
622 .start = addr,
623 .end = addr + size - 1,
624 .flags = IORESOURCE_MEM,
625 };
626 struct platform_device *pdev;
51f607c7
AN		 627 static struct mtd_partition parts[2];
628 struct physmap_flash_data pdata_part;
629
630 /* If this area contained boot area, make separate partition */
631 if (pdata->nr_parts == 0 && !pdata->parts &&
632 addr < 0x1fc00000 && addr + size > 0x1fc00000 &&
633 !parts[0].name) {
634 parts[0].name = "boot";
635 parts[0].offset = 0x1fc00000 - addr;
636 parts[0].size = addr + size - 0x1fc00000;
637 parts[1].name = "user";
638 parts[1].offset = 0;
639 parts[1].size = 0x1fc00000 - addr;
640 pdata_part = *pdata;
641 pdata_part.nr_parts = ARRAY_SIZE(parts);
642 pdata_part.parts = parts;
643 pdata = &pdata_part;
644 }
47854888 645
51f607c7
AN		 646 pdev = platform_device_alloc("physmap-flash", no);
647 if (!pdev ||
648 platform_device_add_resources(pdev, &res, 1) ||
a591f5d3
AN		 649 platform_device_add_data(pdev, pdata, sizeof(*pdata)) ||
650 platform_device_add(pdev))
651 platform_device_put(pdev);
652#endif
653}
654
655void __init txx9_ndfmc_init(unsigned long baseaddr,
656 const struct txx9ndfmc_platform_data *pdata)
657{
b33b4407 658#if IS_ENABLED(CONFIG_MTD_NAND_TXX9NDFMC)
a591f5d3
AN		 659 struct resource res = {
660 .start = baseaddr,
661 .end = baseaddr + 0x1000 - 1,
662 .flags = IORESOURCE_MEM,
663 };
664 struct platform_device *pdev = platform_device_alloc("txx9ndfmc", -1);
665
666 if (!pdev ||
667 platform_device_add_resources(pdev, &res, 1) ||
51f607c7
AN		 668 platform_device_add_data(pdev, pdata, sizeof(*pdata)) ||
669 platform_device_add(pdev))
670 platform_device_put(pdev);
671#endif
672}
ae027ead 673
b33b4407 674#if IS_ENABLED(CONFIG_LEDS_GPIO)
ae027ead
AN		 675static DEFINE_SPINLOCK(txx9_iocled_lock);
676
677#define TXX9_IOCLED_MAXLEDS 8
678
679struct txx9_iocled_data {
680 struct gpio_chip chip;
681 u8 cur_val;
682 void __iomem *mmioaddr;
683 struct gpio_led_platform_data pdata;
684 struct gpio_led leds[TXX9_IOCLED_MAXLEDS];
685 char names[TXX9_IOCLED_MAXLEDS][32];
686};
687
688static int txx9_iocled_get(struct gpio_chip *chip, unsigned int offset)
689{
be7658f7 690 struct txx9_iocled_data *data = gpiochip_get_data(chip);
8cbe4b5c 691 return !!(data->cur_val & (1 << offset));
ae027ead
AN		 692}
693
694static void txx9_iocled_set(struct gpio_chip *chip, unsigned int offset,
695 int value)
696{
be7658f7 697 struct txx9_iocled_data *data = gpiochip_get_data(chip);
ae027ead
AN		 698 unsigned long flags;
699 spin_lock_irqsave(&txx9_iocled_lock, flags);
700 if (value)
701 data->cur_val |= 1 << offset;
702 else
703 data->cur_val &= ~(1 << offset);
704 writeb(data->cur_val, data->mmioaddr);
705 mmiowb();
706 spin_unlock_irqrestore(&txx9_iocled_lock, flags);
707}
708
709static int txx9_iocled_dir_in(struct gpio_chip *chip, unsigned int offset)
710{
711 return 0;
712}
713
714static int txx9_iocled_dir_out(struct gpio_chip *chip, unsigned int offset,
715 int value)
716{
717 txx9_iocled_set(chip, offset, value);
718 return 0;
719}
720
721void __init txx9_iocled_init(unsigned long baseaddr,
722 int basenum, unsigned int num, int lowactive,
723 const char *color, char **deftriggers)
724{
725 struct txx9_iocled_data *iocled;
726 struct platform_device *pdev;
727 int i;
728 static char *default_triggers[] __initdata = {
729 "heartbeat",
dde00512 730 "disk-activity",
ae027ead
AN		 731 "nand-disk",
732 NULL,
733 };
734
735 if (!deftriggers)
736 deftriggers = default_triggers;
737 iocled = kzalloc(sizeof(*iocled), GFP_KERNEL);
738 if (!iocled)
739 return;
740 iocled->mmioaddr = ioremap(baseaddr, 1);
741 if (!iocled->mmioaddr)
70ebadc8 742 goto out_free;
ae027ead
AN		 743 iocled->chip.get = txx9_iocled_get;
744 iocled->chip.set = txx9_iocled_set;
745 iocled->chip.direction_input = txx9_iocled_dir_in;
746 iocled->chip.direction_output = txx9_iocled_dir_out;
747 iocled->chip.label = "iocled";
748 iocled->chip.base = basenum;
749 iocled->chip.ngpio = num;
be7658f7 750 if (gpiochip_add_data(&iocled->chip, iocled))
70ebadc8 751 goto out_unmap;
ae027ead
AN		 752 if (basenum < 0)
753 basenum = iocled->chip.base;
754
755 pdev = platform_device_alloc("leds-gpio", basenum);
756 if (!pdev)
70ebadc8 757 goto out_gpio;
ae027ead
AN		 758 iocled->pdata.num_leds = num;
759 iocled->pdata.leds = iocled->leds;
760 for (i = 0; i < num; i++) {
761 struct gpio_led *led = &iocled->leds[i];
762 snprintf(iocled->names[i], sizeof(iocled->names[i]),
763 "iocled:%s:%u", color, i);
764 led->name = iocled->names[i];
765 led->gpio = basenum + i;
766 led->active_low = lowactive;
767 if (deftriggers && *deftriggers)
768 led->default_trigger = *deftriggers++;
769 }
770 pdev->dev.platform_data = &iocled->pdata;
771 if (platform_device_add(pdev))
70ebadc8
JL		 772 goto out_pdev;
773 return;
88d5e520 774
70ebadc8
JL		 775out_pdev:
776 platform_device_put(pdev);
777out_gpio:
88d5e520 778 gpiochip_remove(&iocled->chip);
70ebadc8
JL		 779out_unmap:
780 iounmap(iocled->mmioaddr);
781out_free:
782 kfree(iocled);
ae027ead
AN		 783}
784#else /* CONFIG_LEDS_GPIO */
785void __init txx9_iocled_init(unsigned long baseaddr,
786 int basenum, unsigned int num, int lowactive,
787 const char *color, char **deftriggers)
788{
789}
790#endif /* CONFIG_LEDS_GPIO */
f48c8c95
AN		 791
792void __init txx9_dmac_init(int id, unsigned long baseaddr, int irq,
793 const struct txx9dmac_platform_data *pdata)
794{
b33b4407 795#if IS_ENABLED(CONFIG_TXX9_DMAC)
f48c8c95
AN		 796 struct resource res[] = {
797 {
798 .start = baseaddr,
799 .end = baseaddr + 0x800 - 1,
800 .flags = IORESOURCE_MEM,
801#ifndef CONFIG_MACH_TX49XX
802 }, {
803 .start = irq,
804 .flags = IORESOURCE_IRQ,
805#endif
806 }
807 };
808#ifdef CONFIG_MACH_TX49XX
809 struct resource chan_res[] = {
810 {
811 .flags = IORESOURCE_IRQ,
812 }
813 };
814#endif
815 struct platform_device *pdev = platform_device_alloc("txx9dmac", id);
816 struct txx9dmac_chan_platform_data cpdata;
817 int i;
818
819 if (!pdev ||
820 platform_device_add_resources(pdev, res, ARRAY_SIZE(res)) ||
821 platform_device_add_data(pdev, pdata, sizeof(*pdata)) ||
822 platform_device_add(pdev)) {
823 platform_device_put(pdev);
824 return;
825 }
826 memset(&cpdata, 0, sizeof(cpdata));
827 cpdata.dmac_dev = pdev;
828 for (i = 0; i < TXX9_DMA_MAX_NR_CHANNELS; i++) {
829#ifdef CONFIG_MACH_TX49XX
830 chan_res[0].start = irq + i;
831#endif
832 pdev = platform_device_alloc("txx9dmac-chan",
833 id * TXX9_DMA_MAX_NR_CHANNELS + i);
834 if (!pdev ||
835#ifdef CONFIG_MACH_TX49XX
836 platform_device_add_resources(pdev, chan_res,
837 ARRAY_SIZE(chan_res)) ||
838#endif
839 platform_device_add_data(pdev, &cpdata, sizeof(cpdata)) ||
840 platform_device_add(pdev))
841 platform_device_put(pdev);
842 }
843#endif
844}
742cd586
AN		 845
846void __init txx9_aclc_init(unsigned long baseaddr, int irq,
847 unsigned int dmac_id,
848 unsigned int dma_chan_out,
849 unsigned int dma_chan_in)
850{
b33b4407 851#if IS_ENABLED(CONFIG_SND_SOC_TXX9ACLC)
742cd586
AN		 852 unsigned int dma_base = dmac_id * TXX9_DMA_MAX_NR_CHANNELS;
853 struct resource res[] = {
854 {
855 .start = baseaddr,
856 .end = baseaddr + 0x100 - 1,
857 .flags = IORESOURCE_MEM,
858 }, {
859 .start = irq,
860 .flags = IORESOURCE_IRQ,
861 }, {
862 .name = "txx9dmac-chan",
863 .start = dma_base + dma_chan_out,
864 .flags = IORESOURCE_DMA,
865 }, {
866 .name = "txx9dmac-chan",
867 .start = dma_base + dma_chan_in,
868 .flags = IORESOURCE_DMA,
869 }
870 };
871 struct platform_device *pdev =
872 platform_device_alloc("txx9aclc-ac97", -1);
873
874 if (!pdev ||
875 platform_device_add_resources(pdev, res, ARRAY_SIZE(res)) ||
876 platform_device_add(pdev))
877 platform_device_put(pdev);
878#endif
879}
c3b28ae2 880
269a3eb1
KS		 881static struct bus_type txx9_sramc_subsys = {
882 .name = "txx9_sram",
883 .dev_name = "txx9_sram",
884};
c3b28ae2 885
269a3eb1
KS		 886struct txx9_sramc_dev {
887 struct device dev;
c3b28ae2
AN		 888 struct bin_attribute bindata_attr;
889 void __iomem *base;
890};
891
2c3c8bea 892static ssize_t txx9_sram_read(struct file *filp, struct kobject *kobj,
c3b28ae2
AN		 893 struct bin_attribute *bin_attr,
894 char *buf, loff_t pos, size_t size)
895{
269a3eb1 896 struct txx9_sramc_dev *dev = bin_attr->private;
c3b28ae2
AN		 897 size_t ramsize = bin_attr->size;
898
899 if (pos >= ramsize)
900 return 0;
901 if (pos + size > ramsize)
902 size = ramsize - pos;
903 memcpy_fromio(buf, dev->base + pos, size);
904 return size;
905}
906
2c3c8bea 907static ssize_t txx9_sram_write(struct file *filp, struct kobject *kobj,
c3b28ae2
AN		 908 struct bin_attribute *bin_attr,
909 char *buf, loff_t pos, size_t size)
910{
269a3eb1 911 struct txx9_sramc_dev *dev = bin_attr->private;
c3b28ae2
AN		 912 size_t ramsize = bin_attr->size;
913
914 if (pos >= ramsize)
915 return 0;
916 if (pos + size > ramsize)
917 size = ramsize - pos;
918 memcpy_toio(dev->base + pos, buf, size);
919 return size;
920}
921
1610c8a8
LK		 922static void txx9_device_release(struct device *dev)
923{
924 struct txx9_sramc_dev *tdev;
925
926 tdev = container_of(dev, struct txx9_sramc_dev, dev);
927 kfree(tdev);
928}
929
c3b28ae2
AN		 930void __init txx9_sramc_init(struct resource *r)
931{
269a3eb1 932 struct txx9_sramc_dev *dev;
c3b28ae2
AN		 933 size_t size;
934 int err;
935
269a3eb1
KS		 936 err = subsys_system_register(&txx9_sramc_subsys, NULL);
937 if (err)
938 return;
c3b28ae2
AN		 939 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
940 if (!dev)
941 return;
942 size = resource_size(r);
943 dev->base = ioremap(r->start, size);
1610c8a8
LK		 944 if (!dev->base) {
945 kfree(dev);
946 return;
947 }
948 dev->dev.release = &txx9_device_release;
269a3eb1 949 dev->dev.bus = &txx9_sramc_subsys;
f937331b 950 sysfs_bin_attr_init(&dev->bindata_attr);
c3b28ae2
AN		 951 dev->bindata_attr.attr.name = "bindata";
952 dev->bindata_attr.attr.mode = S_IRUSR | S_IWUSR;
953 dev->bindata_attr.read = txx9_sram_read;
954 dev->bindata_attr.write = txx9_sram_write;
955 dev->bindata_attr.size = size;
956 dev->bindata_attr.private = dev;
269a3eb1 957 err = device_register(&dev->dev);
c3b28ae2 958 if (err)
1610c8a8 959 goto exit_put;
c3b28ae2
AN		 960 err = sysfs_create_bin_file(&dev->dev.kobj, &dev->bindata_attr);
961 if (err) {
269a3eb1 962 device_unregister(&dev->dev);
1610c8a8 963 iounmap(dev->base);
c3b28ae2
AN		 964 kfree(dev);
965 }
1610c8a8
LK		 966 return;
967exit_put:
968 put_device(&dev->dev);
969 return;
c3b28ae2 970}
Linux kernel - Deliverables
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