[deliverable/linux.git] / arch / mips / txx9 / jmr3927 / irq.c

/*
 * Copyright 2001 MontaVista Software Inc.
 * Author: MontaVista Software, Inc.
 *              ahennessy@mvista.com
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2000-2001 Toshiba Corporation
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/interrupt.h>

#include <asm/io.h>
#include <asm/mipsregs.h>
#include <asm/system.h>

#include <asm/processor.h>
#include <asm/txx9/generic.h>
#include <asm/txx9/jmr3927.h>

#if JMR3927_IRQ_END > NR_IRQS
#error JMR3927_IRQ_END > NR_IRQS
#endif

/*
 * CP0_STATUS is a thread's resource (saved/restored on context switch).
 * So disable_irq/enable_irq MUST handle IOC/IRC registers.
 */
static void mask_irq_ioc(unsigned int irq)
{
	/* 0: mask */
	unsigned int irq_nr = irq - JMR3927_IRQ_IOC;
	unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
	unsigned int bit = 1 << irq_nr;
	jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR);
	/* flush write buffer */
	(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
}
static void unmask_irq_ioc(unsigned int irq)
{
	/* 0: mask */
	unsigned int irq_nr = irq - JMR3927_IRQ_IOC;
	unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
	unsigned int bit = 1 << irq_nr;
	jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR);
	/* flush write buffer */
	(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
}

static int jmr3927_ioc_irqroute(void)
{
	unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR);
	int i;

	for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) {
		if (istat & (1 << i))
			return JMR3927_IRQ_IOC + i;
	}
	return -1;
}

static int jmr3927_irq_dispatch(int pending)
{
	int irq;

	if ((pending & CAUSEF_IP7) == 0)
		return -1;
	irq = (pending >> CAUSEB_IP2) & 0x0f;
	irq += JMR3927_IRQ_IRC;
	if (irq == JMR3927_IRQ_IOCINT)
		irq = jmr3927_ioc_irqroute();
	return irq;
}

static struct irq_chip jmr3927_irq_ioc = {
	.name = "jmr3927_ioc",
	.ack = mask_irq_ioc,
	.mask = mask_irq_ioc,
	.mask_ack = mask_irq_ioc,
	.unmask = unmask_irq_ioc,
};

void __init jmr3927_irq_setup(void)
{
	int i;

	txx9_irq_dispatch = jmr3927_irq_dispatch;
	/* Now, interrupt control disabled, */
	/* all IRC interrupts are masked, */
	/* all IRC interrupt mode are Low Active. */

	/* mask all IOC interrupts */
	jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR);
	/* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */
	jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR);

	/* clear PCI Soft interrupts */
	jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR);
	/* clear PCI Reset interrupts */
	jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);

	tx3927_irq_init();
	for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++)
		set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq);

	/* setup IOC interrupt 1 (PCI, MODEM) */
	set_irq_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Copyright 2001 MontaVista Software Inc.
	3	* Author: MontaVista Software, Inc.
	4	* ahennessy@mvista.com
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*
	10	* Copyright (C) 2000-2001 Toshiba Corporation
	11	*
	12	* This program is free software; you can redistribute it and/or modify it
	13	* under the terms of the GNU General Public License as published by the
	14	* Free Software Foundation; either version 2 of the License, or (at your
	15	* option) any later version.
	16	*
	17	* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
	18	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	19	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
	20	* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
	23	* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	24	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	27	*
	28	* You should have received a copy of the GNU General Public License along
	29	* with this program; if not, write to the Free Software Foundation, Inc.,
	30	* 675 Mass Ave, Cambridge, MA 02139, USA.
	31	*/
1da177e4	32	#include <linux/init.h>
1da177e4 LT	33	#include <linux/sched.h>
	34	#include <linux/types.h>
	35	#include <linux/interrupt.h>
1da177e4 LT	36
	37	#include <asm/io.h>
	38	#include <asm/mipsregs.h>
	39	#include <asm/system.h>
	40
1da177e4	41	#include <asm/processor.h>
edcaf1a6	42	#include <asm/txx9/generic.h>
22b1d707	43	#include <asm/txx9/jmr3927.h>
1da177e4 LT	44
	45	#if JMR3927_IRQ_END > NR_IRQS
	46	#error JMR3927_IRQ_END > NR_IRQS
	47	#endif
	48
1da177e4 LT	49	/*
1da177e4 LT	50	* CP0_STATUS is a thread's resource (saved/restored on context switch).
2127435e	51	* So disable_irq/enable_irq MUST handle IOC/IRC registers.
1da177e4	52	*/
2127435e	53	static void mask_irq_ioc(unsigned int irq)
1da177e4 LT	54	{
1da177e4 LT	55	/* 0: mask */
2127435e	56	unsigned int irq_nr = irq - JMR3927_IRQ_IOC;
1da177e4 LT	57	unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
	58	unsigned int bit = 1 << irq_nr;
	59	jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR);
	60	/* flush write buffer */
	61	(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
	62	}
2127435e	63	static void unmask_irq_ioc(unsigned int irq)
1da177e4 LT	64	{
1da177e4 LT	65	/* 0: mask */
2127435e	66	unsigned int irq_nr = irq - JMR3927_IRQ_IOC;
1da177e4 LT	67	unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
	68	unsigned int bit = 1 << irq_nr;
	69	jmr3927_ioc_reg_out(imask \| bit, JMR3927_IOC_INTM_ADDR);
	70	/* flush write buffer */
	71	(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
	72	}
	73
edcaf1a6	74	static int jmr3927_ioc_irqroute(void)
1da177e4 LT	75	{
	76	unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR);
	77	int i;
	78
	79	for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) {
edcaf1a6 AN	80	if (istat & (1 << i))
edcaf1a6 AN	81	return JMR3927_IRQ_IOC + i;
1da177e4	82	}
edcaf1a6	83	return -1;
1da177e4 LT	84	}
1da177e4 LT	85
edcaf1a6 AN	86	static int jmr3927_irq_dispatch(int pending)
	87	{
	88	int irq;
	89
	90	if ((pending & CAUSEF_IP7) == 0)
	91	return -1;
	92	irq = (pending >> CAUSEB_IP2) & 0x0f;
	93	irq += JMR3927_IRQ_IRC;
	94	if (irq == JMR3927_IRQ_IOCINT)
	95	irq = jmr3927_ioc_irqroute();
	96	return irq;
	97	}
1da177e4	98
f6727fb8 AN	99	static struct irq_chip jmr3927_irq_ioc = {
	100	.name = "jmr3927_ioc",
	101	.ack = mask_irq_ioc,
	102	.mask = mask_irq_ioc,
	103	.mask_ack = mask_irq_ioc,
	104	.unmask = unmask_irq_ioc,
	105	};
1da177e4	106
edcaf1a6	107	void __init jmr3927_irq_setup(void)
1da177e4	108	{
f6727fb8 AN	109	int i;
f6727fb8 AN	110
edcaf1a6	111	txx9_irq_dispatch = jmr3927_irq_dispatch;
1da177e4 LT	112	/* Now, interrupt control disabled, */
	113	/* all IRC interrupts are masked, */
	114	/* all IRC interrupt mode are Low Active. */
	115
1da177e4 LT	116	/* mask all IOC interrupts */
	117	jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR);
	118	/* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */
	119	jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR);
	120
1da177e4 LT	121	/* clear PCI Soft interrupts */
	122	jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR);
	123	/* clear PCI Reset interrupts */
	124	jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
	125
f6727fb8 AN	126	tx3927_irq_init();
	127	for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++)
	128	set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq);
1da177e4 LT	129
1da177e4 LT	130	/* setup IOC interrupt 1 (PCI, MODEM) */
edcaf1a6	131	set_irq_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq);
1da177e4	132	}