[deliverable/linux.git] / arch / mips / txx9 / rbtx4927 / setup.c

/*
 * Toshiba rbtx4927 specific setup
 *
 * Author: MontaVista Software, Inc.
 *         source@mvista.com
 *
 * Copyright 2001-2002 MontaVista Software Inc.
 *
 * Copyright (C) 1996, 97, 2001, 04  Ralf Baechle (ralf@linux-mips.org)
 * Copyright (C) 2000 RidgeRun, Inc.
 * Author: RidgeRun, Inc.
 *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
 *
 * Copyright 2001 MontaVista Software Inc.
 * Author: jsun@mvista.com or jsun@junsun.net
 *
 * Copyright 2002 MontaVista Software Inc.
 * Author: Michael Pruznick, michael_pruznick@mvista.com
 *
 * Copyright (C) 2000-2001 Toshiba Corporation
 *
 * Copyright (C) 2004 MontaVista Software Inc.
 * Author: Manish Lachwani, mlachwani@mvista.com
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the
 *  Free Software Foundation; either version 2 of the License, or (at your
 *  option) any later version.
 *
 *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
 *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
 *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
 *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/pm.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/reboot.h>
#include <asm/txx9/generic.h>
#include <asm/txx9/pci.h>
#include <asm/txx9/rbtx4927.h>
#include <asm/txx9/tx4938.h>	/* for TX4937 */

#ifdef CONFIG_PCI
static void __init tx4927_pci_setup(void)
{
	int extarb = !(__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB);
	struct pci_controller *c = &txx9_primary_pcic;

	register_pci_controller(c);

	if (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66)
		txx9_pci_option =
			(txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
			TXX9_PCI_OPT_CLK_66; /* already configured */

	/* Reset PCI Bus */
	writeb(1, rbtx4927_pcireset_addr);
	/* Reset PCIC */
	txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
	if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
	    TXX9_PCI_OPT_CLK_66)
		tx4927_pciclk66_setup();
	mdelay(10);
	/* clear PCIC reset */
	txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
	writeb(0, rbtx4927_pcireset_addr);
	iob();

	tx4927_report_pciclk();
	tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
	if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
	    TXX9_PCI_OPT_CLK_AUTO &&
	    txx9_pci66_check(c, 0, 0)) {
		/* Reset PCI Bus */
		writeb(1, rbtx4927_pcireset_addr);
		/* Reset PCIC */
		txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
		tx4927_pciclk66_setup();
		mdelay(10);
		/* clear PCIC reset */
		txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
		writeb(0, rbtx4927_pcireset_addr);
		iob();
		/* Reinitialize PCIC */
		tx4927_report_pciclk();
		tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
	}
}

static void __init tx4937_pci_setup(void)
{
	int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
	struct pci_controller *c = &txx9_primary_pcic;

	register_pci_controller(c);

	if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
		txx9_pci_option =
			(txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
			TXX9_PCI_OPT_CLK_66; /* already configured */

	/* Reset PCI Bus */
	writeb(1, rbtx4927_pcireset_addr);
	/* Reset PCIC */
	txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
	if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
	    TXX9_PCI_OPT_CLK_66)
		tx4938_pciclk66_setup();
	mdelay(10);
	/* clear PCIC reset */
	txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
	writeb(0, rbtx4927_pcireset_addr);
	iob();

	tx4938_report_pciclk();
	tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
	if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
	    TXX9_PCI_OPT_CLK_AUTO &&
	    txx9_pci66_check(c, 0, 0)) {
		/* Reset PCI Bus */
		writeb(1, rbtx4927_pcireset_addr);
		/* Reset PCIC */
		txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
		tx4938_pciclk66_setup();
		mdelay(10);
		/* clear PCIC reset */
		txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
		writeb(0, rbtx4927_pcireset_addr);
		iob();
		/* Reinitialize PCIC */
		tx4938_report_pciclk();
		tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
	}
}

static void __init rbtx4927_arch_init(void)
{
	tx4927_pci_setup();
}

static void __init rbtx4937_arch_init(void)
{
	tx4937_pci_setup();
}
#else
#define rbtx4927_arch_init NULL
#define rbtx4937_arch_init NULL
#endif /* CONFIG_PCI */

static void __noreturn wait_forever(void)
{
	while (1)
		if (cpu_wait)
			(*cpu_wait)();
}

static void toshiba_rbtx4927_restart(char *command)
{
	printk(KERN_NOTICE "System Rebooting...\n");

	/* enable the s/w reset register */
	writeb(1, rbtx4927_softresetlock_addr);

	/* wait for enable to be seen */
	while (!(readb(rbtx4927_softresetlock_addr) & 1))
		;

	/* do a s/w reset */
	writeb(1, rbtx4927_softreset_addr);

	/* do something passive while waiting for reset */
	local_irq_disable();
	wait_forever();
	/* no return */
}

static void toshiba_rbtx4927_halt(void)
{
	printk(KERN_NOTICE "System Halted\n");
	local_irq_disable();
	wait_forever();
	/* no return */
}

static void toshiba_rbtx4927_power_off(void)
{
	toshiba_rbtx4927_halt();
	/* no return */
}

static void __init rbtx4927_clock_init(void);
static void __init rbtx4937_clock_init(void);

static void __init rbtx4927_mem_setup(void)
{
	u32 cp0_config;
	char *argptr;

	/* f/w leaves this on at startup */
	clear_c0_status(ST0_ERL);

	/* enable caches -- HCP5 does this, pmon does not */
	cp0_config = read_c0_config();
	cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
	write_c0_config(cp0_config);

	if (TX4927_REV_PCODE() == 0x4927) {
		rbtx4927_clock_init();
		tx4927_setup();
	} else {
		rbtx4937_clock_init();
		tx4938_setup();
	}

	_machine_restart = toshiba_rbtx4927_restart;
	_machine_halt = toshiba_rbtx4927_halt;
	pm_power_off = toshiba_rbtx4927_power_off;

#ifdef CONFIG_PCI
	txx9_alloc_pci_controller(&txx9_primary_pcic,
				  RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE,
				  RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE);
#else
	set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET);
#endif

	tx4927_setup_serial();
#ifdef CONFIG_SERIAL_TXX9_CONSOLE
        argptr = prom_getcmdline();
        if (strstr(argptr, "console=") == NULL) {
                strcat(argptr, " console=ttyS0,38400");
        }
#endif

#ifdef CONFIG_ROOT_NFS
        argptr = prom_getcmdline();
        if (strstr(argptr, "root=") == NULL) {
                strcat(argptr, " root=/dev/nfs rw");
        }
#endif

#ifdef CONFIG_IP_PNP
        argptr = prom_getcmdline();
        if (strstr(argptr, "ip=") == NULL) {
                strcat(argptr, " ip=any");
        }
#endif
}

static void __init rbtx4927_clock_init(void)
{
	/*
	 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
	 *
	 * For TX4927:
	 * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1).
	 * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
	 * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
	 * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
	 * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
	 * i.e. S9[3]: ON (83MHz), OFF (100MHz)
	 */
	switch ((unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg) &
		TX4927_CCFG_PCIDIVMODE_MASK) {
	case TX4927_CCFG_PCIDIVMODE_2_5:
	case TX4927_CCFG_PCIDIVMODE_5:
		txx9_cpu_clock = 166666666;	/* 166MHz */
		break;
	default:
		txx9_cpu_clock = 200000000;	/* 200MHz */
	}
}

static void __init rbtx4937_clock_init(void)
{
	/*
	 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
	 *
	 * For TX4937:
	 * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1)
	 * PCIDIVMODE[10] is 0.
	 * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8)
	 * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4)
	 * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9)
	 * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5)
	 * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10)
	 * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5)
	 */
	switch ((unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg) &
		TX4938_CCFG_PCIDIVMODE_MASK) {
	case TX4938_CCFG_PCIDIVMODE_8:
	case TX4938_CCFG_PCIDIVMODE_4:
		txx9_cpu_clock = 266666666;	/* 266MHz */
		break;
	case TX4938_CCFG_PCIDIVMODE_9:
	case TX4938_CCFG_PCIDIVMODE_4_5:
		txx9_cpu_clock = 300000000;	/* 300MHz */
		break;
	default:
		txx9_cpu_clock = 333333333;	/* 333MHz */
	}
}

static void __init rbtx4927_time_init(void)
{
	tx4927_time_init(0);
}

static int __init toshiba_rbtx4927_rtc_init(void)
{
	struct resource res = {
		.start	= RBTX4927_BRAMRTC_BASE - IO_BASE,
		.end	= RBTX4927_BRAMRTC_BASE - IO_BASE + 0x800 - 1,
		.flags	= IORESOURCE_MEM,
	};
	struct platform_device *dev =
		platform_device_register_simple("rtc-ds1742", -1, &res, 1);
	return IS_ERR(dev) ? PTR_ERR(dev) : 0;
}

static int __init rbtx4927_ne_init(void)
{
	struct resource res[] = {
		{
			.start	= RBTX4927_RTL_8019_BASE,
			.end	= RBTX4927_RTL_8019_BASE + 0x20 - 1,
			.flags	= IORESOURCE_IO,
		}, {
			.start	= RBTX4927_RTL_8019_IRQ,
			.flags	= IORESOURCE_IRQ,
		}
	};
	struct platform_device *dev =
		platform_device_register_simple("ne", -1,
						res, ARRAY_SIZE(res));
	return IS_ERR(dev) ? PTR_ERR(dev) : 0;
}

/* Watchdog support */

static int __init txx9_wdt_init(unsigned long base)
{
	struct resource res = {
		.start	= base,
		.end	= base + 0x100 - 1,
		.flags	= IORESOURCE_MEM,
	};
	struct platform_device *dev =
		platform_device_register_simple("txx9wdt", -1, &res, 1);
	return IS_ERR(dev) ? PTR_ERR(dev) : 0;
}

static int __init rbtx4927_wdt_init(void)
{
	return txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL);
}

static void __init rbtx4927_device_init(void)
{
	toshiba_rbtx4927_rtc_init();
	rbtx4927_ne_init();
	rbtx4927_wdt_init();
}

struct txx9_board_vec rbtx4927_vec __initdata = {
	.system = "Toshiba RBTX4927",
	.prom_init = rbtx4927_prom_init,
	.mem_setup = rbtx4927_mem_setup,
	.irq_setup = rbtx4927_irq_setup,
	.time_init = rbtx4927_time_init,
	.device_init = rbtx4927_device_init,
	.arch_init = rbtx4927_arch_init,
#ifdef CONFIG_PCI
	.pci_map_irq = rbtx4927_pci_map_irq,
#endif
};
struct txx9_board_vec rbtx4937_vec __initdata = {
	.system = "Toshiba RBTX4937",
	.prom_init = rbtx4927_prom_init,
	.mem_setup = rbtx4927_mem_setup,
	.irq_setup = rbtx4927_irq_setup,
	.time_init = rbtx4927_time_init,
	.device_init = rbtx4927_device_init,
	.arch_init = rbtx4937_arch_init,
#ifdef CONFIG_PCI
	.pci_map_irq = rbtx4927_pci_map_irq,
#endif
};
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Toshiba rbtx4927 specific setup
	3	*
	4	* Author: MontaVista Software, Inc.
	5	* source@mvista.com
	6	*
	7	* Copyright 2001-2002 MontaVista Software Inc.
	8	*
	9	* Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org)
	10	* Copyright (C) 2000 RidgeRun, Inc.
	11	* Author: RidgeRun, Inc.
	12	* glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
	13	*
	14	* Copyright 2001 MontaVista Software Inc.
	15	* Author: jsun@mvista.com or jsun@junsun.net
	16	*
	17	* Copyright 2002 MontaVista Software Inc.
	18	* Author: Michael Pruznick, michael_pruznick@mvista.com
	19	*
	20	* Copyright (C) 2000-2001 Toshiba Corporation
	21	*
	22	* Copyright (C) 2004 MontaVista Software Inc.
	23	* Author: Manish Lachwani, mlachwani@mvista.com
	24	*
	25	* This program is free software; you can redistribute it and/or modify it
	26	* under the terms of the GNU General Public License as published by the
	27	* Free Software Foundation; either version 2 of the License, or (at your
	28	* option) any later version.
	29	*
	30	* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
	31	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	32	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
	33	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
	34	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
	35	* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
	36	* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	37	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
	38	* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
	39	* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	40	*
	41	* You should have received a copy of the GNU General Public License along
	42	* with this program; if not, write to the Free Software Foundation, Inc.,
	43	* 675 Mass Ave, Cambridge, MA 02139, USA.
	44	*/
1da177e4 LT	45	#include <linux/init.h>
	46	#include <linux/kernel.h>
	47	#include <linux/types.h>
1da177e4	48	#include <linux/ioport.h>
1da177e4	49	#include <linux/interrupt.h>
fcdb27ad	50	#include <linux/pm.h>
a0574e04	51	#include <linux/platform_device.h>
89d63fe1	52	#include <linux/delay.h>
1da177e4	53	#include <asm/io.h>
1da177e4	54	#include <asm/processor.h>
1da177e4	55	#include <asm/reboot.h>
89d63fe1 AN	56	#include <asm/txx9/generic.h>
89d63fe1 AN	57	#include <asm/txx9/pci.h>
22b1d707	58	#include <asm/txx9/rbtx4927.h>
89d63fe1	59	#include <asm/txx9/tx4938.h> /* for TX4937 */
1da177e4	60
1da177e4	61	#ifdef CONFIG_PCI
89d63fe1	62	static void __init tx4927_pci_setup(void)
1da177e4	63	{
89d63fe1 AN	64	int extarb = !(__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB);
	65	struct pci_controller *c = &txx9_primary_pcic;
	66
	67	register_pci_controller(c);
	68
	69	if (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66)
	70	txx9_pci_option =
	71	(txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) \|
	72	TXX9_PCI_OPT_CLK_66; /* already configured */
	73
	74	/* Reset PCI Bus */
	75	writeb(1, rbtx4927_pcireset_addr);
	76	/* Reset PCIC */
	77	txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
	78	if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
	79	TXX9_PCI_OPT_CLK_66)
	80	tx4927_pciclk66_setup();
	81	mdelay(10);
	82	/* clear PCIC reset */
	83	txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
	84	writeb(0, rbtx4927_pcireset_addr);
	85	iob();
	86
	87	tx4927_report_pciclk();
	88	tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
	89	if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
	90	TXX9_PCI_OPT_CLK_AUTO &&
	91	txx9_pci66_check(c, 0, 0)) {
	92	/* Reset PCI Bus */
	93	writeb(1, rbtx4927_pcireset_addr);
	94	/* Reset PCIC */
	95	txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
	96	tx4927_pciclk66_setup();
	97	mdelay(10);
	98	/* clear PCIC reset */
	99	txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
	100	writeb(0, rbtx4927_pcireset_addr);
	101	iob();
	102	/* Reinitialize PCIC */
	103	tx4927_report_pciclk();
	104	tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
	105	}
1da177e4 LT	106	}
1da177e4 LT	107
89d63fe1	108	static void __init tx4937_pci_setup(void)
1da177e4	109	{
89d63fe1 AN	110	int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
	111	struct pci_controller *c = &txx9_primary_pcic;
	112
	113	register_pci_controller(c);
	114
	115	if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
	116	txx9_pci_option =
	117	(txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) \|
	118	TXX9_PCI_OPT_CLK_66; /* already configured */
	119
	120	/* Reset PCI Bus */
	121	writeb(1, rbtx4927_pcireset_addr);
	122	/* Reset PCIC */
	123	txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
	124	if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
	125	TXX9_PCI_OPT_CLK_66)
	126	tx4938_pciclk66_setup();
	127	mdelay(10);
	128	/* clear PCIC reset */
	129	txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
	130	writeb(0, rbtx4927_pcireset_addr);
	131	iob();
	132
	133	tx4938_report_pciclk();
	134	tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
	135	if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
	136	TXX9_PCI_OPT_CLK_AUTO &&
	137	txx9_pci66_check(c, 0, 0)) {
	138	/* Reset PCI Bus */
	139	writeb(1, rbtx4927_pcireset_addr);
	140	/* Reset PCIC */
	141	txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
	142	tx4938_pciclk66_setup();
	143	mdelay(10);
	144	/* clear PCIC reset */
	145	txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
	146	writeb(0, rbtx4927_pcireset_addr);
	147	iob();
	148	/* Reinitialize PCIC */
	149	tx4938_report_pciclk();
	150	tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
1da177e4	151	}
1da177e4 LT	152	}
1da177e4 LT	153
edcaf1a6	154	static void __init rbtx4927_arch_init(void)
1da177e4	155	{
a38c4751 YY	156	tx4927_pci_setup();
	157	}
	158
	159	static void __init rbtx4937_arch_init(void)
	160	{
	161	tx4937_pci_setup();
1da177e4	162	}
edcaf1a6 AN	163	#else
edcaf1a6 AN	164	#define rbtx4927_arch_init NULL
a38c4751	165	#define rbtx4937_arch_init NULL
1da177e4 LT	166	#endif /* CONFIG_PCI */
1da177e4 LT	167
a02eb8da AN	168	static void __noreturn wait_forever(void)
	169	{
	170	while (1)
	171	if (cpu_wait)
	172	(*cpu_wait)();
	173	}
	174
7b226094	175	static void toshiba_rbtx4927_restart(char *command)
1da177e4 LT	176	{
	177	printk(KERN_NOTICE "System Rebooting...\n");
	178
	179	/* enable the s/w reset register */
94a4c329	180	writeb(1, rbtx4927_softresetlock_addr);
1da177e4 LT	181
1da177e4 LT	182	/* wait for enable to be seen */
94a4c329 AN	183	while (!(readb(rbtx4927_softresetlock_addr) & 1))
94a4c329 AN	184	;
1da177e4 LT	185
1da177e4 LT	186	/* do a s/w reset */
94a4c329	187	writeb(1, rbtx4927_softreset_addr);
1da177e4 LT	188
	189	/* do something passive while waiting for reset */
	190	local_irq_disable();
a02eb8da	191	wait_forever();
1da177e4 LT	192	/* no return */
	193	}
	194
7b226094	195	static void toshiba_rbtx4927_halt(void)
1da177e4 LT	196	{
	197	printk(KERN_NOTICE "System Halted\n");
	198	local_irq_disable();
a02eb8da	199	wait_forever();
1da177e4 LT	200	/* no return */
	201	}
	202
7b226094	203	static void toshiba_rbtx4927_power_off(void)
1da177e4 LT	204	{
	205	toshiba_rbtx4927_halt();
	206	/* no return */
	207	}
	208
94a4c329 AN	209	static void __init rbtx4927_clock_init(void);
	210	static void __init rbtx4937_clock_init(void);
	211
edcaf1a6	212	static void __init rbtx4927_mem_setup(void)
1da177e4	213	{
a02eb8da	214	u32 cp0_config;
1da177e4 LT	215	char *argptr;
1da177e4 LT	216
1da177e4	217	/* f/w leaves this on at startup */
1da177e4 LT	218	clear_c0_status(ST0_ERL);
	219
	220	/* enable caches -- HCP5 does this, pmon does not */
1da177e4 LT	221	cp0_config = read_c0_config();
	222	cp0_config = cp0_config & ~(TX49_CONF_IC \| TX49_CONF_DC);
	223	write_c0_config(cp0_config);
	224
94a4c329 AN	225	if (TX4927_REV_PCODE() == 0x4927) {
	226	rbtx4927_clock_init();
	227	tx4927_setup();
	228	} else {
	229	rbtx4937_clock_init();
	230	tx4938_setup();
	231	}
1da177e4	232
1da177e4 LT	233	_machine_restart = toshiba_rbtx4927_restart;
1da177e4 LT	234	_machine_halt = toshiba_rbtx4927_halt;
fcdb27ad	235	pm_power_off = toshiba_rbtx4927_power_off;
1da177e4 LT	236
1da177e4 LT	237	#ifdef CONFIG_PCI
89d63fe1 AN	238	txx9_alloc_pci_controller(&txx9_primary_pcic,
	239	RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE,
	240	RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE);
	241	#else
	242	set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET);
	243	#endif
1da177e4	244
94a4c329	245	tx4927_setup_serial();
1da177e4 LT	246	#ifdef CONFIG_SERIAL_TXX9_CONSOLE
	247	argptr = prom_getcmdline();
	248	if (strstr(argptr, "console=") == NULL) {
	249	strcat(argptr, " console=ttyS0,38400");
	250	}
	251	#endif
	252
	253	#ifdef CONFIG_ROOT_NFS
	254	argptr = prom_getcmdline();
	255	if (strstr(argptr, "root=") == NULL) {
	256	strcat(argptr, " root=/dev/nfs rw");
	257	}
	258	#endif
	259
1da177e4 LT	260	#ifdef CONFIG_IP_PNP
	261	argptr = prom_getcmdline();
	262	if (strstr(argptr, "ip=") == NULL) {
	263	strcat(argptr, " ip=any");
	264	}
	265	#endif
1da177e4 LT	266	}
1da177e4 LT	267
94a4c329	268	static void __init rbtx4927_clock_init(void)
1da177e4	269	{
a00fb669 YY	270	/*
	271	* ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
	272	*
	273	* For TX4927:
	274	* PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1).
	275	* CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
	276	* CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
	277	* CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
	278	* CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
	279	* i.e. S9[3]: ON (83MHz), OFF (100MHz)
b6c40536 YY	280	*/
	281	switch ((unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg) &
	282	TX4927_CCFG_PCIDIVMODE_MASK) {
	283	case TX4927_CCFG_PCIDIVMODE_2_5:
	284	case TX4927_CCFG_PCIDIVMODE_5:
	285	txx9_cpu_clock = 166666666; /* 166MHz */
	286	break;
	287	default:
	288	txx9_cpu_clock = 200000000; /* 200MHz */
	289	}
b6c40536 YY	290	}
b6c40536 YY	291
94a4c329	292	static void __init rbtx4937_clock_init(void)
b6c40536 YY	293	{
	294	/*
	295	* ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
a00fb669 YY	296	*
	297	* For TX4937:
	298	* PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1)
	299	* PCIDIVMODE[10] is 0.
	300	* CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8)
	301	* CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4)
	302	* CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9)
	303	* CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5)
	304	* CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10)
	305	* CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5)
	306	*/
b6c40536 YY	307	switch ((unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg) &
	308	TX4938_CCFG_PCIDIVMODE_MASK) {
	309	case TX4938_CCFG_PCIDIVMODE_8:
	310	case TX4938_CCFG_PCIDIVMODE_4:
	311	txx9_cpu_clock = 266666666; /* 266MHz */
	312	break;
	313	case TX4938_CCFG_PCIDIVMODE_9:
	314	case TX4938_CCFG_PCIDIVMODE_4_5:
	315	txx9_cpu_clock = 300000000; /* 300MHz */
	316	break;
	317	default:
	318	txx9_cpu_clock = 333333333; /* 333MHz */
	319	}
94a4c329	320	}
a00fb669	321
94a4c329 AN	322	static void __init rbtx4927_time_init(void)
	323	{
	324	tx4927_time_init(0);
1da177e4 LT	325	}
1da177e4 LT	326
a0574e04 AN	327	static int __init toshiba_rbtx4927_rtc_init(void)
a0574e04 AN	328	{
94a4c329 AN	329	struct resource res = {
	330	.start = RBTX4927_BRAMRTC_BASE - IO_BASE,
	331	.end = RBTX4927_BRAMRTC_BASE - IO_BASE + 0x800 - 1,
a0574e04 AN	332	.flags = IORESOURCE_MEM,
	333	};
	334	struct platform_device *dev =
a95e23a2	335	platform_device_register_simple("rtc-ds1742", -1, &res, 1);
a0574e04 AN	336	return IS_ERR(dev) ? PTR_ERR(dev) : 0;
a0574e04 AN	337	}
57e386ce AN	338
	339	static int __init rbtx4927_ne_init(void)
	340	{
94a4c329	341	struct resource res[] = {
57e386ce AN	342	{
	343	.start = RBTX4927_RTL_8019_BASE,
	344	.end = RBTX4927_RTL_8019_BASE + 0x20 - 1,
	345	.flags = IORESOURCE_IO,
	346	}, {
	347	.start = RBTX4927_RTL_8019_IRQ,
	348	.flags = IORESOURCE_IRQ,
	349	}
	350	};
	351	struct platform_device *dev =
	352	platform_device_register_simple("ne", -1,
	353	res, ARRAY_SIZE(res));
	354	return IS_ERR(dev) ? PTR_ERR(dev) : 0;
	355	}
2064ba23 AN	356
	357	/* Watchdog support */
	358
	359	static int __init txx9_wdt_init(unsigned long base)
	360	{
	361	struct resource res = {
	362	.start = base,
	363	.end = base + 0x100 - 1,
	364	.flags = IORESOURCE_MEM,
	365	};
	366	struct platform_device *dev =
	367	platform_device_register_simple("txx9wdt", -1, &res, 1);
	368	return IS_ERR(dev) ? PTR_ERR(dev) : 0;
	369	}
	370
	371	static int __init rbtx4927_wdt_init(void)
	372	{
	373	return txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL);
	374	}
2064ba23	375
edcaf1a6	376	static void __init rbtx4927_device_init(void)
2064ba23	377	{
edcaf1a6 AN	378	toshiba_rbtx4927_rtc_init();
	379	rbtx4927_ne_init();
	380	rbtx4927_wdt_init();
2064ba23	381	}
2064ba23	382
edcaf1a6	383	struct txx9_board_vec rbtx4927_vec __initdata = {
edcaf1a6 AN	384	.system = "Toshiba RBTX4927",
	385	.prom_init = rbtx4927_prom_init,
	386	.mem_setup = rbtx4927_mem_setup,
	387	.irq_setup = rbtx4927_irq_setup,
	388	.time_init = rbtx4927_time_init,
	389	.device_init = rbtx4927_device_init,
	390	.arch_init = rbtx4927_arch_init,
	391	#ifdef CONFIG_PCI
	392	.pci_map_irq = rbtx4927_pci_map_irq,
	393	#endif
	394	};
	395	struct txx9_board_vec rbtx4937_vec __initdata = {
edcaf1a6 AN	396	.system = "Toshiba RBTX4937",
	397	.prom_init = rbtx4927_prom_init,
	398	.mem_setup = rbtx4927_mem_setup,
	399	.irq_setup = rbtx4927_irq_setup,
94a4c329	400	.time_init = rbtx4927_time_init,
edcaf1a6	401	.device_init = rbtx4927_device_init,
a38c4751	402	.arch_init = rbtx4937_arch_init,
edcaf1a6 AN	403	#ifdef CONFIG_PCI
	404	.pci_map_irq = rbtx4927_pci_map_irq,
	405	#endif
	406	};