Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Toshiba rbtx4927 specific setup | |
3 | * | |
4 | * Author: MontaVista Software, Inc. | |
5 | * source@mvista.com | |
6 | * | |
7 | * Copyright 2001-2002 MontaVista Software Inc. | |
8 | * | |
9 | * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org) | |
10 | * Copyright (C) 2000 RidgeRun, Inc. | |
11 | * Author: RidgeRun, Inc. | |
12 | * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com | |
13 | * | |
14 | * Copyright 2001 MontaVista Software Inc. | |
15 | * Author: jsun@mvista.com or jsun@junsun.net | |
16 | * | |
17 | * Copyright 2002 MontaVista Software Inc. | |
18 | * Author: Michael Pruznick, michael_pruznick@mvista.com | |
19 | * | |
20 | * Copyright (C) 2000-2001 Toshiba Corporation | |
21 | * | |
22 | * Copyright (C) 2004 MontaVista Software Inc. | |
23 | * Author: Manish Lachwani, mlachwani@mvista.com | |
24 | * | |
25 | * This program is free software; you can redistribute it and/or modify it | |
26 | * under the terms of the GNU General Public License as published by the | |
27 | * Free Software Foundation; either version 2 of the License, or (at your | |
28 | * option) any later version. | |
29 | * | |
30 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
31 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
32 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. | |
33 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
34 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, | |
35 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS | |
36 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
37 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR | |
38 | * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE | |
39 | * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
40 | * | |
41 | * You should have received a copy of the GNU General Public License along | |
42 | * with this program; if not, write to the Free Software Foundation, Inc., | |
43 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
44 | */ | |
1da177e4 LT |
45 | #include <linux/init.h> |
46 | #include <linux/kernel.h> | |
47 | #include <linux/types.h> | |
1da177e4 | 48 | #include <linux/ioport.h> |
a0574e04 | 49 | #include <linux/platform_device.h> |
89d63fe1 | 50 | #include <linux/delay.h> |
f96a3383 | 51 | #include <linux/gpio.h> |
864cbf80 | 52 | #include <linux/leds.h> |
1da177e4 | 53 | #include <asm/io.h> |
1da177e4 | 54 | #include <asm/reboot.h> |
89d63fe1 AN |
55 | #include <asm/txx9/generic.h> |
56 | #include <asm/txx9/pci.h> | |
22b1d707 | 57 | #include <asm/txx9/rbtx4927.h> |
89d63fe1 | 58 | #include <asm/txx9/tx4938.h> /* for TX4937 */ |
1da177e4 | 59 | |
1da177e4 | 60 | #ifdef CONFIG_PCI |
89d63fe1 | 61 | static void __init tx4927_pci_setup(void) |
1da177e4 | 62 | { |
89d63fe1 AN |
63 | int extarb = !(__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB); |
64 | struct pci_controller *c = &txx9_primary_pcic; | |
65 | ||
66 | register_pci_controller(c); | |
67 | ||
68 | if (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66) | |
69 | txx9_pci_option = | |
70 | (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) | | |
71 | TXX9_PCI_OPT_CLK_66; /* already configured */ | |
72 | ||
73 | /* Reset PCI Bus */ | |
74 | writeb(1, rbtx4927_pcireset_addr); | |
75 | /* Reset PCIC */ | |
76 | txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST); | |
77 | if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) == | |
78 | TXX9_PCI_OPT_CLK_66) | |
79 | tx4927_pciclk66_setup(); | |
80 | mdelay(10); | |
81 | /* clear PCIC reset */ | |
82 | txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST); | |
83 | writeb(0, rbtx4927_pcireset_addr); | |
84 | iob(); | |
85 | ||
86 | tx4927_report_pciclk(); | |
87 | tx4927_pcic_setup(tx4927_pcicptr, c, extarb); | |
88 | if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) == | |
89 | TXX9_PCI_OPT_CLK_AUTO && | |
90 | txx9_pci66_check(c, 0, 0)) { | |
91 | /* Reset PCI Bus */ | |
92 | writeb(1, rbtx4927_pcireset_addr); | |
93 | /* Reset PCIC */ | |
94 | txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST); | |
95 | tx4927_pciclk66_setup(); | |
96 | mdelay(10); | |
97 | /* clear PCIC reset */ | |
98 | txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST); | |
99 | writeb(0, rbtx4927_pcireset_addr); | |
100 | iob(); | |
101 | /* Reinitialize PCIC */ | |
102 | tx4927_report_pciclk(); | |
103 | tx4927_pcic_setup(tx4927_pcicptr, c, extarb); | |
104 | } | |
455cc256 | 105 | tx4927_setup_pcierr_irq(); |
1da177e4 LT |
106 | } |
107 | ||
89d63fe1 | 108 | static void __init tx4937_pci_setup(void) |
1da177e4 | 109 | { |
89d63fe1 AN |
110 | int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB); |
111 | struct pci_controller *c = &txx9_primary_pcic; | |
112 | ||
113 | register_pci_controller(c); | |
114 | ||
115 | if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66) | |
116 | txx9_pci_option = | |
117 | (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) | | |
118 | TXX9_PCI_OPT_CLK_66; /* already configured */ | |
119 | ||
120 | /* Reset PCI Bus */ | |
121 | writeb(1, rbtx4927_pcireset_addr); | |
122 | /* Reset PCIC */ | |
123 | txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); | |
124 | if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) == | |
125 | TXX9_PCI_OPT_CLK_66) | |
126 | tx4938_pciclk66_setup(); | |
127 | mdelay(10); | |
128 | /* clear PCIC reset */ | |
129 | txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); | |
130 | writeb(0, rbtx4927_pcireset_addr); | |
131 | iob(); | |
132 | ||
133 | tx4938_report_pciclk(); | |
134 | tx4927_pcic_setup(tx4938_pcicptr, c, extarb); | |
135 | if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) == | |
136 | TXX9_PCI_OPT_CLK_AUTO && | |
137 | txx9_pci66_check(c, 0, 0)) { | |
138 | /* Reset PCI Bus */ | |
139 | writeb(1, rbtx4927_pcireset_addr); | |
140 | /* Reset PCIC */ | |
141 | txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); | |
142 | tx4938_pciclk66_setup(); | |
143 | mdelay(10); | |
144 | /* clear PCIC reset */ | |
145 | txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST); | |
146 | writeb(0, rbtx4927_pcireset_addr); | |
147 | iob(); | |
148 | /* Reinitialize PCIC */ | |
149 | tx4938_report_pciclk(); | |
150 | tx4927_pcic_setup(tx4938_pcicptr, c, extarb); | |
1da177e4 | 151 | } |
455cc256 | 152 | tx4938_setup_pcierr_irq(); |
1da177e4 LT |
153 | } |
154 | ||
edcaf1a6 | 155 | static void __init rbtx4927_arch_init(void) |
1da177e4 | 156 | { |
a38c4751 YY |
157 | tx4927_pci_setup(); |
158 | } | |
159 | ||
160 | static void __init rbtx4937_arch_init(void) | |
161 | { | |
162 | tx4937_pci_setup(); | |
1da177e4 | 163 | } |
edcaf1a6 AN |
164 | #else |
165 | #define rbtx4927_arch_init NULL | |
a38c4751 | 166 | #define rbtx4937_arch_init NULL |
1da177e4 LT |
167 | #endif /* CONFIG_PCI */ |
168 | ||
7b226094 | 169 | static void toshiba_rbtx4927_restart(char *command) |
1da177e4 | 170 | { |
1da177e4 | 171 | /* enable the s/w reset register */ |
94a4c329 | 172 | writeb(1, rbtx4927_softresetlock_addr); |
1da177e4 LT |
173 | |
174 | /* wait for enable to be seen */ | |
94a4c329 AN |
175 | while (!(readb(rbtx4927_softresetlock_addr) & 1)) |
176 | ; | |
1da177e4 LT |
177 | |
178 | /* do a s/w reset */ | |
94a4c329 | 179 | writeb(1, rbtx4927_softreset_addr); |
1da177e4 | 180 | |
a49297e8 AN |
181 | /* fallback */ |
182 | (*_machine_halt)(); | |
1da177e4 LT |
183 | } |
184 | ||
94a4c329 AN |
185 | static void __init rbtx4927_clock_init(void); |
186 | static void __init rbtx4937_clock_init(void); | |
187 | ||
edcaf1a6 | 188 | static void __init rbtx4927_mem_setup(void) |
1da177e4 | 189 | { |
1da177e4 LT |
190 | char *argptr; |
191 | ||
94a4c329 AN |
192 | if (TX4927_REV_PCODE() == 0x4927) { |
193 | rbtx4927_clock_init(); | |
194 | tx4927_setup(); | |
195 | } else { | |
196 | rbtx4937_clock_init(); | |
197 | tx4938_setup(); | |
198 | } | |
1da177e4 | 199 | |
1da177e4 | 200 | _machine_restart = toshiba_rbtx4927_restart; |
1da177e4 LT |
201 | |
202 | #ifdef CONFIG_PCI | |
89d63fe1 AN |
203 | txx9_alloc_pci_controller(&txx9_primary_pcic, |
204 | RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE, | |
205 | RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE); | |
07517529 | 206 | txx9_board_pcibios_setup = tx4927_pcibios_setup; |
89d63fe1 AN |
207 | #else |
208 | set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET); | |
209 | #endif | |
1da177e4 | 210 | |
f96a3383 AN |
211 | /* TX4927-SIO DTR on (PIO[15]) */ |
212 | gpio_request(15, "sio-dtr"); | |
213 | gpio_direction_output(15, 1); | |
f96a3383 | 214 | |
7779a5e0 | 215 | tx4927_sio_init(0, 0); |
1da177e4 | 216 | #ifdef CONFIG_SERIAL_TXX9_CONSOLE |
bb72f1f7 AN |
217 | argptr = prom_getcmdline(); |
218 | if (!strstr(argptr, "console=")) | |
219 | strcat(argptr, " console=ttyS0,38400"); | |
1da177e4 | 220 | #endif |
1da177e4 LT |
221 | } |
222 | ||
94a4c329 | 223 | static void __init rbtx4927_clock_init(void) |
1da177e4 | 224 | { |
a00fb669 YY |
225 | /* |
226 | * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. | |
227 | * | |
228 | * For TX4927: | |
229 | * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1). | |
230 | * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5) | |
231 | * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3) | |
232 | * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5) | |
233 | * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6) | |
234 | * i.e. S9[3]: ON (83MHz), OFF (100MHz) | |
b6c40536 YY |
235 | */ |
236 | switch ((unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg) & | |
237 | TX4927_CCFG_PCIDIVMODE_MASK) { | |
238 | case TX4927_CCFG_PCIDIVMODE_2_5: | |
239 | case TX4927_CCFG_PCIDIVMODE_5: | |
240 | txx9_cpu_clock = 166666666; /* 166MHz */ | |
241 | break; | |
242 | default: | |
243 | txx9_cpu_clock = 200000000; /* 200MHz */ | |
244 | } | |
b6c40536 YY |
245 | } |
246 | ||
94a4c329 | 247 | static void __init rbtx4937_clock_init(void) |
b6c40536 YY |
248 | { |
249 | /* | |
250 | * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. | |
a00fb669 YY |
251 | * |
252 | * For TX4937: | |
253 | * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1) | |
254 | * PCIDIVMODE[10] is 0. | |
255 | * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8) | |
256 | * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4) | |
257 | * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9) | |
258 | * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5) | |
259 | * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10) | |
260 | * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5) | |
261 | */ | |
b6c40536 YY |
262 | switch ((unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg) & |
263 | TX4938_CCFG_PCIDIVMODE_MASK) { | |
264 | case TX4938_CCFG_PCIDIVMODE_8: | |
265 | case TX4938_CCFG_PCIDIVMODE_4: | |
266 | txx9_cpu_clock = 266666666; /* 266MHz */ | |
267 | break; | |
268 | case TX4938_CCFG_PCIDIVMODE_9: | |
269 | case TX4938_CCFG_PCIDIVMODE_4_5: | |
270 | txx9_cpu_clock = 300000000; /* 300MHz */ | |
271 | break; | |
272 | default: | |
273 | txx9_cpu_clock = 333333333; /* 333MHz */ | |
274 | } | |
94a4c329 | 275 | } |
a00fb669 | 276 | |
94a4c329 AN |
277 | static void __init rbtx4927_time_init(void) |
278 | { | |
279 | tx4927_time_init(0); | |
1da177e4 LT |
280 | } |
281 | ||
bb72f1f7 | 282 | static void __init toshiba_rbtx4927_rtc_init(void) |
a0574e04 | 283 | { |
94a4c329 AN |
284 | struct resource res = { |
285 | .start = RBTX4927_BRAMRTC_BASE - IO_BASE, | |
286 | .end = RBTX4927_BRAMRTC_BASE - IO_BASE + 0x800 - 1, | |
a0574e04 AN |
287 | .flags = IORESOURCE_MEM, |
288 | }; | |
bb72f1f7 | 289 | platform_device_register_simple("rtc-ds1742", -1, &res, 1); |
a0574e04 | 290 | } |
57e386ce | 291 | |
bb72f1f7 | 292 | static void __init rbtx4927_ne_init(void) |
57e386ce | 293 | { |
94a4c329 | 294 | struct resource res[] = { |
57e386ce AN |
295 | { |
296 | .start = RBTX4927_RTL_8019_BASE, | |
297 | .end = RBTX4927_RTL_8019_BASE + 0x20 - 1, | |
298 | .flags = IORESOURCE_IO, | |
299 | }, { | |
300 | .start = RBTX4927_RTL_8019_IRQ, | |
301 | .flags = IORESOURCE_IRQ, | |
302 | } | |
303 | }; | |
bb72f1f7 | 304 | platform_device_register_simple("ne", -1, res, ARRAY_SIZE(res)); |
57e386ce | 305 | } |
2064ba23 | 306 | |
51f607c7 AN |
307 | static void __init rbtx4927_mtd_init(void) |
308 | { | |
309 | int i; | |
310 | ||
311 | for (i = 0; i < 2; i++) | |
312 | tx4927_mtd_init(i); | |
313 | } | |
314 | ||
864cbf80 AN |
315 | static void __init rbtx4927_gpioled_init(void) |
316 | { | |
317 | static struct gpio_led leds[] = { | |
318 | { .name = "gpioled:green:0", .gpio = 0, .active_low = 1, }, | |
319 | { .name = "gpioled:green:1", .gpio = 1, .active_low = 1, }, | |
320 | }; | |
321 | static struct gpio_led_platform_data pdata = { | |
322 | .num_leds = ARRAY_SIZE(leds), | |
323 | .leds = leds, | |
324 | }; | |
325 | struct platform_device *pdev = platform_device_alloc("leds-gpio", 0); | |
326 | ||
327 | if (!pdev) | |
328 | return; | |
329 | pdev->dev.platform_data = &pdata; | |
330 | if (platform_device_add(pdev)) | |
331 | platform_device_put(pdev); | |
332 | } | |
333 | ||
edcaf1a6 | 334 | static void __init rbtx4927_device_init(void) |
2064ba23 | 335 | { |
edcaf1a6 AN |
336 | toshiba_rbtx4927_rtc_init(); |
337 | rbtx4927_ne_init(); | |
68314725 | 338 | tx4927_wdt_init(); |
51f607c7 | 339 | rbtx4927_mtd_init(); |
ae027ead | 340 | txx9_iocled_init(RBTX4927_LED_ADDR - IO_BASE, -1, 3, 1, "green", NULL); |
864cbf80 | 341 | rbtx4927_gpioled_init(); |
2064ba23 | 342 | } |
2064ba23 | 343 | |
edcaf1a6 | 344 | struct txx9_board_vec rbtx4927_vec __initdata = { |
edcaf1a6 AN |
345 | .system = "Toshiba RBTX4927", |
346 | .prom_init = rbtx4927_prom_init, | |
347 | .mem_setup = rbtx4927_mem_setup, | |
348 | .irq_setup = rbtx4927_irq_setup, | |
349 | .time_init = rbtx4927_time_init, | |
350 | .device_init = rbtx4927_device_init, | |
351 | .arch_init = rbtx4927_arch_init, | |
352 | #ifdef CONFIG_PCI | |
353 | .pci_map_irq = rbtx4927_pci_map_irq, | |
354 | #endif | |
355 | }; | |
356 | struct txx9_board_vec rbtx4937_vec __initdata = { | |
edcaf1a6 AN |
357 | .system = "Toshiba RBTX4937", |
358 | .prom_init = rbtx4927_prom_init, | |
359 | .mem_setup = rbtx4927_mem_setup, | |
360 | .irq_setup = rbtx4927_irq_setup, | |
94a4c329 | 361 | .time_init = rbtx4927_time_init, |
edcaf1a6 | 362 | .device_init = rbtx4927_device_init, |
a38c4751 | 363 | .arch_init = rbtx4937_arch_init, |
edcaf1a6 AN |
364 | #ifdef CONFIG_PCI |
365 | .pci_map_irq = rbtx4927_pci_map_irq, | |
366 | #endif | |
367 | }; |