[deliverable/linux.git] / arch / mips / txx9 / rbtx4927 / setup.c

/*
 * Toshiba rbtx4927 specific setup
 *
 * Author: MontaVista Software, Inc.
 *         source@mvista.com
 *
 * Copyright 2001-2002 MontaVista Software Inc.
 *
 * Copyright (C) 1996, 97, 2001, 04  Ralf Baechle (ralf@linux-mips.org)
 * Copyright (C) 2000 RidgeRun, Inc.
 * Author: RidgeRun, Inc.
 *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
 *
 * Copyright 2001 MontaVista Software Inc.
 * Author: jsun@mvista.com or jsun@junsun.net
 *
 * Copyright 2002 MontaVista Software Inc.
 * Author: Michael Pruznick, michael_pruznick@mvista.com
 *
 * Copyright (C) 2000-2001 Toshiba Corporation
 *
 * Copyright (C) 2004 MontaVista Software Inc.
 * Author: Manish Lachwani, mlachwani@mvista.com
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the
 *  Free Software Foundation; either version 2 of the License, or (at your
 *  option) any later version.
 *
 *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
 *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
 *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
 *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/pm.h>
#include <linux/platform_device.h>
#include <linux/delay.h>

#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/reboot.h>
#include <asm/time.h>
#include <asm/txx9tmr.h>
#include <asm/txx9/generic.h>
#include <asm/txx9/pci.h>
#include <asm/txx9/rbtx4927.h>
#include <asm/txx9/tx4938.h>	/* for TX4937 */
#ifdef CONFIG_SERIAL_TXX9
#include <linux/serial_core.h>
#endif

/* These functions are used for rebooting or halting the machine*/
extern void toshiba_rbtx4927_restart(char *command);
extern void toshiba_rbtx4927_halt(void);
extern void toshiba_rbtx4927_power_off(void);
extern void toshiba_rbtx4927_irq_setup(void);

char *prom_getcmdline(void);

static int tx4927_ccfg_toeon = 1;

#ifdef CONFIG_PCI
static void __init tx4927_pci_setup(void)
{
	int extarb = !(__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB);
	struct pci_controller *c = &txx9_primary_pcic;

	register_pci_controller(c);

	if (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66)
		txx9_pci_option =
			(txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
			TXX9_PCI_OPT_CLK_66; /* already configured */

	/* Reset PCI Bus */
	writeb(1, rbtx4927_pcireset_addr);
	/* Reset PCIC */
	txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
	if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
	    TXX9_PCI_OPT_CLK_66)
		tx4927_pciclk66_setup();
	mdelay(10);
	/* clear PCIC reset */
	txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
	writeb(0, rbtx4927_pcireset_addr);
	iob();

	tx4927_report_pciclk();
	tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
	if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
	    TXX9_PCI_OPT_CLK_AUTO &&
	    txx9_pci66_check(c, 0, 0)) {
		/* Reset PCI Bus */
		writeb(1, rbtx4927_pcireset_addr);
		/* Reset PCIC */
		txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
		tx4927_pciclk66_setup();
		mdelay(10);
		/* clear PCIC reset */
		txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
		writeb(0, rbtx4927_pcireset_addr);
		iob();
		/* Reinitialize PCIC */
		tx4927_report_pciclk();
		tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
	}
}

static void __init tx4937_pci_setup(void)
{
	int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
	struct pci_controller *c = &txx9_primary_pcic;

	register_pci_controller(c);

	if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
		txx9_pci_option =
			(txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
			TXX9_PCI_OPT_CLK_66; /* already configured */

	/* Reset PCI Bus */
	writeb(1, rbtx4927_pcireset_addr);
	/* Reset PCIC */
	txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
	if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
	    TXX9_PCI_OPT_CLK_66)
		tx4938_pciclk66_setup();
	mdelay(10);
	/* clear PCIC reset */
	txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
	writeb(0, rbtx4927_pcireset_addr);
	iob();

	tx4938_report_pciclk();
	tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
	if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
	    TXX9_PCI_OPT_CLK_AUTO &&
	    txx9_pci66_check(c, 0, 0)) {
		/* Reset PCI Bus */
		writeb(1, rbtx4927_pcireset_addr);
		/* Reset PCIC */
		txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
		tx4938_pciclk66_setup();
		mdelay(10);
		/* clear PCIC reset */
		txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
		writeb(0, rbtx4927_pcireset_addr);
		iob();
		/* Reinitialize PCIC */
		tx4938_report_pciclk();
		tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
	}
}

static void __init rbtx4927_arch_init(void)
{
	tx4927_pci_setup();
}

static void __init rbtx4937_arch_init(void)
{
	tx4937_pci_setup();
}
#else
#define rbtx4927_arch_init NULL
#define rbtx4937_arch_init NULL
#endif /* CONFIG_PCI */

static void __noreturn wait_forever(void)
{
	while (1)
		if (cpu_wait)
			(*cpu_wait)();
}

void toshiba_rbtx4927_restart(char *command)
{
	printk(KERN_NOTICE "System Rebooting...\n");

	/* enable the s/w reset register */
	writeb(RBTX4927_SW_RESET_ENABLE_SET, RBTX4927_SW_RESET_ENABLE);

	/* wait for enable to be seen */
	while ((readb(RBTX4927_SW_RESET_ENABLE) &
		RBTX4927_SW_RESET_ENABLE_SET) == 0x00);

	/* do a s/w reset */
	writeb(RBTX4927_SW_RESET_DO_SET, RBTX4927_SW_RESET_DO);

	/* do something passive while waiting for reset */
	local_irq_disable();
	wait_forever();
	/* no return */
}

void toshiba_rbtx4927_halt(void)
{
	printk(KERN_NOTICE "System Halted\n");
	local_irq_disable();
	wait_forever();
	/* no return */
}

void toshiba_rbtx4927_power_off(void)
{
	toshiba_rbtx4927_halt();
	/* no return */
}

static void __init rbtx4927_mem_setup(void)
{
	int i;
	u32 cp0_config;
	char *argptr;

	/* f/w leaves this on at startup */
	clear_c0_status(ST0_ERL);

	/* enable caches -- HCP5 does this, pmon does not */
	cp0_config = read_c0_config();
	cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
	write_c0_config(cp0_config);

	ioport_resource.end = 0xffffffff;
	iomem_resource.end = 0xffffffff;

	_machine_restart = toshiba_rbtx4927_restart;
	_machine_halt = toshiba_rbtx4927_halt;
	pm_power_off = toshiba_rbtx4927_power_off;

	for (i = 0; i < TX4927_NR_TMR; i++)
		txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL);

#ifdef CONFIG_PCI
	txx9_alloc_pci_controller(&txx9_primary_pcic,
				  RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE,
				  RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE);
#else
	set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET);
#endif

	/* CCFG */
	/* do reset on watchdog */
	tx4927_ccfg_set(TX4927_CCFG_WR);
	/* enable Timeout BusError */
	if (tx4927_ccfg_toeon)
		tx4927_ccfg_set(TX4927_CCFG_TOE);

#ifdef CONFIG_SERIAL_TXX9
	{
		extern int early_serial_txx9_setup(struct uart_port *port);
		struct uart_port req;
		for(i = 0; i < 2; i++) {
			memset(&req, 0, sizeof(req));
			req.line = i;
			req.iotype = UPIO_MEM;
			req.membase = (char *)(0xff1ff300 + i * 0x100);
			req.mapbase = 0xff1ff300 + i * 0x100;
			req.irq = TXX9_IRQ_BASE + TX4927_IR_SIO(i);
			req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
			req.uartclk = 50000000;
			early_serial_txx9_setup(&req);
		}
	}
#ifdef CONFIG_SERIAL_TXX9_CONSOLE
        argptr = prom_getcmdline();
        if (strstr(argptr, "console=") == NULL) {
                strcat(argptr, " console=ttyS0,38400");
        }
#endif
#endif

#ifdef CONFIG_ROOT_NFS
        argptr = prom_getcmdline();
        if (strstr(argptr, "root=") == NULL) {
                strcat(argptr, " root=/dev/nfs rw");
        }
#endif

#ifdef CONFIG_IP_PNP
        argptr = prom_getcmdline();
        if (strstr(argptr, "ip=") == NULL) {
                strcat(argptr, " ip=any");
        }
#endif
}

static void __init rbtx4927_time_init(void)
{
	/*
	 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
	 *
	 * For TX4927:
	 * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1).
	 * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
	 * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
	 * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
	 * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
	 * i.e. S9[3]: ON (83MHz), OFF (100MHz)
	 *
	 * For TX4937:
	 * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1)
	 * PCIDIVMODE[10] is 0.
	 * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8)
	 * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4)
	 * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9)
	 * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5)
	 * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10)
	 * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5)
	 */
	if (mips_machtype == MACH_TOSHIBA_RBTX4937)
		switch ((unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg) &
			TX4938_CCFG_PCIDIVMODE_MASK) {
		case TX4938_CCFG_PCIDIVMODE_8:
		case TX4938_CCFG_PCIDIVMODE_4:
			txx9_cpu_clock = 266666666;	/* 266MHz */
			break;
		case TX4938_CCFG_PCIDIVMODE_9:
		case TX4938_CCFG_PCIDIVMODE_4_5:
			txx9_cpu_clock = 300000000;	/* 300MHz */
			break;
		default:
			txx9_cpu_clock = 333333333;	/* 333MHz */
		}
	else
		switch ((unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg) &
			TX4927_CCFG_PCIDIVMODE_MASK) {
		case TX4927_CCFG_PCIDIVMODE_2_5:
		case TX4927_CCFG_PCIDIVMODE_5:
			txx9_cpu_clock = 166666666;	/* 166MHz */
			break;
		default:
			txx9_cpu_clock = 200000000;	/* 200MHz */
		}

	/* change default value to udelay/mdelay take reasonable time */
	loops_per_jiffy = txx9_cpu_clock / HZ / 2;

	mips_hpt_frequency = txx9_cpu_clock / 2;
	if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS)
		txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL,
				     TXX9_IRQ_BASE + 17,
				     50000000);
}

static int __init toshiba_rbtx4927_rtc_init(void)
{
	static struct resource __initdata res = {
		.start	= 0x1c010000,
		.end	= 0x1c010000 + 0x800 - 1,
		.flags	= IORESOURCE_MEM,
	};
	struct platform_device *dev =
		platform_device_register_simple("rtc-ds1742", -1, &res, 1);
	return IS_ERR(dev) ? PTR_ERR(dev) : 0;
}

static int __init rbtx4927_ne_init(void)
{
	static struct resource __initdata res[] = {
		{
			.start	= RBTX4927_RTL_8019_BASE,
			.end	= RBTX4927_RTL_8019_BASE + 0x20 - 1,
			.flags	= IORESOURCE_IO,
		}, {
			.start	= RBTX4927_RTL_8019_IRQ,
			.flags	= IORESOURCE_IRQ,
		}
	};
	struct platform_device *dev =
		platform_device_register_simple("ne", -1,
						res, ARRAY_SIZE(res));
	return IS_ERR(dev) ? PTR_ERR(dev) : 0;
}

/* Watchdog support */

static int __init txx9_wdt_init(unsigned long base)
{
	struct resource res = {
		.start	= base,
		.end	= base + 0x100 - 1,
		.flags	= IORESOURCE_MEM,
	};
	struct platform_device *dev =
		platform_device_register_simple("txx9wdt", -1, &res, 1);
	return IS_ERR(dev) ? PTR_ERR(dev) : 0;
}

static int __init rbtx4927_wdt_init(void)
{
	return txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL);
}

static void __init rbtx4927_device_init(void)
{
	toshiba_rbtx4927_rtc_init();
	rbtx4927_ne_init();
	rbtx4927_wdt_init();
}

struct txx9_board_vec rbtx4927_vec __initdata = {
	.type = MACH_TOSHIBA_RBTX4927,
	.system = "Toshiba RBTX4927",
	.prom_init = rbtx4927_prom_init,
	.mem_setup = rbtx4927_mem_setup,
	.irq_setup = rbtx4927_irq_setup,
	.time_init = rbtx4927_time_init,
	.device_init = rbtx4927_device_init,
	.arch_init = rbtx4927_arch_init,
#ifdef CONFIG_PCI
	.pci_map_irq = rbtx4927_pci_map_irq,
#endif
};
struct txx9_board_vec rbtx4937_vec __initdata = {
	.type = MACH_TOSHIBA_RBTX4937,
	.system = "Toshiba RBTX4937",
	.prom_init = rbtx4927_prom_init,
	.mem_setup = rbtx4927_mem_setup,
	.irq_setup = rbtx4927_irq_setup,
	.time_init = rbtx4927_time_init,
	.device_init = rbtx4927_device_init,
	.arch_init = rbtx4937_arch_init,
#ifdef CONFIG_PCI
	.pci_map_irq = rbtx4927_pci_map_irq,
#endif
};
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Toshiba rbtx4927 specific setup
	3	*
	4	* Author: MontaVista Software, Inc.
	5	* source@mvista.com
	6	*
	7	* Copyright 2001-2002 MontaVista Software Inc.
	8	*
	9	* Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org)
	10	* Copyright (C) 2000 RidgeRun, Inc.
	11	* Author: RidgeRun, Inc.
	12	* glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
	13	*
	14	* Copyright 2001 MontaVista Software Inc.
	15	* Author: jsun@mvista.com or jsun@junsun.net
	16	*
	17	* Copyright 2002 MontaVista Software Inc.
	18	* Author: Michael Pruznick, michael_pruznick@mvista.com
	19	*
	20	* Copyright (C) 2000-2001 Toshiba Corporation
	21	*
	22	* Copyright (C) 2004 MontaVista Software Inc.
	23	* Author: Manish Lachwani, mlachwani@mvista.com
	24	*
	25	* This program is free software; you can redistribute it and/or modify it
	26	* under the terms of the GNU General Public License as published by the
	27	* Free Software Foundation; either version 2 of the License, or (at your
	28	* option) any later version.
	29	*
	30	* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
	31	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	32	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
	33	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
	34	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
	35	* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
	36	* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	37	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
	38	* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
	39	* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	40	*
	41	* You should have received a copy of the GNU General Public License along
	42	* with this program; if not, write to the Free Software Foundation, Inc.,
	43	* 675 Mass Ave, Cambridge, MA 02139, USA.
	44	*/
1da177e4 LT	45	#include <linux/init.h>
	46	#include <linux/kernel.h>
	47	#include <linux/types.h>
1da177e4	48	#include <linux/ioport.h>
1da177e4	49	#include <linux/interrupt.h>
fcdb27ad	50	#include <linux/pm.h>
a0574e04	51	#include <linux/platform_device.h>
89d63fe1	52	#include <linux/delay.h>
fcdb27ad	53
1da177e4	54	#include <asm/bootinfo.h>
1da177e4	55	#include <asm/io.h>
1da177e4	56	#include <asm/processor.h>
1da177e4 LT	57	#include <asm/reboot.h>
1da177e4 LT	58	#include <asm/time.h>
229f773e	59	#include <asm/txx9tmr.h>
89d63fe1 AN	60	#include <asm/txx9/generic.h>
89d63fe1 AN	61	#include <asm/txx9/pci.h>
22b1d707	62	#include <asm/txx9/rbtx4927.h>
89d63fe1	63	#include <asm/txx9/tx4938.h> /* for TX4937 */
5eaf7a21	64	#ifdef CONFIG_SERIAL_TXX9
5eaf7a21 RB	65	#include <linux/serial_core.h>
5eaf7a21 RB	66	#endif
1da177e4	67
1da177e4 LT	68	/* These functions are used for rebooting or halting the machine*/
	69	extern void toshiba_rbtx4927_restart(char *command);
	70	extern void toshiba_rbtx4927_halt(void);
	71	extern void toshiba_rbtx4927_power_off(void);
1da177e4 LT	72	extern void toshiba_rbtx4927_irq_setup(void);
1da177e4 LT	73
57340b2b SS	74	char *prom_getcmdline(void);
57340b2b SS	75
1da177e4	76	static int tx4927_ccfg_toeon = 1;
1da177e4	77
1da177e4	78	#ifdef CONFIG_PCI
89d63fe1	79	static void __init tx4927_pci_setup(void)
1da177e4	80	{
89d63fe1 AN	81	int extarb = !(__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB);
	82	struct pci_controller *c = &txx9_primary_pcic;
	83
	84	register_pci_controller(c);
	85
	86	if (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66)
	87	txx9_pci_option =
	88	(txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) \|
	89	TXX9_PCI_OPT_CLK_66; /* already configured */
	90
	91	/* Reset PCI Bus */
	92	writeb(1, rbtx4927_pcireset_addr);
	93	/* Reset PCIC */
	94	txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
	95	if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
	96	TXX9_PCI_OPT_CLK_66)
	97	tx4927_pciclk66_setup();
	98	mdelay(10);
	99	/* clear PCIC reset */
	100	txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
	101	writeb(0, rbtx4927_pcireset_addr);
	102	iob();
	103
	104	tx4927_report_pciclk();
	105	tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
	106	if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
	107	TXX9_PCI_OPT_CLK_AUTO &&
	108	txx9_pci66_check(c, 0, 0)) {
	109	/* Reset PCI Bus */
	110	writeb(1, rbtx4927_pcireset_addr);
	111	/* Reset PCIC */
	112	txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
	113	tx4927_pciclk66_setup();
	114	mdelay(10);
	115	/* clear PCIC reset */
	116	txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
	117	writeb(0, rbtx4927_pcireset_addr);
	118	iob();
	119	/* Reinitialize PCIC */
	120	tx4927_report_pciclk();
	121	tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
	122	}
1da177e4 LT	123	}
1da177e4 LT	124
89d63fe1	125	static void __init tx4937_pci_setup(void)
1da177e4	126	{
89d63fe1 AN	127	int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
	128	struct pci_controller *c = &txx9_primary_pcic;
	129
	130	register_pci_controller(c);
	131
	132	if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
	133	txx9_pci_option =
	134	(txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) \|
	135	TXX9_PCI_OPT_CLK_66; /* already configured */
	136
	137	/* Reset PCI Bus */
	138	writeb(1, rbtx4927_pcireset_addr);
	139	/* Reset PCIC */
	140	txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
	141	if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
	142	TXX9_PCI_OPT_CLK_66)
	143	tx4938_pciclk66_setup();
	144	mdelay(10);
	145	/* clear PCIC reset */
	146	txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
	147	writeb(0, rbtx4927_pcireset_addr);
	148	iob();
	149
	150	tx4938_report_pciclk();
	151	tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
	152	if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
	153	TXX9_PCI_OPT_CLK_AUTO &&
	154	txx9_pci66_check(c, 0, 0)) {
	155	/* Reset PCI Bus */
	156	writeb(1, rbtx4927_pcireset_addr);
	157	/* Reset PCIC */
	158	txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
	159	tx4938_pciclk66_setup();
	160	mdelay(10);
	161	/* clear PCIC reset */
	162	txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
	163	writeb(0, rbtx4927_pcireset_addr);
	164	iob();
	165	/* Reinitialize PCIC */
	166	tx4938_report_pciclk();
	167	tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
1da177e4	168	}
1da177e4 LT	169	}
1da177e4 LT	170
edcaf1a6	171	static void __init rbtx4927_arch_init(void)
1da177e4	172	{
a38c4751 YY	173	tx4927_pci_setup();
	174	}
	175
	176	static void __init rbtx4937_arch_init(void)
	177	{
	178	tx4937_pci_setup();
1da177e4	179	}
edcaf1a6 AN	180	#else
edcaf1a6 AN	181	#define rbtx4927_arch_init NULL
a38c4751	182	#define rbtx4937_arch_init NULL
1da177e4 LT	183	#endif /* CONFIG_PCI */
1da177e4 LT	184
a02eb8da AN	185	static void __noreturn wait_forever(void)
	186	{
	187	while (1)
	188	if (cpu_wait)
	189	(*cpu_wait)();
	190	}
	191
1da177e4 LT	192	void toshiba_rbtx4927_restart(char *command)
	193	{
	194	printk(KERN_NOTICE "System Rebooting...\n");
	195
	196	/* enable the s/w reset register */
a02eb8da	197	writeb(RBTX4927_SW_RESET_ENABLE_SET, RBTX4927_SW_RESET_ENABLE);
1da177e4 LT	198
1da177e4 LT	199	/* wait for enable to be seen */
a02eb8da	200	while ((readb(RBTX4927_SW_RESET_ENABLE) &
1da177e4 LT	201	RBTX4927_SW_RESET_ENABLE_SET) == 0x00);
	202
	203	/* do a s/w reset */
a02eb8da	204	writeb(RBTX4927_SW_RESET_DO_SET, RBTX4927_SW_RESET_DO);
1da177e4 LT	205
	206	/* do something passive while waiting for reset */
	207	local_irq_disable();
a02eb8da	208	wait_forever();
1da177e4 LT	209	/* no return */
	210	}
	211
1da177e4 LT	212	void toshiba_rbtx4927_halt(void)
	213	{
	214	printk(KERN_NOTICE "System Halted\n");
	215	local_irq_disable();
a02eb8da	216	wait_forever();
1da177e4 LT	217	/* no return */
	218	}
	219
	220	void toshiba_rbtx4927_power_off(void)
	221	{
	222	toshiba_rbtx4927_halt();
	223	/* no return */
	224	}
	225
edcaf1a6	226	static void __init rbtx4927_mem_setup(void)
1da177e4	227	{
229f773e	228	int i;
a02eb8da	229	u32 cp0_config;
1da177e4 LT	230	char *argptr;
1da177e4 LT	231
1da177e4	232	/* f/w leaves this on at startup */
1da177e4 LT	233	clear_c0_status(ST0_ERL);
	234
	235	/* enable caches -- HCP5 does this, pmon does not */
1da177e4 LT	236	cp0_config = read_c0_config();
	237	cp0_config = cp0_config & ~(TX49_CONF_IC \| TX49_CONF_DC);
	238	write_c0_config(cp0_config);
	239
1da177e4 LT	240	ioport_resource.end = 0xffffffff;
	241	iomem_resource.end = 0xffffffff;
	242
1da177e4 LT	243	_machine_restart = toshiba_rbtx4927_restart;
1da177e4 LT	244	_machine_halt = toshiba_rbtx4927_halt;
fcdb27ad	245	pm_power_off = toshiba_rbtx4927_power_off;
1da177e4	246
229f773e AN	247	for (i = 0; i < TX4927_NR_TMR; i++)
	248	txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL);
	249
1da177e4	250	#ifdef CONFIG_PCI
89d63fe1 AN	251	txx9_alloc_pci_controller(&txx9_primary_pcic,
	252	RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE,
	253	RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE);
	254	#else
	255	set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET);
	256	#endif
1da177e4	257
1da177e4	258	/* CCFG */
2064ba23	259	/* do reset on watchdog */
89d63fe1	260	tx4927_ccfg_set(TX4927_CCFG_WR);
1da177e4 LT	261	/* enable Timeout BusError */
1da177e4 LT	262	if (tx4927_ccfg_toeon)
89d63fe1	263	tx4927_ccfg_set(TX4927_CCFG_TOE);
1da177e4	264
5eaf7a21 RB	265	#ifdef CONFIG_SERIAL_TXX9
	266	{
	267	extern int early_serial_txx9_setup(struct uart_port *port);
5eaf7a21 RB	268	struct uart_port req;
	269	for(i = 0; i < 2; i++) {
	270	memset(&req, 0, sizeof(req));
	271	req.line = i;
	272	req.iotype = UPIO_MEM;
	273	req.membase = (char )(0xff1ff300 + i 0x100);
	274	req.mapbase = 0xff1ff300 + i * 0x100;
edcaf1a6	275	req.irq = TXX9_IRQ_BASE + TX4927_IR_SIO(i);
5eaf7a21 RB	276	req.flags \|= UPF_BUGGY_UART /HAVE_CTS_LINE/;
	277	req.uartclk = 50000000;
	278	early_serial_txx9_setup(&req);
	279	}
	280	}
1da177e4 LT	281	#ifdef CONFIG_SERIAL_TXX9_CONSOLE
	282	argptr = prom_getcmdline();
	283	if (strstr(argptr, "console=") == NULL) {
	284	strcat(argptr, " console=ttyS0,38400");
	285	}
	286	#endif
5eaf7a21	287	#endif
1da177e4 LT	288
	289	#ifdef CONFIG_ROOT_NFS
	290	argptr = prom_getcmdline();
	291	if (strstr(argptr, "root=") == NULL) {
	292	strcat(argptr, " root=/dev/nfs rw");
	293	}
	294	#endif
	295
1da177e4 LT	296	#ifdef CONFIG_IP_PNP
	297	argptr = prom_getcmdline();
	298	if (strstr(argptr, "ip=") == NULL) {
	299	strcat(argptr, " ip=any");
	300	}
	301	#endif
1da177e4 LT	302	}
1da177e4 LT	303
edcaf1a6	304	static void __init rbtx4927_time_init(void)
1da177e4	305	{
a00fb669 YY	306	/*
	307	* ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
	308	*
	309	* For TX4927:
	310	* PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1).
	311	* CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
	312	* CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
	313	* CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
	314	* CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
	315	* i.e. S9[3]: ON (83MHz), OFF (100MHz)
	316	*
	317	* For TX4937:
	318	* PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1)
	319	* PCIDIVMODE[10] is 0.
	320	* CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8)
	321	* CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4)
	322	* CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9)
	323	* CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5)
	324	* CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10)
	325	* CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5)
	326	*/
	327	if (mips_machtype == MACH_TOSHIBA_RBTX4937)
	328	switch ((unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg) &
	329	TX4938_CCFG_PCIDIVMODE_MASK) {
	330	case TX4938_CCFG_PCIDIVMODE_8:
	331	case TX4938_CCFG_PCIDIVMODE_4:
	332	txx9_cpu_clock = 266666666; /* 266MHz */
	333	break;
	334	case TX4938_CCFG_PCIDIVMODE_9:
	335	case TX4938_CCFG_PCIDIVMODE_4_5:
	336	txx9_cpu_clock = 300000000; /* 300MHz */
	337	break;
	338	default:
	339	txx9_cpu_clock = 333333333; /* 333MHz */
	340	}
	341	else
	342	switch ((unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg) &
	343	TX4927_CCFG_PCIDIVMODE_MASK) {
	344	case TX4927_CCFG_PCIDIVMODE_2_5:
	345	case TX4927_CCFG_PCIDIVMODE_5:
	346	txx9_cpu_clock = 166666666; /* 166MHz */
	347	break;
	348	default:
	349	txx9_cpu_clock = 200000000; /* 200MHz */
	350	}
	351
	352	/* change default value to udelay/mdelay take reasonable time */
	353	loops_per_jiffy = txx9_cpu_clock / HZ / 2;
	354
89d63fe1 AN	355	mips_hpt_frequency = txx9_cpu_clock / 2;
89d63fe1 AN	356	if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS)
229f773e AN	357	txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL,
	358	TXX9_IRQ_BASE + 17,
	359	50000000);
1da177e4 LT	360	}
1da177e4 LT	361
a0574e04 AN	362	static int __init toshiba_rbtx4927_rtc_init(void)
a0574e04 AN	363	{
4614c326	364	static struct resource __initdata res = {
a0574e04 AN	365	.start = 0x1c010000,
	366	.end = 0x1c010000 + 0x800 - 1,
	367	.flags = IORESOURCE_MEM,
	368	};
	369	struct platform_device *dev =
a95e23a2	370	platform_device_register_simple("rtc-ds1742", -1, &res, 1);
a0574e04 AN	371	return IS_ERR(dev) ? PTR_ERR(dev) : 0;
a0574e04 AN	372	}
57e386ce AN	373
	374	static int __init rbtx4927_ne_init(void)
	375	{
	376	static struct resource __initdata res[] = {
	377	{
	378	.start = RBTX4927_RTL_8019_BASE,
	379	.end = RBTX4927_RTL_8019_BASE + 0x20 - 1,
	380	.flags = IORESOURCE_IO,
	381	}, {
	382	.start = RBTX4927_RTL_8019_IRQ,
	383	.flags = IORESOURCE_IRQ,
	384	}
	385	};
	386	struct platform_device *dev =
	387	platform_device_register_simple("ne", -1,
	388	res, ARRAY_SIZE(res));
	389	return IS_ERR(dev) ? PTR_ERR(dev) : 0;
	390	}
2064ba23 AN	391
	392	/* Watchdog support */
	393
	394	static int __init txx9_wdt_init(unsigned long base)
	395	{
	396	struct resource res = {
	397	.start = base,
	398	.end = base + 0x100 - 1,
	399	.flags = IORESOURCE_MEM,
	400	};
	401	struct platform_device *dev =
	402	platform_device_register_simple("txx9wdt", -1, &res, 1);
	403	return IS_ERR(dev) ? PTR_ERR(dev) : 0;
	404	}
	405
	406	static int __init rbtx4927_wdt_init(void)
	407	{
	408	return txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL);
	409	}
2064ba23	410
edcaf1a6	411	static void __init rbtx4927_device_init(void)
2064ba23	412	{
edcaf1a6 AN	413	toshiba_rbtx4927_rtc_init();
	414	rbtx4927_ne_init();
	415	rbtx4927_wdt_init();
2064ba23	416	}
2064ba23	417
edcaf1a6 AN	418	struct txx9_board_vec rbtx4927_vec __initdata = {
	419	.type = MACH_TOSHIBA_RBTX4927,
	420	.system = "Toshiba RBTX4927",
	421	.prom_init = rbtx4927_prom_init,
	422	.mem_setup = rbtx4927_mem_setup,
	423	.irq_setup = rbtx4927_irq_setup,
	424	.time_init = rbtx4927_time_init,
	425	.device_init = rbtx4927_device_init,
	426	.arch_init = rbtx4927_arch_init,
	427	#ifdef CONFIG_PCI
	428	.pci_map_irq = rbtx4927_pci_map_irq,
	429	#endif
	430	};
	431	struct txx9_board_vec rbtx4937_vec __initdata = {
	432	.type = MACH_TOSHIBA_RBTX4937,
	433	.system = "Toshiba RBTX4937",
	434	.prom_init = rbtx4927_prom_init,
	435	.mem_setup = rbtx4927_mem_setup,
	436	.irq_setup = rbtx4927_irq_setup,
	437	.time_init = rbtx4927_time_init,
	438	.device_init = rbtx4927_device_init,
a38c4751	439	.arch_init = rbtx4937_arch_init,
edcaf1a6 AN	440	#ifdef CONFIG_PCI
	441	.pci_map_irq = rbtx4927_pci_map_irq,
	442	#endif
	443	};