[deliverable/linux.git] / arch / mips / txx9 / rbtx4938 / irq.c

/*
 * Toshiba RBTX4938 specific interrupt handlers
 * Copyright (C) 2000-2001 Toshiba Corporation
 *
 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
 * terms of the GNU General Public License version 2. This program is
 * licensed "as is" without any warranty of any kind, whether express
 * or implied.
 *
 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
 */

/*
 * MIPS_CPU_IRQ_BASE+00 Software 0
 * MIPS_CPU_IRQ_BASE+01 Software 1
 * MIPS_CPU_IRQ_BASE+02 Cascade TX4938-CP0
 * MIPS_CPU_IRQ_BASE+03 Multiplexed -- do not use
 * MIPS_CPU_IRQ_BASE+04 Multiplexed -- do not use
 * MIPS_CPU_IRQ_BASE+05 Multiplexed -- do not use
 * MIPS_CPU_IRQ_BASE+06 Multiplexed -- do not use
 * MIPS_CPU_IRQ_BASE+07 CPU TIMER
 *
 * TXX9_IRQ_BASE+00
 * TXX9_IRQ_BASE+01
 * TXX9_IRQ_BASE+02 Cascade RBTX4938-IOC
 * TXX9_IRQ_BASE+03 RBTX4938 RTL-8019AS Ethernet
 * TXX9_IRQ_BASE+04
 * TXX9_IRQ_BASE+05 TX4938 ETH1
 * TXX9_IRQ_BASE+06 TX4938 ETH0
 * TXX9_IRQ_BASE+07
 * TXX9_IRQ_BASE+08 TX4938 SIO 0
 * TXX9_IRQ_BASE+09 TX4938 SIO 1
 * TXX9_IRQ_BASE+10 TX4938 DMA0
 * TXX9_IRQ_BASE+11 TX4938 DMA1
 * TXX9_IRQ_BASE+12 TX4938 DMA2
 * TXX9_IRQ_BASE+13 TX4938 DMA3
 * TXX9_IRQ_BASE+14
 * TXX9_IRQ_BASE+15
 * TXX9_IRQ_BASE+16 TX4938 PCIC
 * TXX9_IRQ_BASE+17 TX4938 TMR0
 * TXX9_IRQ_BASE+18 TX4938 TMR1
 * TXX9_IRQ_BASE+19 TX4938 TMR2
 * TXX9_IRQ_BASE+20
 * TXX9_IRQ_BASE+21
 * TXX9_IRQ_BASE+22 TX4938 PCIERR
 * TXX9_IRQ_BASE+23
 * TXX9_IRQ_BASE+24
 * TXX9_IRQ_BASE+25
 * TXX9_IRQ_BASE+26
 * TXX9_IRQ_BASE+27
 * TXX9_IRQ_BASE+28
 * TXX9_IRQ_BASE+29
 * TXX9_IRQ_BASE+30
 * TXX9_IRQ_BASE+31 TX4938 SPI
 *
 * RBTX4938_IRQ_IOC+00 PCI-D
 * RBTX4938_IRQ_IOC+01 PCI-C
 * RBTX4938_IRQ_IOC+02 PCI-B
 * RBTX4938_IRQ_IOC+03 PCI-A
 * RBTX4938_IRQ_IOC+04 RTC
 * RBTX4938_IRQ_IOC+05 ATA
 * RBTX4938_IRQ_IOC+06 MODEM
 * RBTX4938_IRQ_IOC+07 SWINT
 */
#include <linux/init.h>
#include <linux/interrupt.h>
#include <asm/mipsregs.h>
#include <asm/txx9/generic.h>
#include <asm/txx9/rbtx4938.h>

static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq);
static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq);

#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC"
static struct irq_chip toshiba_rbtx4938_irq_ioc_type = {
	.name = TOSHIBA_RBTX4938_IOC_NAME,
	.ack = toshiba_rbtx4938_irq_ioc_disable,
	.mask = toshiba_rbtx4938_irq_ioc_disable,
	.mask_ack = toshiba_rbtx4938_irq_ioc_disable,
	.unmask = toshiba_rbtx4938_irq_ioc_enable,
};

static int toshiba_rbtx4938_irq_nested(int sw_irq)
{
	u8 level3;

	level3 = readb(rbtx4938_imstat_addr);
	if (level3)
		/* must use fls so onboard ATA has priority */
		sw_irq = RBTX4938_IRQ_IOC + fls(level3) - 1;
	return sw_irq;
}

static void __init
toshiba_rbtx4938_irq_ioc_init(void)
{
	int i;

	for (i = RBTX4938_IRQ_IOC;
	     i < RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC; i++)
		set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type,
					 handle_level_irq);

	set_irq_chained_handler(RBTX4938_IRQ_IOCINT, handle_simple_irq);
}

static void
toshiba_rbtx4938_irq_ioc_enable(unsigned int irq)
{
	unsigned char v;

	v = readb(rbtx4938_imask_addr);
	v |= (1 << (irq - RBTX4938_IRQ_IOC));
	writeb(v, rbtx4938_imask_addr);
	mmiowb();
}

static void
toshiba_rbtx4938_irq_ioc_disable(unsigned int irq)
{
	unsigned char v;

	v = readb(rbtx4938_imask_addr);
	v &= ~(1 << (irq - RBTX4938_IRQ_IOC));
	writeb(v, rbtx4938_imask_addr);
	mmiowb();
}

static int rbtx4938_irq_dispatch(int pending)
{
	int irq;

	if (pending & STATUSF_IP7)
		irq = MIPS_CPU_IRQ_BASE + 7;
	else if (pending & STATUSF_IP2) {
		irq = txx9_irq();
		if (irq == RBTX4938_IRQ_IOCINT)
			irq = toshiba_rbtx4938_irq_nested(irq);
	} else if (pending & STATUSF_IP1)
		irq = MIPS_CPU_IRQ_BASE + 0;
	else if (pending & STATUSF_IP0)
		irq = MIPS_CPU_IRQ_BASE + 1;
	else
		irq = -1;
	return irq;
}

void __init rbtx4938_irq_setup(void)
{
	txx9_irq_dispatch = rbtx4938_irq_dispatch;
	/* Now, interrupt control disabled, */
	/* all IRC interrupts are masked, */
	/* all IRC interrupt mode are Low Active. */

	/* mask all IOC interrupts */
	writeb(0, rbtx4938_imask_addr);

	/* clear SoftInt interrupts */
	writeb(0, rbtx4938_softint_addr);
	tx4938_irq_init();
	toshiba_rbtx4938_irq_ioc_init();
	/* Onboard 10M Ether: High Active */
	set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH);
}
Commit	Line	Data
23fbee9d	1	/*
23fbee9d RB	2	* Toshiba RBTX4938 specific interrupt handlers
	3	* Copyright (C) 2000-2001 Toshiba Corporation
	4	*
	5	* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
	6	* terms of the GNU General Public License version 2. This program is
	7	* licensed "as is" without any warranty of any kind, whether express
	8	* or implied.
	9	*
	10	* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
	11	*/
	12
	13	/*
bb72f1f7 AN	14	* MIPS_CPU_IRQ_BASE+00 Software 0
	15	* MIPS_CPU_IRQ_BASE+01 Software 1
	16	* MIPS_CPU_IRQ_BASE+02 Cascade TX4938-CP0
	17	* MIPS_CPU_IRQ_BASE+03 Multiplexed -- do not use
	18	* MIPS_CPU_IRQ_BASE+04 Multiplexed -- do not use
	19	* MIPS_CPU_IRQ_BASE+05 Multiplexed -- do not use
	20	* MIPS_CPU_IRQ_BASE+06 Multiplexed -- do not use
	21	* MIPS_CPU_IRQ_BASE+07 CPU TIMER
	22	*
	23	* TXX9_IRQ_BASE+00
	24	* TXX9_IRQ_BASE+01
	25	* TXX9_IRQ_BASE+02 Cascade RBTX4938-IOC
	26	* TXX9_IRQ_BASE+03 RBTX4938 RTL-8019AS Ethernet
	27	* TXX9_IRQ_BASE+04
	28	* TXX9_IRQ_BASE+05 TX4938 ETH1
	29	* TXX9_IRQ_BASE+06 TX4938 ETH0
	30	* TXX9_IRQ_BASE+07
	31	* TXX9_IRQ_BASE+08 TX4938 SIO 0
	32	* TXX9_IRQ_BASE+09 TX4938 SIO 1
	33	* TXX9_IRQ_BASE+10 TX4938 DMA0
	34	* TXX9_IRQ_BASE+11 TX4938 DMA1
	35	* TXX9_IRQ_BASE+12 TX4938 DMA2
	36	* TXX9_IRQ_BASE+13 TX4938 DMA3
	37	* TXX9_IRQ_BASE+14
	38	* TXX9_IRQ_BASE+15
	39	* TXX9_IRQ_BASE+16 TX4938 PCIC
	40	* TXX9_IRQ_BASE+17 TX4938 TMR0
	41	* TXX9_IRQ_BASE+18 TX4938 TMR1
	42	* TXX9_IRQ_BASE+19 TX4938 TMR2
	43	* TXX9_IRQ_BASE+20
	44	* TXX9_IRQ_BASE+21
	45	* TXX9_IRQ_BASE+22 TX4938 PCIERR
	46	* TXX9_IRQ_BASE+23
	47	* TXX9_IRQ_BASE+24
	48	* TXX9_IRQ_BASE+25
	49	* TXX9_IRQ_BASE+26
	50	* TXX9_IRQ_BASE+27
	51	* TXX9_IRQ_BASE+28
	52	* TXX9_IRQ_BASE+29
	53	* TXX9_IRQ_BASE+30
	54	* TXX9_IRQ_BASE+31 TX4938 SPI
	55	*
	56	* RBTX4938_IRQ_IOC+00 PCI-D
	57	* RBTX4938_IRQ_IOC+01 PCI-C
	58	* RBTX4938_IRQ_IOC+02 PCI-B
	59	* RBTX4938_IRQ_IOC+03 PCI-A
	60	* RBTX4938_IRQ_IOC+04 RTC
	61	* RBTX4938_IRQ_IOC+05 ATA
	62	* RBTX4938_IRQ_IOC+06 MODEM
	63	* RBTX4938_IRQ_IOC+07 SWINT
	64	*/
23fbee9d	65	#include <linux/init.h>
23fbee9d	66	#include <linux/interrupt.h>
edcaf1a6 AN	67	#include <asm/mipsregs.h>
edcaf1a6 AN	68	#include <asm/txx9/generic.h>
22b1d707	69	#include <asm/txx9/rbtx4938.h>
23fbee9d	70
23fbee9d RB	71	static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq);
23fbee9d RB	72	static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq);
23fbee9d	73
23fbee9d	74	#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC"
94dee171	75	static struct irq_chip toshiba_rbtx4938_irq_ioc_type = {
70d21cde	76	.name = TOSHIBA_RBTX4938_IOC_NAME,
1603b5ac AN	77	.ack = toshiba_rbtx4938_irq_ioc_disable,
	78	.mask = toshiba_rbtx4938_irq_ioc_disable,
	79	.mask_ack = toshiba_rbtx4938_irq_ioc_disable,
	80	.unmask = toshiba_rbtx4938_irq_ioc_enable,
23fbee9d RB	81	};
23fbee9d RB	82
edcaf1a6	83	static int toshiba_rbtx4938_irq_nested(int sw_irq)
23fbee9d RB	84	{
	85	u8 level3;
	86
66140c8e AN	87	level3 = readb(rbtx4938_imstat_addr);
66140c8e AN	88	if (level3)
23fbee9d	89	/* must use fls so onboard ATA has priority */
edcaf1a6	90	sw_irq = RBTX4938_IRQ_IOC + fls(level3) - 1;
23fbee9d RB	91	return sw_irq;
	92	}
	93
23fbee9d RB	94	static void __init
	95	toshiba_rbtx4938_irq_ioc_init(void)
	96	{
	97	int i;
	98
edcaf1a6 AN	99	for (i = RBTX4938_IRQ_IOC;
edcaf1a6 AN	100	i < RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC; i++)
1417836e AN	101	set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type,
1417836e AN	102	handle_level_irq);
23fbee9d	103
edcaf1a6	104	set_irq_chained_handler(RBTX4938_IRQ_IOCINT, handle_simple_irq);
23fbee9d RB	105	}
23fbee9d RB	106
23fbee9d RB	107	static void
	108	toshiba_rbtx4938_irq_ioc_enable(unsigned int irq)
	109	{
66140c8e	110	unsigned char v;
23fbee9d	111
66140c8e	112	v = readb(rbtx4938_imask_addr);
edcaf1a6	113	v \|= (1 << (irq - RBTX4938_IRQ_IOC));
66140c8e	114	writeb(v, rbtx4938_imask_addr);
23fbee9d	115	mmiowb();
23fbee9d RB	116	}
	117
	118	static void
	119	toshiba_rbtx4938_irq_ioc_disable(unsigned int irq)
	120	{
66140c8e	121	unsigned char v;
23fbee9d	122
66140c8e	123	v = readb(rbtx4938_imask_addr);
edcaf1a6	124	v &= ~(1 << (irq - RBTX4938_IRQ_IOC));
66140c8e	125	writeb(v, rbtx4938_imask_addr);
23fbee9d	126	mmiowb();
23fbee9d RB	127	}
23fbee9d RB	128
edcaf1a6	129	static int rbtx4938_irq_dispatch(int pending)
23fbee9d	130	{
edcaf1a6 AN	131	int irq;
	132
	133	if (pending & STATUSF_IP7)
	134	irq = MIPS_CPU_IRQ_BASE + 7;
	135	else if (pending & STATUSF_IP2) {
	136	irq = txx9_irq();
	137	if (irq == RBTX4938_IRQ_IOCINT)
	138	irq = toshiba_rbtx4938_irq_nested(irq);
	139	} else if (pending & STATUSF_IP1)
	140	irq = MIPS_CPU_IRQ_BASE + 0;
	141	else if (pending & STATUSF_IP0)
	142	irq = MIPS_CPU_IRQ_BASE + 1;
	143	else
	144	irq = -1;
	145	return irq;
	146	}
23fbee9d	147
edcaf1a6 AN	148	void __init rbtx4938_irq_setup(void)
	149	{
	150	txx9_irq_dispatch = rbtx4938_irq_dispatch;
23fbee9d RB	151	/* Now, interrupt control disabled, */
	152	/* all IRC interrupts are masked, */
	153	/* all IRC interrupt mode are Low Active. */
	154
	155	/* mask all IOC interrupts */
66140c8e	156	writeb(0, rbtx4938_imask_addr);
23fbee9d RB	157
23fbee9d RB	158	/* clear SoftInt interrupts */
66140c8e	159	writeb(0, rbtx4938_softint_addr);
23fbee9d RB	160	tx4938_irq_init();
	161	toshiba_rbtx4938_irq_ioc_init();
	162	/* Onboard 10M Ether: High Active */
c87abd75	163	set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH);
23fbee9d	164	}