[deliverable/linux.git] / arch / mips / txx9 / rbtx4939 / setup.c

/*
 * Toshiba RBTX4939 setup routines.
 * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
 *	    and RBTX49xx patch from CELF patch archive.
 *
 * Copyright (C) 2000-2001,2005-2007 Toshiba Corporation
 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
 * terms of the GNU General Public License version 2. This program is
 * licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/platform_device.h>
#include <linux/leds.h>
#include <linux/interrupt.h>
#include <linux/smc91x.h>
#include <asm/reboot.h>
#include <asm/txx9/generic.h>
#include <asm/txx9/pci.h>
#include <asm/txx9/rbtx4939.h>

static void rbtx4939_machine_restart(char *command)
{
	local_irq_disable();
	writeb(1, rbtx4939_reseten_addr);
	writeb(1, rbtx4939_softreset_addr);
	while (1)
		;
}

static void __init rbtx4939_time_init(void)
{
	tx4939_time_init(0);
}

#if defined(__BIG_ENDIAN) && \
	(defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE))
#define HAVE_RBTX4939_IOSWAB
#define IS_CE1_ADDR(addr) \
	((((unsigned long)(addr) - IO_BASE) & 0xfff00000) == TXX9_CE(1))
static u16 rbtx4939_ioswabw(volatile u16 *a, u16 x)
{
	return IS_CE1_ADDR(a) ? x : le16_to_cpu(x);
}
static u16 rbtx4939_mem_ioswabw(volatile u16 *a, u16 x)
{
	return !IS_CE1_ADDR(a) ? x : le16_to_cpu(x);
}
#endif /* __BIG_ENDIAN && CONFIG_SMC91X */

static void __init rbtx4939_pci_setup(void)
{
#ifdef CONFIG_PCI
	int extarb = !(__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCIARB);
	struct pci_controller *c = &txx9_primary_pcic;

	register_pci_controller(c);

	tx4939_report_pciclk();
	tx4927_pcic_setup(tx4939_pcicptr, c, extarb);
	if (!(__raw_readq(&tx4939_ccfgptr->pcfg) & TX4939_PCFG_ATA1MODE) &&
	    (__raw_readq(&tx4939_ccfgptr->pcfg) &
	     (TX4939_PCFG_ET0MODE | TX4939_PCFG_ET1MODE))) {
		tx4939_report_pci1clk();

		/* mem:64K(max), io:64K(max) (enough for ETH0,ETH1) */
		c = txx9_alloc_pci_controller(NULL, 0, 0x10000, 0, 0x10000);
		register_pci_controller(c);
		tx4927_pcic_setup(tx4939_pcic1ptr, c, 0);
	}

	tx4939_setup_pcierr_irq();
#endif /* CONFIG_PCI */
}

static unsigned long long default_ebccr[] __initdata = {
	0x01c0000000007608ULL, /* 64M ROM */
	0x017f000000007049ULL, /* 1M IOC */
	0x0180000000408608ULL, /* ISA */
	0,
};

static void __init rbtx4939_ebusc_setup(void)
{
	int i;
	unsigned int sp;

	/* use user-configured speed */
	sp = TX4939_EBUSC_CR(0) & 0x30;
	default_ebccr[0] |= sp;
	default_ebccr[1] |= sp;
	default_ebccr[2] |= sp;
	/* initialise by myself */
	for (i = 0; i < ARRAY_SIZE(default_ebccr); i++) {
		if (default_ebccr[i])
			____raw_writeq(default_ebccr[i],
				       &tx4939_ebuscptr->cr[i]);
		else
			____raw_writeq(____raw_readq(&tx4939_ebuscptr->cr[i])
				       & ~8,
				       &tx4939_ebuscptr->cr[i]);
	}
}

static void __init rbtx4939_update_ioc_pen(void)
{
	__u64 pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
	__u64 ccfg = ____raw_readq(&tx4939_ccfgptr->ccfg);
	__u8 pe1 = readb(rbtx4939_pe1_addr);
	__u8 pe2 = readb(rbtx4939_pe2_addr);
	__u8 pe3 = readb(rbtx4939_pe3_addr);
	if (pcfg & TX4939_PCFG_ATA0MODE)
		pe1 |= RBTX4939_PE1_ATA(0);
	else
		pe1 &= ~RBTX4939_PE1_ATA(0);
	if (pcfg & TX4939_PCFG_ATA1MODE) {
		pe1 |= RBTX4939_PE1_ATA(1);
		pe1 &= ~(RBTX4939_PE1_RMII(0) | RBTX4939_PE1_RMII(1));
	} else {
		pe1 &= ~RBTX4939_PE1_ATA(1);
		if (pcfg & TX4939_PCFG_ET0MODE)
			pe1 |= RBTX4939_PE1_RMII(0);
		else
			pe1 &= ~RBTX4939_PE1_RMII(0);
		if (pcfg & TX4939_PCFG_ET1MODE)
			pe1 |= RBTX4939_PE1_RMII(1);
		else
			pe1 &= ~RBTX4939_PE1_RMII(1);
	}
	if (ccfg & TX4939_CCFG_PTSEL)
		pe3 &= ~(RBTX4939_PE3_VP | RBTX4939_PE3_VP_P |
			 RBTX4939_PE3_VP_S);
	else {
		__u64 vmode = pcfg &
			(TX4939_PCFG_VSSMODE | TX4939_PCFG_VPSMODE);
		if (vmode == 0)
			pe3 &= ~(RBTX4939_PE3_VP | RBTX4939_PE3_VP_P |
				 RBTX4939_PE3_VP_S);
		else if (vmode == TX4939_PCFG_VPSMODE) {
			pe3 |= RBTX4939_PE3_VP_P;
			pe3 &= ~(RBTX4939_PE3_VP | RBTX4939_PE3_VP_S);
		} else if (vmode == TX4939_PCFG_VSSMODE) {
			pe3 |= RBTX4939_PE3_VP | RBTX4939_PE3_VP_S;
			pe3 &= ~RBTX4939_PE3_VP_P;
		} else {
			pe3 |= RBTX4939_PE3_VP | RBTX4939_PE3_VP_P;
			pe3 &= ~RBTX4939_PE3_VP_S;
		}
	}
	if (pcfg & TX4939_PCFG_SPIMODE) {
		if (pcfg & TX4939_PCFG_SIO2MODE_GPIO)
			pe2 &= ~(RBTX4939_PE2_SIO2 | RBTX4939_PE2_SIO0);
		else {
			if (pcfg & TX4939_PCFG_SIO2MODE_SIO2) {
				pe2 |= RBTX4939_PE2_SIO2;
				pe2 &= ~RBTX4939_PE2_SIO0;
			} else {
				pe2 |= RBTX4939_PE2_SIO0;
				pe2 &= ~RBTX4939_PE2_SIO2;
			}
		}
		if (pcfg & TX4939_PCFG_SIO3MODE)
			pe2 |= RBTX4939_PE2_SIO3;
		else
			pe2 &= ~RBTX4939_PE2_SIO3;
		pe2 &= ~RBTX4939_PE2_SPI;
	} else {
		pe2 |= RBTX4939_PE2_SPI;
		pe2 &= ~(RBTX4939_PE2_SIO3 | RBTX4939_PE2_SIO2 |
			 RBTX4939_PE2_SIO0);
	}
	if ((pcfg & TX4939_PCFG_I2SMODE_MASK) == TX4939_PCFG_I2SMODE_GPIO)
		pe2 |= RBTX4939_PE2_GPIO;
	else
		pe2 &= ~RBTX4939_PE2_GPIO;
	writeb(pe1, rbtx4939_pe1_addr);
	writeb(pe2, rbtx4939_pe2_addr);
	writeb(pe3, rbtx4939_pe3_addr);
}

#define RBTX4939_MAX_7SEGLEDS	8

#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
static u8 led_val[RBTX4939_MAX_7SEGLEDS];
struct rbtx4939_led_data {
	struct led_classdev cdev;
	char name[32];
	unsigned int num;
};

/* Use "dot" in 7seg LEDs */
static void rbtx4939_led_brightness_set(struct led_classdev *led_cdev,
					enum led_brightness value)
{
	struct rbtx4939_led_data *led_dat =
		container_of(led_cdev, struct rbtx4939_led_data, cdev);
	unsigned int num = led_dat->num;
	unsigned long flags;

	local_irq_save(flags);
	led_val[num] = (led_val[num] & 0x7f) | (value ? 0x80 : 0);
	writeb(led_val[num], rbtx4939_7seg_addr(num / 4, num % 4));
	local_irq_restore(flags);
}

static int __init rbtx4939_led_probe(struct platform_device *pdev)
{
	struct rbtx4939_led_data *leds_data;
	int i;
	static char *default_triggers[] __initdata = {
		"heartbeat",
		"ide-disk",
		"nand-disk",
	};

	leds_data = kzalloc(sizeof(*leds_data) * RBTX4939_MAX_7SEGLEDS,
			    GFP_KERNEL);
	if (!leds_data)
		return -ENOMEM;
	for (i = 0; i < RBTX4939_MAX_7SEGLEDS; i++) {
		int rc;
		struct rbtx4939_led_data *led_dat = &leds_data[i];

		led_dat->num = i;
		led_dat->cdev.brightness_set = rbtx4939_led_brightness_set;
		sprintf(led_dat->name, "rbtx4939:amber:%u", i);
		led_dat->cdev.name = led_dat->name;
		if (i < ARRAY_SIZE(default_triggers))
			led_dat->cdev.default_trigger = default_triggers[i];
		rc = led_classdev_register(&pdev->dev, &led_dat->cdev);
		if (rc < 0)
			return rc;
		led_dat->cdev.brightness_set(&led_dat->cdev, 0);
	}
	return 0;

}

static struct platform_driver rbtx4939_led_driver = {
	.driver  = {
		.name = "rbtx4939-led",
		.owner = THIS_MODULE,
	},
};

static void __init rbtx4939_led_setup(void)
{
	platform_device_register_simple("rbtx4939-led", -1, NULL, 0);
	platform_driver_probe(&rbtx4939_led_driver, rbtx4939_led_probe);
}
#else
static inline void rbtx4939_led_setup(void)
{
}
#endif

static void __rbtx4939_7segled_putc(unsigned int pos, unsigned char val)
{
#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
	unsigned long flags;
	local_irq_save(flags);
	/* bit7: reserved for LED class */
	led_val[pos] = (led_val[pos] & 0x80) | (val & 0x7f);
	val = led_val[pos];
	local_irq_restore(flags);
#endif
	writeb(val, rbtx4939_7seg_addr(pos / 4, pos % 4));
}

static void rbtx4939_7segled_putc(unsigned int pos, unsigned char val)
{
	/* convert from map_to_seg7() notation */
	val = (val & 0x88) |
		((val & 0x40) >> 6) |
		((val & 0x20) >> 4) |
		((val & 0x10) >> 2) |
		((val & 0x04) << 2) |
		((val & 0x02) << 4) |
		((val & 0x01) << 6);
	__rbtx4939_7segled_putc(pos, val);
}

static void __init rbtx4939_arch_init(void)
{
	rbtx4939_pci_setup();
}

static void __init rbtx4939_device_init(void)
{
	unsigned long smc_addr = RBTX4939_ETHER_ADDR - IO_BASE;
	struct resource smc_res[] = {
		{
			.start	= smc_addr,
			.end	= smc_addr + 0x10 - 1,
			.flags	= IORESOURCE_MEM,
		}, {
			.start	= RBTX4939_IRQ_ETHER,
			/* override default irq flag defined in smc91x.h */
			.flags	= IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
		},
	};
	struct smc91x_platdata smc_pdata = {
		.flags = SMC91X_USE_16BIT,
	};
	struct platform_device *pdev;
#if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE)
	int i, j;
	unsigned char ethaddr[2][6];
	u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f;

	for (i = 0; i < 2; i++) {
		unsigned long area = CKSEG1 + 0x1fff0000 + (i * 0x10);
		if (bdipsw == 0)
			memcpy(ethaddr[i], (void *)area, 6);
		else {
			u16 buf[3];
			if (bdipsw & 8)
				area -= 0x03000000;
			else
				area -= 0x01000000;
			for (j = 0; j < 3; j++)
				buf[j] = le16_to_cpup((u16 *)(area + j * 2));
			memcpy(ethaddr[i], buf, 6);
		}
	}
	tx4939_ethaddr_init(ethaddr[0], ethaddr[1]);
#endif
	pdev = platform_device_alloc("smc91x", -1);
	if (!pdev ||
	    platform_device_add_resources(pdev, smc_res, ARRAY_SIZE(smc_res)) ||
	    platform_device_add_data(pdev, &smc_pdata, sizeof(smc_pdata)) ||
	    platform_device_add(pdev))
		platform_device_put(pdev);
	rbtx4939_led_setup();
	tx4939_wdt_init();
	tx4939_ata_init();
	tx4939_rtc_init();
}

static void __init rbtx4939_setup(void)
{
	int i;

	rbtx4939_ebusc_setup();
	/* always enable ATA0 */
	txx9_set64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_ATA0MODE);
	rbtx4939_update_ioc_pen();
	if (txx9_master_clock == 0)
		txx9_master_clock = 20000000;
	tx4939_setup();
#ifdef HAVE_RBTX4939_IOSWAB
	ioswabw = rbtx4939_ioswabw;
	__mem_ioswabw = rbtx4939_mem_ioswabw;
#endif

	_machine_restart = rbtx4939_machine_restart;

	txx9_7segled_init(RBTX4939_MAX_7SEGLEDS, rbtx4939_7segled_putc);
	for (i = 0; i < RBTX4939_MAX_7SEGLEDS; i++)
		txx9_7segled_putc(i, '-');
	pr_info("RBTX4939 (Rev %02x) --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
		readb(rbtx4939_board_rev_addr), readb(rbtx4939_ioc_rev_addr),
		readb(rbtx4939_udipsw_addr), readb(rbtx4939_bdipsw_addr));

#ifdef CONFIG_PCI
	txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
	txx9_board_pcibios_setup = tx4927_pcibios_setup;
#else
	set_io_port_base(RBTX4939_ETHER_BASE);
#endif

	tx4939_sio_init(TX4939_SCLK0(txx9_master_clock), 0);
}

struct txx9_board_vec rbtx4939_vec __initdata = {
	.system = "Tothiba RBTX4939",
	.prom_init = rbtx4939_prom_init,
	.mem_setup = rbtx4939_setup,
	.irq_setup = rbtx4939_irq_setup,
	.time_init = rbtx4939_time_init,
	.device_init = rbtx4939_device_init,
	.arch_init = rbtx4939_arch_init,
#ifdef CONFIG_PCI
	.pci_map_irq = tx4939_pci_map_irq,
#endif
};
Commit	Line	Data
b27311e1 AN	1	/*
	2	* Toshiba RBTX4939 setup routines.
	3	* Based on linux/arch/mips/txx9/rbtx4938/setup.c,
	4	* and RBTX49xx patch from CELF patch archive.
	5	*
	6	* Copyright (C) 2000-2001,2005-2007 Toshiba Corporation
	7	* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
	8	* terms of the GNU General Public License version 2. This program is
	9	* licensed "as is" without any warranty of any kind, whether express
	10	* or implied.
	11	*/
	12	#include <linux/init.h>
	13	#include <linux/kernel.h>
	14	#include <linux/types.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/leds.h>
1ba5a176 AN	17	#include <linux/interrupt.h>
1ba5a176 AN	18	#include <linux/smc91x.h>
b27311e1 AN	19	#include <asm/reboot.h>
	20	#include <asm/txx9/generic.h>
	21	#include <asm/txx9/pci.h>
	22	#include <asm/txx9/rbtx4939.h>
	23
	24	static void rbtx4939_machine_restart(char *command)
	25	{
	26	local_irq_disable();
	27	writeb(1, rbtx4939_reseten_addr);
	28	writeb(1, rbtx4939_softreset_addr);
	29	while (1)
	30	;
	31	}
	32
	33	static void __init rbtx4939_time_init(void)
	34	{
	35	tx4939_time_init(0);
	36	}
	37
1ba5a176 AN	38	#if defined(__BIG_ENDIAN) && \
	39	(defined(CONFIG_SMC91X) \|\| defined(CONFIG_SMC91X_MODULE))
	40	#define HAVE_RBTX4939_IOSWAB
	41	#define IS_CE1_ADDR(addr) \
	42	((((unsigned long)(addr) - IO_BASE) & 0xfff00000) == TXX9_CE(1))
	43	static u16 rbtx4939_ioswabw(volatile u16 *a, u16 x)
	44	{
	45	return IS_CE1_ADDR(a) ? x : le16_to_cpu(x);
	46	}
	47	static u16 rbtx4939_mem_ioswabw(volatile u16 *a, u16 x)
	48	{
	49	return !IS_CE1_ADDR(a) ? x : le16_to_cpu(x);
	50	}
	51	#endif /* __BIG_ENDIAN && CONFIG_SMC91X */
	52
b27311e1 AN	53	static void __init rbtx4939_pci_setup(void)
	54	{
	55	#ifdef CONFIG_PCI
	56	int extarb = !(__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCIARB);
	57	struct pci_controller *c = &txx9_primary_pcic;
	58
	59	register_pci_controller(c);
	60
	61	tx4939_report_pciclk();
	62	tx4927_pcic_setup(tx4939_pcicptr, c, extarb);
	63	if (!(__raw_readq(&tx4939_ccfgptr->pcfg) & TX4939_PCFG_ATA1MODE) &&
	64	(__raw_readq(&tx4939_ccfgptr->pcfg) &
	65	(TX4939_PCFG_ET0MODE \| TX4939_PCFG_ET1MODE))) {
	66	tx4939_report_pci1clk();
	67
	68	/* mem:64K(max), io:64K(max) (enough for ETH0,ETH1) */
	69	c = txx9_alloc_pci_controller(NULL, 0, 0x10000, 0, 0x10000);
	70	register_pci_controller(c);
	71	tx4927_pcic_setup(tx4939_pcic1ptr, c, 0);
	72	}
	73
	74	tx4939_setup_pcierr_irq();
	75	#endif /* CONFIG_PCI */
	76	}
	77
	78	static unsigned long long default_ebccr[] __initdata = {
	79	0x01c0000000007608ULL, /* 64M ROM */
	80	0x017f000000007049ULL, /* 1M IOC */
	81	0x0180000000408608ULL, /* ISA */
	82	0,
	83	};
	84
	85	static void __init rbtx4939_ebusc_setup(void)
	86	{
	87	int i;
	88	unsigned int sp;
	89
	90	/* use user-configured speed */
	91	sp = TX4939_EBUSC_CR(0) & 0x30;
	92	default_ebccr[0] \|= sp;
	93	default_ebccr[1] \|= sp;
	94	default_ebccr[2] \|= sp;
	95	/* initialise by myself */
	96	for (i = 0; i < ARRAY_SIZE(default_ebccr); i++) {
	97	if (default_ebccr[i])
	98	____raw_writeq(default_ebccr[i],
	99	&tx4939_ebuscptr->cr[i]);
	100	else
	101	____raw_writeq(____raw_readq(&tx4939_ebuscptr->cr[i])
	102	& ~8,
	103	&tx4939_ebuscptr->cr[i]);
	104	}
	105	}
	106
	107	static void __init rbtx4939_update_ioc_pen(void)
	108	{
	109	__u64 pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
	110	__u64 ccfg = ____raw_readq(&tx4939_ccfgptr->ccfg);
	111	__u8 pe1 = readb(rbtx4939_pe1_addr);
	112	__u8 pe2 = readb(rbtx4939_pe2_addr);
	113	__u8 pe3 = readb(rbtx4939_pe3_addr);
	114	if (pcfg & TX4939_PCFG_ATA0MODE)
	115	pe1 \|= RBTX4939_PE1_ATA(0);
	116	else
117	pe1 &= ~RBTX4939_PE1_ATA(0);
118	if (pcfg & TX4939_PCFG_ATA1MODE) {
119	pe1 \|= RBTX4939_PE1_ATA(1);
120	pe1 &= ~(RBTX4939_PE1_RMII(0) \| RBTX4939_PE1_RMII(1));
121	} else {
122	pe1 &= ~RBTX4939_PE1_ATA(1);
123	if (pcfg & TX4939_PCFG_ET0MODE)
124	pe1 \|= RBTX4939_PE1_RMII(0);
125	else
126	pe1 &= ~RBTX4939_PE1_RMII(0);
127	if (pcfg & TX4939_PCFG_ET1MODE)
128	pe1 \|= RBTX4939_PE1_RMII(1);
129	else
130	pe1 &= ~RBTX4939_PE1_RMII(1);
131	}
132	if (ccfg & TX4939_CCFG_PTSEL)
133	pe3 &= ~(RBTX4939_PE3_VP \| RBTX4939_PE3_VP_P \|
134	RBTX4939_PE3_VP_S);
135	else {
136	__u64 vmode = pcfg &
137	(TX4939_PCFG_VSSMODE \| TX4939_PCFG_VPSMODE);
138	if (vmode == 0)
139	pe3 &= ~(RBTX4939_PE3_VP \| RBTX4939_PE3_VP_P \|
140	RBTX4939_PE3_VP_S);
141	else if (vmode == TX4939_PCFG_VPSMODE) {
142	pe3 \|= RBTX4939_PE3_VP_P;
143	pe3 &= ~(RBTX4939_PE3_VP \| RBTX4939_PE3_VP_S);
144	} else if (vmode == TX4939_PCFG_VSSMODE) {
145	pe3 \|= RBTX4939_PE3_VP \| RBTX4939_PE3_VP_S;
146	pe3 &= ~RBTX4939_PE3_VP_P;
147	} else {
148	pe3 \|= RBTX4939_PE3_VP \| RBTX4939_PE3_VP_P;
149	pe3 &= ~RBTX4939_PE3_VP_S;
150	}
151	}
152	if (pcfg & TX4939_PCFG_SPIMODE) {
153	if (pcfg & TX4939_PCFG_SIO2MODE_GPIO)
154	pe2 &= ~(RBTX4939_PE2_SIO2 \| RBTX4939_PE2_SIO0);
155	else {
156	if (pcfg & TX4939_PCFG_SIO2MODE_SIO2) {
157	pe2 \|= RBTX4939_PE2_SIO2;
158	pe2 &= ~RBTX4939_PE2_SIO0;
159	} else {
160	pe2 \|= RBTX4939_PE2_SIO0;
161	pe2 &= ~RBTX4939_PE2_SIO2;
162	}
163	}
164	if (pcfg & TX4939_PCFG_SIO3MODE)
165	pe2 \|= RBTX4939_PE2_SIO3;
166	else
167	pe2 &= ~RBTX4939_PE2_SIO3;
168	pe2 &= ~RBTX4939_PE2_SPI;
169	} else {
170	pe2 \|= RBTX4939_PE2_SPI;
171	pe2 &= ~(RBTX4939_PE2_SIO3 \| RBTX4939_PE2_SIO2 \|
172	RBTX4939_PE2_SIO0);
173	}
174	if ((pcfg & TX4939_PCFG_I2SMODE_MASK) == TX4939_PCFG_I2SMODE_GPIO)
175	pe2 \|= RBTX4939_PE2_GPIO;
176	else
177	pe2 &= ~RBTX4939_PE2_GPIO;
178	writeb(pe1, rbtx4939_pe1_addr);
179	writeb(pe2, rbtx4939_pe2_addr);
180	writeb(pe3, rbtx4939_pe3_addr);
181	}
182
183	#define RBTX4939_MAX_7SEGLEDS 8
184
185	#if defined(CONFIG_LEDS_CLASS) \|\| defined(CONFIG_LEDS_CLASS_MODULE)
186	static u8 led_val[RBTX4939_MAX_7SEGLEDS];
187	struct rbtx4939_led_data {
188	struct led_classdev cdev;
189	char name[32];
190	unsigned int num;
191	};
192
193	/* Use "dot" in 7seg LEDs */
194	static void rbtx4939_led_brightness_set(struct led_classdev *led_cdev,
195	enum led_brightness value)
196	{
197	struct rbtx4939_led_data *led_dat =
198	container_of(led_cdev, struct rbtx4939_led_data, cdev);
199	unsigned int num = led_dat->num;
200	unsigned long flags;
201
202	local_irq_save(flags);
203	led_val[num] = (led_val[num] & 0x7f) \| (value ? 0x80 : 0);
204	writeb(led_val[num], rbtx4939_7seg_addr(num / 4, num % 4));
205	local_irq_restore(flags);
206	}
207
208	static int __init rbtx4939_led_probe(struct platform_device *pdev)
209	{
210	struct rbtx4939_led_data *leds_data;
211	int i;
212	static char *default_triggers[] __initdata = {
213	"heartbeat",
214	"ide-disk",
215	"nand-disk",
216	};
217
218	leds_data = kzalloc(sizeof(leds_data) RBTX4939_MAX_7SEGLEDS,
219	GFP_KERNEL);
220	if (!leds_data)
221	return -ENOMEM;
222	for (i = 0; i < RBTX4939_MAX_7SEGLEDS; i++) {
223	int rc;
224	struct rbtx4939_led_data *led_dat = &leds_data[i];
225
226	led_dat->num = i;
227	led_dat->cdev.brightness_set = rbtx4939_led_brightness_set;
228	sprintf(led_dat->name, "rbtx4939:amber:%u", i);
229	led_dat->cdev.name = led_dat->name;
230	if (i < ARRAY_SIZE(default_triggers))
231	led_dat->cdev.default_trigger = default_triggers[i];
232	rc = led_classdev_register(&pdev->dev, &led_dat->cdev);
233	if (rc < 0)
234	return rc;
235	led_dat->cdev.brightness_set(&led_dat->cdev, 0);
236	}
237	return 0;
238
239	}
240
241	static struct platform_driver rbtx4939_led_driver = {
242	.driver = {
243	.name = "rbtx4939-led",
244	.owner = THIS_MODULE,
245	},
246	};
247
248	static void __init rbtx4939_led_setup(void)
249	{
250	platform_device_register_simple("rbtx4939-led", -1, NULL, 0);
251	platform_driver_probe(&rbtx4939_led_driver, rbtx4939_led_probe);
252	}
253	#else
254	static inline void rbtx4939_led_setup(void)
255	{
256	}
257	#endif
258
bc89b2bd AN	259	static void __rbtx4939_7segled_putc(unsigned int pos, unsigned char val)
	260	{
	261	#if defined(CONFIG_LEDS_CLASS) \|\| defined(CONFIG_LEDS_CLASS_MODULE)
	262	unsigned long flags;
	263	local_irq_save(flags);
	264	/* bit7: reserved for LED class */
	265	led_val[pos] = (led_val[pos] & 0x80) \| (val & 0x7f);
	266	val = led_val[pos];
	267	local_irq_restore(flags);
	268	#endif
	269	writeb(val, rbtx4939_7seg_addr(pos / 4, pos % 4));
	270	}
	271
	272	static void rbtx4939_7segled_putc(unsigned int pos, unsigned char val)
	273	{
	274	/* convert from map_to_seg7() notation */
	275	val = (val & 0x88) \|
	276	((val & 0x40) >> 6) \|
	277	((val & 0x20) >> 4) \|
	278	((val & 0x10) >> 2) \|
	279	((val & 0x04) << 2) \|
	280	((val & 0x02) << 4) \|
	281	((val & 0x01) << 6);
	282	__rbtx4939_7segled_putc(pos, val);
	283	}
	284
b27311e1 AN	285	static void __init rbtx4939_arch_init(void)
	286	{
	287	rbtx4939_pci_setup();
	288	}
	289
	290	static void __init rbtx4939_device_init(void)
	291	{
1ba5a176 AN	292	unsigned long smc_addr = RBTX4939_ETHER_ADDR - IO_BASE;
	293	struct resource smc_res[] = {
	294	{
	295	.start = smc_addr,
	296	.end = smc_addr + 0x10 - 1,
	297	.flags = IORESOURCE_MEM,
	298	}, {
	299	.start = RBTX4939_IRQ_ETHER,
	300	/* override default irq flag defined in smc91x.h */
	301	.flags = IORESOURCE_IRQ \| IRQF_TRIGGER_LOW,
	302	},
	303	};
	304	struct smc91x_platdata smc_pdata = {
	305	.flags = SMC91X_USE_16BIT,
	306	};
	307	struct platform_device *pdev;
b27311e1 AN	308	#if defined(CONFIG_TC35815) \|\| defined(CONFIG_TC35815_MODULE)
	309	int i, j;
	310	unsigned char ethaddr[2][6];
9cc45815 AN	311	u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f;
9cc45815 AN	312
b27311e1 AN	313	for (i = 0; i < 2; i++) {
b27311e1 AN	314	unsigned long area = CKSEG1 + 0x1fff0000 + (i * 0x10);
9cc45815 AN	315	if (bdipsw == 0)
	316	memcpy(ethaddr[i], (void *)area, 6);
	317	else {
b27311e1	318	u16 buf[3];
9cc45815 AN	319	if (bdipsw & 8)
	320	area -= 0x03000000;
	321	else
	322	area -= 0x01000000;
b27311e1 AN	323	for (j = 0; j < 3; j++)
	324	buf[j] = le16_to_cpup((u16 )(area + j 2));
	325	memcpy(ethaddr[i], buf, 6);
9cc45815	326	}
b27311e1 AN	327	}
	328	tx4939_ethaddr_init(ethaddr[0], ethaddr[1]);
	329	#endif
1ba5a176 AN	330	pdev = platform_device_alloc("smc91x", -1);
	331	if (!pdev \|\|
	332	platform_device_add_resources(pdev, smc_res, ARRAY_SIZE(smc_res)) \|\|
	333	platform_device_add_data(pdev, &smc_pdata, sizeof(smc_pdata)) \|\|
	334	platform_device_add(pdev))
	335	platform_device_put(pdev);
b27311e1 AN	336	rbtx4939_led_setup();
b27311e1 AN	337	tx4939_wdt_init();
4bacc687	338	tx4939_ata_init();
65655b5a	339	tx4939_rtc_init();
b27311e1 AN	340	}
	341
	342	static void __init rbtx4939_setup(void)
	343	{
bc89b2bd AN	344	int i;
bc89b2bd AN	345
b27311e1 AN	346	rbtx4939_ebusc_setup();
	347	/* always enable ATA0 */
	348	txx9_set64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_ATA0MODE);
	349	rbtx4939_update_ioc_pen();
	350	if (txx9_master_clock == 0)
	351	txx9_master_clock = 20000000;
	352	tx4939_setup();
1ba5a176 AN	353	#ifdef HAVE_RBTX4939_IOSWAB
	354	ioswabw = rbtx4939_ioswabw;
	355	__mem_ioswabw = rbtx4939_mem_ioswabw;
	356	#endif
b27311e1 AN	357
	358	_machine_restart = rbtx4939_machine_restart;
	359
bc89b2bd AN	360	txx9_7segled_init(RBTX4939_MAX_7SEGLEDS, rbtx4939_7segled_putc);
	361	for (i = 0; i < RBTX4939_MAX_7SEGLEDS; i++)
	362	txx9_7segled_putc(i, '-');
b27311e1 AN	363	pr_info("RBTX4939 (Rev %02x) --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
	364	readb(rbtx4939_board_rev_addr), readb(rbtx4939_ioc_rev_addr),
	365	readb(rbtx4939_udipsw_addr), readb(rbtx4939_bdipsw_addr));
	366
	367	#ifdef CONFIG_PCI
	368	txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
	369	txx9_board_pcibios_setup = tx4927_pcibios_setup;
	370	#else
	371	set_io_port_base(RBTX4939_ETHER_BASE);
	372	#endif
	373
	374	tx4939_sio_init(TX4939_SCLK0(txx9_master_clock), 0);
	375	}
	376
	377	struct txx9_board_vec rbtx4939_vec __initdata = {
	378	.system = "Tothiba RBTX4939",
	379	.prom_init = rbtx4939_prom_init,
	380	.mem_setup = rbtx4939_setup,
	381	.irq_setup = rbtx4939_irq_setup,
	382	.time_init = rbtx4939_time_init,
	383	.device_init = rbtx4939_device_init,
	384	.arch_init = rbtx4939_arch_init,
	385	#ifdef CONFIG_PCI
	386	.pci_map_irq = tx4939_pci_map_irq,
	387	#endif
	388	};