[deliverable/linux.git] / arch / mn10300 / kernel / irq.c

/* MN10300 Arch-specific interrupt handling
 *
 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
 * Written by David Howells (dhowells@redhat.com)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public Licence
 * as published by the Free Software Foundation; either version
 * 2 of the Licence, or (at your option) any later version.
 */
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/seq_file.h>
#include <linux/cpumask.h>
#include <asm/setup.h>
#include <asm/serial-regs.h>

unsigned long __mn10300_irq_enabled_epsw[NR_CPUS] __cacheline_aligned_in_smp = {
	[0 ... NR_CPUS - 1] = EPSW_IE | EPSW_IM_7
};
EXPORT_SYMBOL(__mn10300_irq_enabled_epsw);

#ifdef CONFIG_SMP
static char irq_affinity_online[NR_IRQS] = {
	[0 ... NR_IRQS - 1] = 0
};

#define NR_IRQ_WORDS	((NR_IRQS + 31) / 32)
static unsigned long irq_affinity_request[NR_IRQ_WORDS] = {
	[0 ... NR_IRQ_WORDS - 1] = 0
};
#endif  /* CONFIG_SMP */

atomic_t irq_err_count;

/*
 * MN10300 interrupt controller operations
 */
static void mn10300_cpupic_ack(struct irq_data *d)
{
	unsigned int irq = d->irq;
	unsigned long flags;
	u16 tmp;

	flags = arch_local_cli_save();
	GxICR_u8(irq) = GxICR_DETECT;
	tmp = GxICR(irq);
	arch_local_irq_restore(flags);
}

static void __mask_and_set_icr(unsigned int irq,
			       unsigned int mask, unsigned int set)
{
	unsigned long flags;
	u16 tmp;

	flags = arch_local_cli_save();
	tmp = GxICR(irq);
	GxICR(irq) = (tmp & mask) | set;
	tmp = GxICR(irq);
	arch_local_irq_restore(flags);
}

static void mn10300_cpupic_mask(struct irq_data *d)
{
	__mask_and_set_icr(d->irq, GxICR_LEVEL, 0);
}

static void mn10300_cpupic_mask_ack(struct irq_data *d)
{
	unsigned int irq = d->irq;
#ifdef CONFIG_SMP
	unsigned long flags;
	u16 tmp;

	flags = arch_local_cli_save();

	if (!test_and_clear_bit(irq, irq_affinity_request)) {
		tmp = GxICR(irq);
		GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_DETECT;
		tmp = GxICR(irq);
	} else {
		u16 tmp2;
		tmp = GxICR(irq);
		GxICR(irq) = (tmp & GxICR_LEVEL);
		tmp2 = GxICR(irq);

		irq_affinity_online[irq] =
			cpumask_any_and(irq_data_get_affinity_mask(d),
					cpu_online_mask);
		CROSS_GxICR(irq, irq_affinity_online[irq]) =
			(tmp & (GxICR_LEVEL | GxICR_ENABLE)) | GxICR_DETECT;
		tmp = CROSS_GxICR(irq, irq_affinity_online[irq]);
	}

	arch_local_irq_restore(flags);
#else  /* CONFIG_SMP */
	__mask_and_set_icr(irq, GxICR_LEVEL, GxICR_DETECT);
#endif /* CONFIG_SMP */
}

static void mn10300_cpupic_unmask(struct irq_data *d)
{
	__mask_and_set_icr(d->irq, GxICR_LEVEL, GxICR_ENABLE);
}

static void mn10300_cpupic_unmask_clear(struct irq_data *d)
{
	unsigned int irq = d->irq;
	/* the MN10300 PIC latches its interrupt request bit, even after the
	 * device has ceased to assert its interrupt line and the interrupt
	 * channel has been disabled in the PIC, so for level-triggered
	 * interrupts we need to clear the request bit when we re-enable */
#ifdef CONFIG_SMP
	unsigned long flags;
	u16 tmp;

	flags = arch_local_cli_save();

	if (!test_and_clear_bit(irq, irq_affinity_request)) {
		tmp = GxICR(irq);
		GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_ENABLE | GxICR_DETECT;
		tmp = GxICR(irq);
	} else {
		tmp = GxICR(irq);

		irq_affinity_online[irq] = cpumask_any_and(irq_data_get_affinity_mask(d),
							   cpu_online_mask);
		CROSS_GxICR(irq, irq_affinity_online[irq]) = (tmp & GxICR_LEVEL) | GxICR_ENABLE | GxICR_DETECT;
		tmp = CROSS_GxICR(irq, irq_affinity_online[irq]);
	}

	arch_local_irq_restore(flags);
#else  /* CONFIG_SMP */
	__mask_and_set_icr(irq, GxICR_LEVEL, GxICR_ENABLE | GxICR_DETECT);
#endif /* CONFIG_SMP */
}

#ifdef CONFIG_SMP
static int
mn10300_cpupic_setaffinity(struct irq_data *d, const struct cpumask *mask,
			   bool force)
{
	unsigned long flags;

	flags = arch_local_cli_save();
	set_bit(d->irq, irq_affinity_request);
	arch_local_irq_restore(flags);
	return 0;
}
#endif /* CONFIG_SMP */

/*
 * MN10300 PIC level-triggered IRQ handling.
 *
 * The PIC has no 'ACK' function per se.  It is possible to clear individual
 * channel latches, but each latch relatches whether or not the channel is
 * masked, so we need to clear the latch when we unmask the channel.
 *
 * Also for this reason, we don't supply an ack() op (it's unused anyway if
 * mask_ack() is provided), and mask_ack() just masks.
 */
static struct irq_chip mn10300_cpu_pic_level = {
	.name			= "cpu_l",
	.irq_disable		= mn10300_cpupic_mask,
	.irq_enable		= mn10300_cpupic_unmask_clear,
	.irq_ack		= NULL,
	.irq_mask		= mn10300_cpupic_mask,
	.irq_mask_ack		= mn10300_cpupic_mask,
	.irq_unmask		= mn10300_cpupic_unmask_clear,
#ifdef CONFIG_SMP
	.irq_set_affinity	= mn10300_cpupic_setaffinity,
#endif
};

/*
 * MN10300 PIC edge-triggered IRQ handling.
 *
 * We use the latch clearing function of the PIC as the 'ACK' function.
 */
static struct irq_chip mn10300_cpu_pic_edge = {
	.name			= "cpu_e",
	.irq_disable		= mn10300_cpupic_mask,
	.irq_enable		= mn10300_cpupic_unmask,
	.irq_ack		= mn10300_cpupic_ack,
	.irq_mask		= mn10300_cpupic_mask,
	.irq_mask_ack		= mn10300_cpupic_mask_ack,
	.irq_unmask		= mn10300_cpupic_unmask,
#ifdef CONFIG_SMP
	.irq_set_affinity	= mn10300_cpupic_setaffinity,
#endif
};

/*
 * 'what should we do if we get a hw irq event on an illegal vector'.
 * each architecture has to answer this themselves.
 */
void ack_bad_irq(int irq)
{
	printk(KERN_WARNING "unexpected IRQ trap at vector %02x\n", irq);
}

/*
 * change the level at which an IRQ executes
 * - must not be called whilst interrupts are being processed!
 */
void set_intr_level(int irq, u16 level)
{
	BUG_ON(in_interrupt());

	__mask_and_set_icr(irq, GxICR_ENABLE, level);
}

/*
 * mark an interrupt to be ACK'd after interrupt handlers have been run rather
 * than before
 */
void mn10300_set_lateack_irq_type(int irq)
{
	irq_set_chip_and_handler(irq, &mn10300_cpu_pic_level,
				 handle_level_irq);
}

/*
 * initialise the interrupt system
 */
void __init init_IRQ(void)
{
	int irq;

	for (irq = 0; irq < NR_IRQS; irq++)
		if (irq_get_chip(irq) == &no_irq_chip)
			/* due to the PIC latching interrupt requests, even
			 * when the IRQ is disabled, IRQ_PENDING is superfluous
			 * and we can use handle_level_irq() for edge-triggered
			 * interrupts */
			irq_set_chip_and_handler(irq, &mn10300_cpu_pic_edge,
						 handle_level_irq);

	unit_init_IRQ();
}

/*
 * handle normal device IRQs
 */
asmlinkage void do_IRQ(void)
{
	unsigned long sp, epsw, irq_disabled_epsw, old_irq_enabled_epsw;
	unsigned int cpu_id = smp_processor_id();
	int irq;

	sp = current_stack_pointer();
	BUG_ON(sp - (sp & ~(THREAD_SIZE - 1)) < STACK_WARN);

	/* make sure local_irq_enable() doesn't muck up the interrupt priority
	 * setting in EPSW */
	old_irq_enabled_epsw = __mn10300_irq_enabled_epsw[cpu_id];
	local_save_flags(epsw);
	__mn10300_irq_enabled_epsw[cpu_id] = EPSW_IE | (EPSW_IM & epsw);
	irq_disabled_epsw = EPSW_IE | MN10300_CLI_LEVEL;

#ifdef CONFIG_MN10300_WD_TIMER
	__IRQ_STAT(cpu_id, __irq_count)++;
#endif

	irq_enter();

	for (;;) {
		/* ask the interrupt controller for the next IRQ to process
		 * - the result we get depends on EPSW.IM
		 */
		irq = IAGR & IAGR_GN;
		if (!irq)
			break;

		local_irq_restore(irq_disabled_epsw);

		generic_handle_irq(irq >> 2);

		/* restore IRQ controls for IAGR access */
		local_irq_restore(epsw);
	}

	__mn10300_irq_enabled_epsw[cpu_id] = old_irq_enabled_epsw;

	irq_exit();
}

/*
 * Display interrupt management information through /proc/interrupts
 */
int arch_show_interrupts(struct seq_file *p, int prec)
{
#ifdef CONFIG_MN10300_WD_TIMER
	int j;

	seq_printf(p, "%*s: ", prec, "NMI");
	for (j = 0; j < NR_CPUS; j++)
		if (cpu_online(j))
			seq_printf(p, "%10u ", nmi_count(j));
	seq_putc(p, '\n');
#endif

	seq_printf(p, "%*s: ", prec, "ERR");
	seq_printf(p, "%10u\n", atomic_read(&irq_err_count));
	return 0;
}

#ifdef CONFIG_HOTPLUG_CPU
void migrate_irqs(void)
{
	int irq;
	unsigned int self, new;
	unsigned long flags;

	self = smp_processor_id();
	for (irq = 0; irq < NR_IRQS; irq++) {
		struct irq_data *data = irq_get_irq_data(irq);
		struct cpumask *mask = irq_data_get_affinity_mask(data);

		if (irqd_is_per_cpu(data))
			continue;

		if (cpumask_test_cpu(self, mask) &&
		    !cpumask_intersects(&irq_affinity[irq], cpu_online_mask)) {
			int cpu_id;
			cpu_id = cpumask_first(cpu_online_mask);
			cpumask_set_cpu(cpu_id, mask);
		}
		/* We need to operate irq_affinity_online atomically. */
		arch_local_cli_save(flags);
		if (irq_affinity_online[irq] == self) {
			u16 x, tmp;

			x = GxICR(irq);
			GxICR(irq) = x & GxICR_LEVEL;
			tmp = GxICR(irq);

			new = cpumask_any_and(mask, cpu_online_mask);
			irq_affinity_online[irq] = new;

			CROSS_GxICR(irq, new) =
				(x & GxICR_LEVEL) | GxICR_DETECT;
			tmp = CROSS_GxICR(irq, new);

			x &= GxICR_LEVEL | GxICR_ENABLE;
			if (GxICR(irq) & GxICR_REQUEST)
				x |= GxICR_REQUEST | GxICR_DETECT;
			CROSS_GxICR(irq, new) = x;
			tmp = CROSS_GxICR(irq, new);
		}
		arch_local_irq_restore(flags);
	}
}
#endif /* CONFIG_HOTPLUG_CPU */
Commit	Line	Data
b920de1b DH	1	/* MN10300 Arch-specific interrupt handling
	2	*
	3	* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
	4	* Written by David Howells (dhowells@redhat.com)
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public Licence
	8	* as published by the Free Software Foundation; either version
	9	* 2 of the Licence, or (at your option) any later version.
	10	*/
	11	#include <linux/module.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/kernel_stat.h>
	14	#include <linux/seq_file.h>
368dd5ac	15	#include <linux/cpumask.h>
b920de1b	16	#include <asm/setup.h>
368dd5ac	17	#include <asm/serial-regs.h>
b920de1b	18
368dd5ac AT	19	unsigned long __mn10300_irq_enabled_epsw[NR_CPUS] __cacheline_aligned_in_smp = {
	20	[0 ... NR_CPUS - 1] = EPSW_IE \| EPSW_IM_7
	21	};
b920de1b DH	22	EXPORT_SYMBOL(__mn10300_irq_enabled_epsw);
b920de1b DH	23
368dd5ac AT	24	#ifdef CONFIG_SMP
	25	static char irq_affinity_online[NR_IRQS] = {
	26	[0 ... NR_IRQS - 1] = 0
	27	};
	28
	29	#define NR_IRQ_WORDS ((NR_IRQS + 31) / 32)
	30	static unsigned long irq_affinity_request[NR_IRQ_WORDS] = {
	31	[0 ... NR_IRQ_WORDS - 1] = 0
	32	};
	33	#endif /* CONFIG_SMP */
	34
b920de1b DH	35	atomic_t irq_err_count;
	36
	37	/*
d6478fad	38	* MN10300 interrupt controller operations
b920de1b	39	*/
125bb1db	40	static void mn10300_cpupic_ack(struct irq_data *d)
b920de1b	41	{
125bb1db	42	unsigned int irq = d->irq;
368dd5ac AT	43	unsigned long flags;
	44	u16 tmp;
	45
	46	flags = arch_local_cli_save();
	47	GxICR_u8(irq) = GxICR_DETECT;
	48	tmp = GxICR(irq);
	49	arch_local_irq_restore(flags);
	50	}
	51
	52	static void __mask_and_set_icr(unsigned int irq,
	53	unsigned int mask, unsigned int set)
	54	{
	55	unsigned long flags;
b920de1b	56	u16 tmp;
368dd5ac AT	57
368dd5ac AT	58	flags = arch_local_cli_save();
b920de1b	59	tmp = GxICR(irq);
368dd5ac AT	60	GxICR(irq) = (tmp & mask) \| set;
	61	tmp = GxICR(irq);
	62	arch_local_irq_restore(flags);
b920de1b DH	63	}
b920de1b DH	64
125bb1db	65	static void mn10300_cpupic_mask(struct irq_data *d)
b920de1b	66	{
125bb1db	67	__mask_and_set_icr(d->irq, GxICR_LEVEL, 0);
b920de1b DH	68	}
b920de1b DH	69
125bb1db	70	static void mn10300_cpupic_mask_ack(struct irq_data *d)
b920de1b	71	{
125bb1db	72	unsigned int irq = d->irq;
368dd5ac AT	73	#ifdef CONFIG_SMP
	74	unsigned long flags;
	75	u16 tmp;
	76
	77	flags = arch_local_cli_save();
	78
	79	if (!test_and_clear_bit(irq, irq_affinity_request)) {
	80	tmp = GxICR(irq);
	81	GxICR(irq) = (tmp & GxICR_LEVEL) \| GxICR_DETECT;
	82	tmp = GxICR(irq);
	83	} else {
	84	u16 tmp2;
	85	tmp = GxICR(irq);
	86	GxICR(irq) = (tmp & GxICR_LEVEL);
	87	tmp2 = GxICR(irq);
	88
730c1fad	89	irq_affinity_online[irq] =
9d03e784 JL	90	cpumask_any_and(irq_data_get_affinity_mask(d),
9d03e784 JL	91	cpu_online_mask);
730c1fad MS	92	CROSS_GxICR(irq, irq_affinity_online[irq]) =
	93	(tmp & (GxICR_LEVEL \| GxICR_ENABLE)) \| GxICR_DETECT;
	94	tmp = CROSS_GxICR(irq, irq_affinity_online[irq]);
368dd5ac AT	95	}
	96
	97	arch_local_irq_restore(flags);
	98	#else /* CONFIG_SMP */
	99	__mask_and_set_icr(irq, GxICR_LEVEL, GxICR_DETECT);
	100	#endif /* CONFIG_SMP */
b920de1b DH	101	}
b920de1b DH	102
125bb1db	103	static void mn10300_cpupic_unmask(struct irq_data *d)
b920de1b	104	{
125bb1db	105	__mask_and_set_icr(d->irq, GxICR_LEVEL, GxICR_ENABLE);
b920de1b DH	106	}
b920de1b DH	107
125bb1db	108	static void mn10300_cpupic_unmask_clear(struct irq_data *d)
b920de1b	109	{
125bb1db	110	unsigned int irq = d->irq;
d6478fad DH	111	/* the MN10300 PIC latches its interrupt request bit, even after the
	112	* device has ceased to assert its interrupt line and the interrupt
	113	* channel has been disabled in the PIC, so for level-triggered
	114	* interrupts we need to clear the request bit when we re-enable */
368dd5ac AT	115	#ifdef CONFIG_SMP
	116	unsigned long flags;
	117	u16 tmp;
	118
	119	flags = arch_local_cli_save();
	120
	121	if (!test_and_clear_bit(irq, irq_affinity_request)) {
	122	tmp = GxICR(irq);
	123	GxICR(irq) = (tmp & GxICR_LEVEL) \| GxICR_ENABLE \| GxICR_DETECT;
	124	tmp = GxICR(irq);
	125	} else {
	126	tmp = GxICR(irq);
	127
9d03e784	128	irq_affinity_online[irq] = cpumask_any_and(irq_data_get_affinity_mask(d),
8ea9716f	129	cpu_online_mask);
730c1fad MS	130	CROSS_GxICR(irq, irq_affinity_online[irq]) = (tmp & GxICR_LEVEL) \| GxICR_ENABLE \| GxICR_DETECT;
730c1fad MS	131	tmp = CROSS_GxICR(irq, irq_affinity_online[irq]);
368dd5ac AT	132	}
	133
	134	arch_local_irq_restore(flags);
	135	#else /* CONFIG_SMP */
	136	__mask_and_set_icr(irq, GxICR_LEVEL, GxICR_ENABLE \| GxICR_DETECT);
	137	#endif /* CONFIG_SMP */
b920de1b DH	138	}
b920de1b DH	139
368dd5ac AT	140	#ifdef CONFIG_SMP
368dd5ac AT	141	static int
125bb1db TG	142	mn10300_cpupic_setaffinity(struct irq_data d, const struct cpumask mask,
125bb1db TG	143	bool force)
368dd5ac AT	144	{
368dd5ac AT	145	unsigned long flags;
368dd5ac AT	146
368dd5ac AT	147	flags = arch_local_cli_save();
7d361cb7	148	set_bit(d->irq, irq_affinity_request);
368dd5ac	149	arch_local_irq_restore(flags);
7d361cb7	150	return 0;
368dd5ac AT	151	}
	152	#endif /* CONFIG_SMP */
	153
d6478fad DH	154	/*
	155	* MN10300 PIC level-triggered IRQ handling.
	156	*
	157	* The PIC has no 'ACK' function per se. It is possible to clear individual
	158	* channel latches, but each latch relatches whether or not the channel is
	159	* masked, so we need to clear the latch when we unmask the channel.
	160	*
	161	* Also for this reason, we don't supply an ack() op (it's unused anyway if
	162	* mask_ack() is provided), and mask_ack() just masks.
	163	*/
	164	static struct irq_chip mn10300_cpu_pic_level = {
125bb1db TG	165	.name = "cpu_l",
	166	.irq_disable = mn10300_cpupic_mask,
	167	.irq_enable = mn10300_cpupic_unmask_clear,
	168	.irq_ack = NULL,
	169	.irq_mask = mn10300_cpupic_mask,
	170	.irq_mask_ack = mn10300_cpupic_mask,
	171	.irq_unmask = mn10300_cpupic_unmask_clear,
368dd5ac	172	#ifdef CONFIG_SMP
125bb1db	173	.irq_set_affinity = mn10300_cpupic_setaffinity,
730c1fad	174	#endif
d6478fad DH	175	};
	176
	177	/*
	178	* MN10300 PIC edge-triggered IRQ handling.
	179	*
	180	* We use the latch clearing function of the PIC as the 'ACK' function.
	181	*/
	182	static struct irq_chip mn10300_cpu_pic_edge = {
125bb1db TG	183	.name = "cpu_e",
	184	.irq_disable = mn10300_cpupic_mask,
	185	.irq_enable = mn10300_cpupic_unmask,
	186	.irq_ack = mn10300_cpupic_ack,
	187	.irq_mask = mn10300_cpupic_mask,
	188	.irq_mask_ack = mn10300_cpupic_mask_ack,
	189	.irq_unmask = mn10300_cpupic_unmask,
368dd5ac	190	#ifdef CONFIG_SMP
125bb1db	191	.irq_set_affinity = mn10300_cpupic_setaffinity,
730c1fad	192	#endif
b920de1b DH	193	};
	194
	195	/*
	196	* 'what should we do if we get a hw irq event on an illegal vector'.
	197	* each architecture has to answer this themselves.
	198	*/
	199	void ack_bad_irq(int irq)
	200	{
	201	printk(KERN_WARNING "unexpected IRQ trap at vector %02x\n", irq);
	202	}
	203
	204	/*
	205	* change the level at which an IRQ executes
	206	* - must not be called whilst interrupts are being processed!
	207	*/
	208	void set_intr_level(int irq, u16 level)
	209	{
368dd5ac	210	BUG_ON(in_interrupt());
b920de1b	211
368dd5ac AT	212	__mask_and_set_icr(irq, GxICR_ENABLE, level);
368dd5ac AT	213	}
b920de1b	214
b920de1b DH	215	/*
	216	* mark an interrupt to be ACK'd after interrupt handlers have been run rather
	217	* than before
b920de1b	218	*/
368dd5ac	219	void mn10300_set_lateack_irq_type(int irq)
b920de1b	220	{
f4c547eb	221	irq_set_chip_and_handler(irq, &mn10300_cpu_pic_level,
d6478fad	222	handle_level_irq);
b920de1b DH	223	}
	224
	225	/*
	226	* initialise the interrupt system
	227	*/
	228	void __init init_IRQ(void)
	229	{
	230	int irq;
	231
	232	for (irq = 0; irq < NR_IRQS; irq++)
f4c547eb	233	if (irq_get_chip(irq) == &no_irq_chip)
d6478fad DH	234	/* due to the PIC latching interrupt requests, even
	235	* when the IRQ is disabled, IRQ_PENDING is superfluous
	236	* and we can use handle_level_irq() for edge-triggered
	237	* interrupts */
f4c547eb	238	irq_set_chip_and_handler(irq, &mn10300_cpu_pic_edge,
d6478fad	239	handle_level_irq);
368dd5ac	240
b920de1b DH	241	unit_init_IRQ();
	242	}
	243
	244	/*
	245	* handle normal device IRQs
	246	*/
	247	asmlinkage void do_IRQ(void)
	248	{
	249	unsigned long sp, epsw, irq_disabled_epsw, old_irq_enabled_epsw;
368dd5ac	250	unsigned int cpu_id = smp_processor_id();
b920de1b DH	251	int irq;
	252
	253	sp = current_stack_pointer();
292aa141	254	BUG_ON(sp - (sp & ~(THREAD_SIZE - 1)) < STACK_WARN);
b920de1b DH	255
	256	/* make sure local_irq_enable() doesn't muck up the interrupt priority
	257	* setting in EPSW */
368dd5ac	258	old_irq_enabled_epsw = __mn10300_irq_enabled_epsw[cpu_id];
b920de1b	259	local_save_flags(epsw);
368dd5ac	260	__mn10300_irq_enabled_epsw[cpu_id] = EPSW_IE \| (EPSW_IM & epsw);
b920de1b DH	261	irq_disabled_epsw = EPSW_IE \| MN10300_CLI_LEVEL;
b920de1b DH	262
368dd5ac AT	263	#ifdef CONFIG_MN10300_WD_TIMER
	264	__IRQ_STAT(cpu_id, __irq_count)++;
	265	#endif
b920de1b DH	266
	267	irq_enter();
	268
	269	for (;;) {
	270	/* ask the interrupt controller for the next IRQ to process
	271	* - the result we get depends on EPSW.IM
	272	*/
	273	irq = IAGR & IAGR_GN;
	274	if (!irq)
	275	break;
	276
	277	local_irq_restore(irq_disabled_epsw);
	278
	279	generic_handle_irq(irq >> 2);
	280
	281	/* restore IRQ controls for IAGR access */
	282	local_irq_restore(epsw);
	283	}
	284
368dd5ac	285	__mn10300_irq_enabled_epsw[cpu_id] = old_irq_enabled_epsw;
b920de1b DH	286
	287	irq_exit();
	288	}
	289
	290	/*
	291	* Display interrupt management information through /proc/interrupts
	292	*/
2a8f55b1	293	int arch_show_interrupts(struct seq_file *p, int prec)
b920de1b	294	{
368dd5ac	295	#ifdef CONFIG_MN10300_WD_TIMER
2a8f55b1	296	int j;
b920de1b	297
2a8f55b1 TG	298	seq_printf(p, "%*s: ", prec, "NMI");
	299	for (j = 0; j < NR_CPUS; j++)
	300	if (cpu_online(j))
	301	seq_printf(p, "%10u ", nmi_count(j));
	302	seq_putc(p, '\n');
	303	#endif
b920de1b	304
2a8f55b1 TG	305	seq_printf(p, "%*s: ", prec, "ERR");
2a8f55b1 TG	306	seq_printf(p, "%10u\n", atomic_read(&irq_err_count));
b920de1b DH	307	return 0;
b920de1b DH	308	}
368dd5ac AT	309
	310	#ifdef CONFIG_HOTPLUG_CPU
	311	void migrate_irqs(void)
	312	{
368dd5ac AT	313	int irq;
	314	unsigned int self, new;
	315	unsigned long flags;
	316
	317	self = smp_processor_id();
	318	for (irq = 0; irq < NR_IRQS; irq++) {
232f1d85	319	struct irq_data *data = irq_get_irq_data(irq);
9d03e784	320	struct cpumask *mask = irq_data_get_affinity_mask(data);
368dd5ac	321
232f1d85	322	if (irqd_is_per_cpu(data))
368dd5ac AT	323	continue;
368dd5ac AT	324
9d03e784	325	if (cpumask_test_cpu(self, mask) &&
8ea9716f	326	!cpumask_intersects(&irq_affinity[irq], cpu_online_mask)) {
368dd5ac	327	int cpu_id;
8ea9716f	328	cpu_id = cpumask_first(cpu_online_mask);
9d03e784	329	cpumask_set_cpu(cpu_id, mask);
368dd5ac AT	330	}
	331	/* We need to operate irq_affinity_online atomically. */
	332	arch_local_cli_save(flags);
	333	if (irq_affinity_online[irq] == self) {
	334	u16 x, tmp;
	335
730c1fad MS	336	x = GxICR(irq);
	337	GxICR(irq) = x & GxICR_LEVEL;
	338	tmp = GxICR(irq);
368dd5ac	339
9d03e784	340	new = cpumask_any_and(mask, cpu_online_mask);
368dd5ac AT	341	irq_affinity_online[irq] = new;
	342
	343	CROSS_GxICR(irq, new) =
	344	(x & GxICR_LEVEL) \| GxICR_DETECT;
	345	tmp = CROSS_GxICR(irq, new);
	346
	347	x &= GxICR_LEVEL \| GxICR_ENABLE;
d9a1abe4	348	if (GxICR(irq) & GxICR_REQUEST)
368dd5ac AT	349	x \|= GxICR_REQUEST \| GxICR_DETECT;
	350	CROSS_GxICR(irq, new) = x;
	351	tmp = CROSS_GxICR(irq, new);
	352	}
	353	arch_local_irq_restore(flags);
	354	}
	355	}
	356	#endif /* CONFIG_HOTPLUG_CPU */