MN10300: Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB control
[deliverable/linux.git] / arch / mn10300 / mm / Makefile
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1#
2# Makefile for the MN10300-specific memory management code
3#
4
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5cache-smp-wback-$(CONFIG_MN10300_CACHE_WBACK) := cache-smp-flush.o
6
518d4bb7 7cacheflush-y := cache.o
8be06289 8cacheflush-$(CONFIG_SMP) += cache-smp.o cache-smp-inv.o $(cache-smp-wback-y)
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9cacheflush-$(CONFIG_MN10300_CACHE_INV_ICACHE) += cache-inv-icache.o
10cacheflush-$(CONFIG_MN10300_CACHE_FLUSH_ICACHE) += cache-flush-icache.o
518d4bb7 11cacheflush-$(CONFIG_MN10300_CACHE_INV_BY_TAG) += cache-inv-by-tag.o
9731d237 12cacheflush-$(CONFIG_MN10300_CACHE_INV_BY_REG) += cache-inv-by-reg.o
518d4bb7 13cacheflush-$(CONFIG_MN10300_CACHE_FLUSH_BY_TAG) += cache-flush-by-tag.o
9731d237 14cacheflush-$(CONFIG_MN10300_CACHE_FLUSH_BY_REG) += cache-flush-by-reg.o
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15
16cacheflush-$(CONFIG_MN10300_CACHE_DISABLED) := cache-disabled.o
17
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18obj-y := \
19 init.o fault.o pgtable.o extable.o tlb-mn10300.o mmu-context.o \
62bdb288 20 misalignment.o dma-alloc.o $(cacheflush-y)
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