[deliverable/linux.git] / arch / mn10300 / mm / misalignment.c

/* MN10300 Misalignment fixup handler
 *
 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
 * Written by David Howells (dhowells@redhat.com)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public Licence
 * as published by the Free Software Foundation; either version
 * 2 of the Licence, or (at your option) any later version.
 */
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/errno.h>
#include <linux/ptrace.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/smp.h>
#include <linux/smp_lock.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <asm/processor.h>
#include <asm/system.h>
#include <asm/uaccess.h>
#include <asm/io.h>
#include <asm/atomic.h>
#include <asm/smp.h>
#include <asm/pgalloc.h>
#include <asm/cpu-regs.h>
#include <asm/busctl-regs.h>
#include <asm/fpu.h>
#include <asm/gdb-stub.h>
#include <asm/asm-offsets.h>

#if 0
#define kdebug(FMT, ...) printk(KERN_DEBUG "MISALIGN: "FMT"\n", ##__VA_ARGS__)
#else
#define kdebug(FMT, ...) do {} while (0)
#endif

static int misalignment_addr(unsigned long *registers, unsigned params,
			     unsigned opcode, unsigned disp,
			     void **_address, unsigned long **_postinc);

static int misalignment_reg(unsigned long *registers, unsigned params,
			    unsigned opcode, unsigned disp,
			    unsigned long **_register);

static const unsigned Dreg_index[] = {
	REG_D0 >> 2, REG_D1 >> 2, REG_D2 >> 2, REG_D3 >> 2
};

static const unsigned Areg_index[] = {
	REG_A0 >> 2, REG_A1 >> 2, REG_A2 >> 2, REG_A3 >> 2
};

static const unsigned Rreg_index[] = {
	REG_E0 >> 2, REG_E1 >> 2, REG_E2 >> 2, REG_E3 >> 2,
	REG_E4 >> 2, REG_E5 >> 2, REG_E6 >> 2, REG_E7 >> 2,
	REG_A0 >> 2, REG_A1 >> 2, REG_A2 >> 2, REG_A3 >> 2,
	REG_D0 >> 2, REG_D1 >> 2, REG_D2 >> 2, REG_D3 >> 2
};

enum format_id {
	FMT_S0,
	FMT_S1,
	FMT_S2,
	FMT_S4,
	FMT_D0,
	FMT_D1,
	FMT_D2,
	FMT_D4,
	FMT_D6,
	FMT_D7,
	FMT_D8,
	FMT_D9,
};

static const struct {
	u_int8_t opsz, dispsz;
} format_tbl[16] = {
	[FMT_S0]	= { 8,	0	},
	[FMT_S1]	= { 8,	8	},
	[FMT_S2]	= { 8,	16	},
	[FMT_S4]	= { 8,	32	},
	[FMT_D0]	= { 16,	0	},
	[FMT_D1]	= { 16,	8	},
	[FMT_D2]	= { 16,	16	},
	[FMT_D4]	= { 16,	32	},
	[FMT_D6]	= { 24,	0	},
	[FMT_D7]	= { 24,	8	},
	[FMT_D8]	= { 24,	24	},
	[FMT_D9]	= { 24,	32	},
};

enum value_id {
	DM0,		/* data reg in opcode in bits 0-1 */
	DM1,		/* data reg in opcode in bits 2-3 */
	DM2,		/* data reg in opcode in bits 4-5 */
	AM0,		/* addr reg in opcode in bits 0-1 */
	AM1,		/* addr reg in opcode in bits 2-3 */
	AM2,		/* addr reg in opcode in bits 4-5 */
	RM0,		/* reg in opcode in bits 0-3 */
	RM1,		/* reg in opcode in bits 2-5 */
	RM2,		/* reg in opcode in bits 4-7 */
	RM4,		/* reg in opcode in bits 8-11 */
	RM6,		/* reg in opcode in bits 12-15 */

	RD0,		/* reg in displacement in bits 0-3 */
	RD2,		/* reg in displacement in bits 4-7 */

	SP,		/* stack pointer */

	SD8,		/* 8-bit signed displacement */
	SD16,		/* 16-bit signed displacement */
	SD24,		/* 24-bit signed displacement */
	SIMM4_2,	/* 4-bit signed displacement in opcode bits 4-7 */
	SIMM8,		/* 8-bit signed immediate */
	IMM24,		/* 24-bit unsigned immediate */
	IMM32,		/* 32-bit unsigned immediate */
	IMM32_HIGH8,	/* 32-bit unsigned immediate, high 8-bits in opcode */

	DN0	= DM0,
	DN1	= DM1,
	DN2	= DM2,
	AN0	= AM0,
	AN1	= AM1,
	AN2	= AM2,
	RN0	= RM0,
	RN1	= RM1,
	RN2	= RM2,
	RN4	= RM4,
	RN6	= RM6,
	DI	= DM1,
	RI	= RM2,

};

struct mn10300_opcode {
	const char	*name;
	u_int32_t	opcode;
	u_int32_t	opmask;
	unsigned	exclusion;

	enum format_id	format;

	unsigned	cpu_mask;
#define AM33	330

	unsigned	params[2];
#define MEM(ADDR)		(0x80000000 | (ADDR))
#define MEM2(ADDR1, ADDR2)	(0x80000000 | (ADDR1) << 8 | (ADDR2))
#define MEMINC(ADDR)		(0x81000000 | (ADDR))
#define MEMINC2(ADDR, INC)	(0x81000000 | (ADDR) << 8 | (INC))
};

/* LIBOPCODES EXCERPT
   Assemble Matsushita MN10300 instructions.
   Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public Licence as published by
   the Free Software Foundation; either version 2 of the Licence, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public Licence for more details.

   You should have received a copy of the GNU General Public Licence
   along with this program; if not, write to the Free Software
   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
static const struct mn10300_opcode mn10300_opcodes[] = {
{ "mov",	0x60,	     0xf0,	  0,    FMT_S0, 0,	{DM1, MEM(AN0)}},
{ "mov",	0x70,	     0xf0,	  0,    FMT_S0, 0,	{MEM(AM0), DN1}},
{ "mov",	0xf000,	     0xfff0,	  0,    FMT_D0, 0,	{MEM(AM0), AN1}},
{ "mov",	0xf010,	     0xfff0,	  0,    FMT_D0, 0,	{AM1, MEM(AN0)}},
{ "mov",	0xf300,	     0xffc0,	  0,    FMT_D0, 0,	{MEM2(DI, AM0), DN2}},
{ "mov",	0xf340,	     0xffc0,	  0,    FMT_D0, 0,	{DM2, MEM2(DI, AN0)}},
{ "mov",	0xf380,	     0xffc0,	  0,    FMT_D0, 0,	{MEM2(DI, AM0), AN2}},
{ "mov",	0xf3c0,	     0xffc0,	  0,    FMT_D0, 0,	{AM2, MEM2(DI, AN0)}},
{ "mov",	0xf80000,    0xfff000,    0,    FMT_D1, 0,	{MEM2(SD8, AM0), DN1}},
{ "mov",	0xf81000,    0xfff000,    0,    FMT_D1, 0,	{DM1, MEM2(SD8, AN0)}},
{ "mov",	0xf82000,    0xfff000,    0,    FMT_D1, 0,	{MEM2(SD8,AM0), AN1}},
{ "mov",	0xf83000,    0xfff000,    0,    FMT_D1, 0,	{AM1, MEM2(SD8, AN0)}},
{ "mov",	0xf8f000,    0xfffc00,    0,    FMT_D1, AM33,	{MEM2(SD8, AM0), SP}},
{ "mov",	0xf8f400,    0xfffc00,    0,    FMT_D1, AM33,	{SP, MEM2(SD8, AN0)}},
{ "mov",	0xf90a00,    0xffff00,    0,    FMT_D6, AM33,	{MEM(RM0), RN2}},
{ "mov",	0xf91a00,    0xffff00,    0,    FMT_D6, AM33,	{RM2, MEM(RN0)}},
{ "mov",	0xf96a00,    0xffff00,    0x12, FMT_D6, AM33,	{MEMINC(RM0), RN2}},
{ "mov",	0xf97a00,    0xffff00,    0,	FMT_D6, AM33,	{RM2, MEMINC(RN0)}},
{ "mov",	0xfa000000,  0xfff00000,  0,    FMT_D2, 0,	{MEM2(SD16, AM0), DN1}},
{ "mov",	0xfa100000,  0xfff00000,  0,    FMT_D2, 0,	{DM1, MEM2(SD16, AN0)}},
{ "mov",	0xfa200000,  0xfff00000,  0,    FMT_D2, 0,	{MEM2(SD16, AM0), AN1}},
{ "mov",	0xfa300000,  0xfff00000,  0,    FMT_D2, 0,	{AM1, MEM2(SD16, AN0)}},
{ "mov",	0xfb0a0000,  0xffff0000,  0,    FMT_D7, AM33,	{MEM2(SD8, RM0), RN2}},
{ "mov",	0xfb1a0000,  0xffff0000,  0,    FMT_D7, AM33,	{RM2, MEM2(SD8, RN0)}},
{ "mov",	0xfb6a0000,  0xffff0000,  0x22, FMT_D7, AM33,	{MEMINC2 (RM0, SIMM8), RN2}},
{ "mov",	0xfb7a0000,  0xffff0000,  0,	FMT_D7, AM33,	{RM2, MEMINC2 (RN0, SIMM8)}},
{ "mov",	0xfb8e0000,  0xffff000f,  0,    FMT_D7, AM33,	{MEM2(RI, RM0), RD2}},
{ "mov",	0xfb9e0000,  0xffff000f,  0,    FMT_D7, AM33,	{RD2, MEM2(RI, RN0)}},
{ "mov",	0xfc000000,  0xfff00000,  0,    FMT_D4, 0,	{MEM2(IMM32,AM0), DN1}},
{ "mov",	0xfc100000,  0xfff00000,  0,    FMT_D4, 0,	{DM1, MEM2(IMM32,AN0)}},
{ "mov",	0xfc200000,  0xfff00000,  0,    FMT_D4, 0,	{MEM2(IMM32,AM0), AN1}},
{ "mov",	0xfc300000,  0xfff00000,  0,    FMT_D4, 0,	{AM1, MEM2(IMM32,AN0)}},
{ "mov",	0xfd0a0000,  0xffff0000,  0,    FMT_D8, AM33,	{MEM2(SD24, RM0), RN2}},
{ "mov",	0xfd1a0000,  0xffff0000,  0,    FMT_D8, AM33,	{RM2, MEM2(SD24, RN0)}},
{ "mov",	0xfd6a0000,  0xffff0000,  0x22, FMT_D8, AM33,	{MEMINC2 (RM0, IMM24), RN2}},
{ "mov",	0xfd7a0000,  0xffff0000,  0,	FMT_D8, AM33,	{RM2, MEMINC2 (RN0, IMM24)}},
{ "mov",	0xfe0a0000,  0xffff0000,  0,    FMT_D9, AM33,	{MEM2(IMM32_HIGH8,RM0), RN2}},
{ "mov",	0xfe1a0000,  0xffff0000,  0,    FMT_D9, AM33,	{RM2, MEM2(IMM32_HIGH8, RN0)}},
{ "mov",	0xfe6a0000,  0xffff0000,  0x22, FMT_D9, AM33,	{MEMINC2 (RM0, IMM32_HIGH8), RN2}},
{ "mov",	0xfe7a0000,  0xffff0000,  0,	FMT_D9, AM33,	{RN2, MEMINC2 (RM0, IMM32_HIGH8)}},

{ "movhu",	0xf060,	     0xfff0,	  0,    FMT_D0, 0,	{MEM(AM0), DN1}},
{ "movhu",	0xf070,	     0xfff0,	  0,    FMT_D0, 0,	{DM1, MEM(AN0)}},
{ "movhu",	0xf480,	     0xffc0,	  0,    FMT_D0, 0,	{MEM2(DI, AM0), DN2}},
{ "movhu",	0xf4c0,	     0xffc0,	  0,    FMT_D0, 0,	{DM2, MEM2(DI, AN0)}},
{ "movhu",	0xf86000,    0xfff000,    0,    FMT_D1, 0,	{MEM2(SD8, AM0), DN1}},
{ "movhu",	0xf87000,    0xfff000,    0,    FMT_D1, 0,	{DM1, MEM2(SD8, AN0)}},
{ "movhu",	0xf94a00,    0xffff00,    0,    FMT_D6, AM33,	{MEM(RM0), RN2}},
{ "movhu",	0xf95a00,    0xffff00,    0,    FMT_D6, AM33,	{RM2, MEM(RN0)}},
{ "movhu",	0xf9ea00,    0xffff00,    0x12, FMT_D6, AM33,	{MEMINC(RM0), RN2}},
{ "movhu",	0xf9fa00,    0xffff00,    0,	FMT_D6, AM33,	{RM2, MEMINC(RN0)}},
{ "movhu",	0xfa600000,  0xfff00000,  0,    FMT_D2, 0,	{MEM2(SD16, AM0), DN1}},
{ "movhu",	0xfa700000,  0xfff00000,  0,    FMT_D2, 0,	{DM1, MEM2(SD16, AN0)}},
{ "movhu",	0xfb4a0000,  0xffff0000,  0,    FMT_D7, AM33,	{MEM2(SD8, RM0), RN2}},
{ "movhu",	0xfb5a0000,  0xffff0000,  0,    FMT_D7, AM33,	{RM2, MEM2(SD8, RN0)}},
{ "movhu",	0xfbce0000,  0xffff000f,  0,    FMT_D7, AM33,	{MEM2(RI, RM0), RD2}},
{ "movhu",	0xfbde0000,  0xffff000f,  0,    FMT_D7, AM33,	{RD2, MEM2(RI, RN0)}},
{ "movhu",	0xfbea0000,  0xffff0000,  0x22, FMT_D7, AM33,	{MEMINC2 (RM0, SIMM8), RN2}},
{ "movhu",	0xfbfa0000,  0xffff0000,  0,	FMT_D7, AM33,	{RM2, MEMINC2 (RN0, SIMM8)}},
{ "movhu",	0xfc600000,  0xfff00000,  0,    FMT_D4, 0,	{MEM2(IMM32,AM0), DN1}},
{ "movhu",	0xfc700000,  0xfff00000,  0,    FMT_D4, 0,	{DM1, MEM2(IMM32,AN0)}},
{ "movhu",	0xfd4a0000,  0xffff0000,  0,    FMT_D8, AM33,	{MEM2(SD24, RM0), RN2}},
{ "movhu",	0xfd5a0000,  0xffff0000,  0,    FMT_D8, AM33,	{RM2, MEM2(SD24, RN0)}},
{ "movhu",	0xfdea0000,  0xffff0000,  0x22, FMT_D8, AM33,	{MEMINC2 (RM0, IMM24), RN2}},
{ "movhu",	0xfdfa0000,  0xffff0000,  0,	FMT_D8, AM33,	{RM2, MEMINC2 (RN0, IMM24)}},
{ "movhu",	0xfe4a0000,  0xffff0000,  0,    FMT_D9, AM33,	{MEM2(IMM32_HIGH8,RM0), RN2}},
{ "movhu",	0xfe5a0000,  0xffff0000,  0,    FMT_D9, AM33,	{RM2, MEM2(IMM32_HIGH8, RN0)}},
{ "movhu",	0xfeea0000,  0xffff0000,  0x22, FMT_D9, AM33,	{MEMINC2 (RM0, IMM32_HIGH8), RN2}},
{ "movhu",	0xfefa0000,  0xffff0000,  0,	FMT_D9, AM33,	{RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
{ 0, 0, 0, 0, 0, 0, {0}},
};

/*
 * fix up misalignment problems where possible
 */
asmlinkage void misalignment(struct pt_regs *regs, enum exception_code code)
{
	const struct exception_table_entry *fixup;
	const struct mn10300_opcode *pop;
	unsigned long *registers = (unsigned long *) regs;
	unsigned long data, *store, *postinc;
	mm_segment_t seg;
	siginfo_t info;
	uint32_t opcode, disp, noc, xo, xm;
	uint8_t *pc, byte;
	void *address;
	unsigned tmp, npop;

	kdebug("==>misalignment({pc=%lx})", regs->pc);

	if (in_interrupt())
		die("Misalignment trap in interrupt context", regs, code);

	if (regs->epsw & EPSW_IE)
		asm volatile("or %0,epsw" : : "i"(EPSW_IE));

	seg = get_fs();
	set_fs(KERNEL_DS);

	fixup = search_exception_tables(regs->pc);

	/* first thing to do is to match the opcode */
	pc = (u_int8_t *) regs->pc;

	if (__get_user(byte, pc) != 0)
		goto fetch_error;
	opcode = byte;
	noc = 8;

	for (pop = mn10300_opcodes; pop->name; pop++) {
		npop = ilog2(pop->opcode | pop->opmask);
		if (npop <= 0 || npop > 31)
			continue;
		npop = (npop + 8) & ~7;

	got_more_bits:
		if (npop == noc) {
			if ((opcode & pop->opmask) == pop->opcode)
				goto found_opcode;
		} else if (npop > noc) {
			xo = pop->opcode >> (npop - noc);
			xm = pop->opmask >> (npop - noc);

			if ((opcode & xm) != xo)
				continue;

			/* we've got a partial match (an exact match on the
			 * first N bytes), so we need to get some more data */
			pc++;
			if (__get_user(byte, pc) != 0)
				goto fetch_error;
			opcode = opcode << 8 | byte;
			noc += 8;
			goto got_more_bits;
		} else {
			/* there's already been a partial match as long as the
			 * complete match we're now considering, so this one
			 * should't match */
			continue;
		}
	}

	/* didn't manage to find a fixup */
	if (!user_mode(regs))
		printk(KERN_CRIT "MISALIGN: %lx: unsupported instruction %x\n",
		       regs->pc, opcode);

failed:
	set_fs(seg);
	if (die_if_no_fixup("misalignment error", regs, code))
		return;

	info.si_signo	= SIGBUS;
	info.si_errno	= 0;
	info.si_code	= BUS_ADRALN;
	info.si_addr	= (void *) regs->pc;
	force_sig_info(SIGBUS, &info, current);
	return;

	/* error reading opcodes */
fetch_error:
	if (!user_mode(regs))
		printk(KERN_CRIT
		       "MISALIGN: %p: fault whilst reading instruction data\n",
		       pc);
	goto failed;

bad_addr_mode:
	if (!user_mode(regs))
		printk(KERN_CRIT
		       "MISALIGN: %lx: unsupported addressing mode %x\n",
		       regs->pc, opcode);
	goto failed;

bad_reg_mode:
	if (!user_mode(regs))
		printk(KERN_CRIT
		       "MISALIGN: %lx: unsupported register mode %x\n",
		       regs->pc, opcode);
	goto failed;

unsupported_instruction:
	if (!user_mode(regs))
		printk(KERN_CRIT
		       "MISALIGN: %lx: unsupported instruction %x (%s)\n",
		       regs->pc, opcode, pop->name);
	goto failed;

transfer_failed:
	set_fs(seg);
	if (fixup) {
		regs->pc = fixup->fixup;
		return;
	}
	if (die_if_no_fixup("misalignment fixup", regs, code))
		return;

	info.si_signo	= SIGSEGV;
	info.si_errno	= 0;
	info.si_code	= 0;
	info.si_addr	= (void *) regs->pc;
	force_sig_info(SIGSEGV, &info, current);
	return;

	/* we matched the opcode */
found_opcode:
	kdebug("%lx: %x==%x { %x, %x }",
	       regs->pc, opcode, pop->opcode, pop->params[0], pop->params[1]);

	tmp = format_tbl[pop->format].opsz;
	if (tmp > noc)
		BUG(); /* match was less complete than it ought to have been */

	if (tmp < noc) {
		tmp = noc - tmp;
		opcode >>= tmp;
		pc -= tmp >> 3;
	}

	/* grab the extra displacement (note it's LSB first) */
	disp = 0;
	tmp = format_tbl[pop->format].dispsz >> 3;
	while (tmp > 0) {
		tmp--;
		disp <<= 8;

		pc++;
		if (__get_user(byte, pc) != 0)
			goto fetch_error;
		disp |= byte;
	}

	set_fs(KERNEL_XDS);
	if (fixup || regs->epsw & EPSW_nSL)
		set_fs(seg);

	tmp = (pop->params[0] ^ pop->params[1]) & 0x80000000;
	if (!tmp) {
		if (!user_mode(regs))
			printk(KERN_CRIT
			       "MISALIGN: %lx:"
			       " insn not move to/from memory %x\n",
			       regs->pc, opcode);
		goto failed;
	}

	if (pop->params[0] & 0x80000000) {
		/* move memory to register */
		if (!misalignment_addr(registers, pop->params[0], opcode, disp,
				       &address, &postinc))
			goto bad_addr_mode;

		if (!misalignment_reg(registers, pop->params[1], opcode, disp,
				      &store))
			goto bad_reg_mode;

		if (strcmp(pop->name, "mov") == 0) {
			kdebug("mov (%p),DARn", address);
			if (copy_from_user(&data, (void *) address, 4) != 0)
				goto transfer_failed;
			if (pop->params[0] & 0x1000000)
				*postinc += 4;
		} else if (strcmp(pop->name, "movhu") == 0) {
			kdebug("movhu (%p),DARn", address);
			data = 0;
			if (copy_from_user(&data, (void *) address, 2) != 0)
				goto transfer_failed;
			if (pop->params[0] & 0x1000000)
				*postinc += 2;
		} else {
			goto unsupported_instruction;
		}

		*store = data;
	} else {
		/* move register to memory */
		if (!misalignment_reg(registers, pop->params[0], opcode, disp,
				      &store))
			goto bad_reg_mode;

		if (!misalignment_addr(registers, pop->params[1], opcode, disp,
				       &address, &postinc))
			goto bad_addr_mode;

		data = *store;

		if (strcmp(pop->name, "mov") == 0) {
			kdebug("mov %lx,(%p)", data, address);
			if (copy_to_user((void *) address, &data, 4) != 0)
				goto transfer_failed;
			if (pop->params[1] & 0x1000000)
				*postinc += 4;
		} else if (strcmp(pop->name, "movhu") == 0) {
			kdebug("movhu %hx,(%p)", (uint16_t) data, address);
			if (copy_to_user((void *) address, &data, 2) != 0)
				goto transfer_failed;
			if (pop->params[1] & 0x1000000)
				*postinc += 2;
		} else {
			goto unsupported_instruction;
		}
	}

	tmp = format_tbl[pop->format].opsz + format_tbl[pop->format].dispsz;
	regs->pc += tmp >> 3;

	set_fs(seg);
	return;
}

/*
 * determine the address that was being accessed
 */
static int misalignment_addr(unsigned long *registers, unsigned params,
			     unsigned opcode, unsigned disp,
			     void **_address, unsigned long **_postinc)
{
	unsigned long *postinc = NULL, address = 0, tmp;

	params &= 0x7fffffff;

	do {
		switch (params & 0xff) {
		case DM0:
			postinc = &registers[Dreg_index[opcode & 0x03]];
			address += *postinc;
			break;
		case DM1:
			postinc = &registers[Dreg_index[opcode >> 2 & 0x0c]];
			address += *postinc;
			break;
		case DM2:
			postinc = &registers[Dreg_index[opcode >> 4 & 0x30]];
			address += *postinc;
			break;
		case AM0:
			postinc = &registers[Areg_index[opcode & 0x03]];
			address += *postinc;
			break;
		case AM1:
			postinc = &registers[Areg_index[opcode >> 2 & 0x0c]];
			address += *postinc;
			break;
		case AM2:
			postinc = &registers[Areg_index[opcode >> 4 & 0x30]];
			address += *postinc;
			break;
		case RM0:
			postinc = &registers[Rreg_index[opcode & 0x0f]];
			address += *postinc;
			break;
		case RM1:
			postinc = &registers[Rreg_index[opcode >> 2 & 0x0f]];
			address += *postinc;
			break;
		case RM2:
			postinc = &registers[Rreg_index[opcode >> 4 & 0x0f]];
			address += *postinc;
			break;
		case RM4:
			postinc = &registers[Rreg_index[opcode >> 8 & 0x0f]];
			address += *postinc;
			break;
		case RM6:
			postinc = &registers[Rreg_index[opcode >> 12 & 0x0f]];
			address += *postinc;
			break;
		case RD0:
			postinc = &registers[Rreg_index[disp & 0x0f]];
			address += *postinc;
			break;
		case RD2:
			postinc = &registers[Rreg_index[disp >> 4 & 0x0f]];
			address += *postinc;
			break;

		case SD8:
		case SIMM8:
			address += (int32_t) (int8_t) (disp & 0xff);
			break;
		case SD16:
			address += (int32_t) (int16_t) (disp & 0xffff);
			break;
		case SD24:
			tmp = disp << 8;
			asm("asr 8,%0" : "=r"(tmp) : "0"(tmp));
			address += tmp;
			break;
		case SIMM4_2:
			tmp = opcode >> 4 & 0x0f;
			tmp <<= 28;
			asm("asr 28,%0" : "=r"(tmp) : "0"(tmp));
			address += tmp;
			break;
		case IMM24:
			address += disp & 0x00ffffff;
			break;
		case IMM32:
		case IMM32_HIGH8:
			address += disp;
			break;
		default:
			return 0;
		}
	} while ((params >>= 8));

	*_address = (void *) address;
	*_postinc = postinc;
	return 1;
}

/*
 * determine the register that is acting as source/dest
 */
static int misalignment_reg(unsigned long *registers, unsigned params,
			    unsigned opcode, unsigned disp,
			    unsigned long **_register)
{
	params &= 0x7fffffff;

	if (params & 0xffffff00)
		return 0;

	switch (params & 0xff) {
	case DM0:
		*_register = &registers[Dreg_index[opcode & 0x03]];
		break;
	case DM1:
		*_register = &registers[Dreg_index[opcode >> 2 & 0x03]];
		break;
	case DM2:
		*_register = &registers[Dreg_index[opcode >> 4 & 0x03]];
		break;
	case AM0:
		*_register = &registers[Areg_index[opcode & 0x03]];
		break;
	case AM1:
		*_register = &registers[Areg_index[opcode >> 2 & 0x03]];
		break;
	case AM2:
		*_register = &registers[Areg_index[opcode >> 4 & 0x03]];
		break;
	case RM0:
		*_register = &registers[Rreg_index[opcode & 0x0f]];
		break;
	case RM1:
		*_register = &registers[Rreg_index[opcode >> 2 & 0x0f]];
		break;
	case RM2:
		*_register = &registers[Rreg_index[opcode >> 4 & 0x0f]];
		break;
	case RM4:
		*_register = &registers[Rreg_index[opcode >> 8 & 0x0f]];
		break;
	case RM6:
		*_register = &registers[Rreg_index[opcode >> 12 & 0x0f]];
		break;
	case RD0:
		*_register = &registers[Rreg_index[disp & 0x0f]];
		break;
	case RD2:
		*_register = &registers[Rreg_index[disp >> 4 & 0x0f]];
		break;
	case SP:
		*_register = &registers[REG_SP >> 2];
		break;

	default:
		return 0;
	}

	return 1;
}
Commit	Line	Data
b920de1b DH	1	/* MN10300 Misalignment fixup handler
	2	*
	3	* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
	4	* Written by David Howells (dhowells@redhat.com)
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public Licence
	8	* as published by the Free Software Foundation; either version
	9	* 2 of the Licence, or (at your option) any later version.
	10	*/
	11	#include <linux/module.h>
	12	#include <linux/sched.h>
	13	#include <linux/kernel.h>
	14	#include <linux/string.h>
	15	#include <linux/errno.h>
	16	#include <linux/ptrace.h>
	17	#include <linux/timer.h>
	18	#include <linux/mm.h>
	19	#include <linux/smp.h>
	20	#include <linux/smp_lock.h>
	21	#include <linux/init.h>
	22	#include <linux/delay.h>
	23	#include <linux/spinlock.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/pci.h>
	26	#include <asm/processor.h>
	27	#include <asm/system.h>
	28	#include <asm/uaccess.h>
	29	#include <asm/io.h>
	30	#include <asm/atomic.h>
	31	#include <asm/smp.h>
	32	#include <asm/pgalloc.h>
	33	#include <asm/cpu-regs.h>
	34	#include <asm/busctl-regs.h>
	35	#include <asm/fpu.h>
	36	#include <asm/gdb-stub.h>
	37	#include <asm/asm-offsets.h>
	38
	39	#if 0
31ea24bb	40	#define kdebug(FMT, ...) printk(KERN_DEBUG "MISALIGN: "FMT"\n", ##__VA_ARGS__)
b920de1b DH	41	#else
	42	#define kdebug(FMT, ...) do {} while (0)
	43	#endif
	44
	45	static int misalignment_addr(unsigned long *registers, unsigned params,
	46	unsigned opcode, unsigned disp,
	47	void _address, unsigned long _postinc);
	48
	49	static int misalignment_reg(unsigned long *registers, unsigned params,
	50	unsigned opcode, unsigned disp,
	51	unsigned long **_register);
	52
b920de1b DH	53	static const unsigned Dreg_index[] = {
	54	REG_D0 >> 2, REG_D1 >> 2, REG_D2 >> 2, REG_D3 >> 2
	55	};
	56
	57	static const unsigned Areg_index[] = {
	58	REG_A0 >> 2, REG_A1 >> 2, REG_A2 >> 2, REG_A3 >> 2
	59	};
	60
	61	static const unsigned Rreg_index[] = {
	62	REG_E0 >> 2, REG_E1 >> 2, REG_E2 >> 2, REG_E3 >> 2,
	63	REG_E4 >> 2, REG_E5 >> 2, REG_E6 >> 2, REG_E7 >> 2,
	64	REG_A0 >> 2, REG_A1 >> 2, REG_A2 >> 2, REG_A3 >> 2,
	65	REG_D0 >> 2, REG_D1 >> 2, REG_D2 >> 2, REG_D3 >> 2
	66	};
	67
	68	enum format_id {
	69	FMT_S0,
	70	FMT_S1,
	71	FMT_S2,
	72	FMT_S4,
	73	FMT_D0,
	74	FMT_D1,
	75	FMT_D2,
	76	FMT_D4,
	77	FMT_D6,
	78	FMT_D7,
	79	FMT_D8,
	80	FMT_D9,
	81	};
	82
31ea24bb	83	static const struct {
b920de1b DH	84	u_int8_t opsz, dispsz;
	85	} format_tbl[16] = {
	86	[FMT_S0] = { 8, 0 },
	87	[FMT_S1] = { 8, 8 },
	88	[FMT_S2] = { 8, 16 },
	89	[FMT_S4] = { 8, 32 },
	90	[FMT_D0] = { 16, 0 },
	91	[FMT_D1] = { 16, 8 },
	92	[FMT_D2] = { 16, 16 },
	93	[FMT_D4] = { 16, 32 },
	94	[FMT_D6] = { 24, 0 },
	95	[FMT_D7] = { 24, 8 },
	96	[FMT_D8] = { 24, 24 },
	97	[FMT_D9] = { 24, 32 },
	98	};
	99
	100	enum value_id {
	101	DM0, /* data reg in opcode in bits 0-1 */
	102	DM1, /* data reg in opcode in bits 2-3 */
	103	DM2, /* data reg in opcode in bits 4-5 */
	104	AM0, /* addr reg in opcode in bits 0-1 */
	105	AM1, /* addr reg in opcode in bits 2-3 */
	106	AM2, /* addr reg in opcode in bits 4-5 */
	107	RM0, /* reg in opcode in bits 0-3 */
	108	RM1, /* reg in opcode in bits 2-5 */
	109	RM2, /* reg in opcode in bits 4-7 */
	110	RM4, /* reg in opcode in bits 8-11 */
	111	RM6, /* reg in opcode in bits 12-15 */
	112
	113	RD0, /* reg in displacement in bits 0-3 */
	114	RD2, /* reg in displacement in bits 4-7 */
	115
	116	SP, /* stack pointer */
	117
	118	SD8, /* 8-bit signed displacement */
	119	SD16, /* 16-bit signed displacement */
	120	SD24, /* 24-bit signed displacement */
	121	SIMM4_2, /* 4-bit signed displacement in opcode bits 4-7 */
	122	SIMM8, /* 8-bit signed immediate */
	123	IMM24, /* 24-bit unsigned immediate */
	124	IMM32, /* 32-bit unsigned immediate */
	125	IMM32_HIGH8, /* 32-bit unsigned immediate, high 8-bits in opcode */
	126
	127	DN0 = DM0,
	128	DN1 = DM1,
	129	DN2 = DM2,
	130	AN0 = AM0,
	131	AN1 = AM1,
	132	AN2 = AM2,
	133	RN0 = RM0,
	134	RN1 = RM1,
	135	RN2 = RM2,
	136	RN4 = RM4,
	137	RN6 = RM6,
	138	DI = DM1,
	139	RI = RM2,
	140
	141	};
	142
	143	struct mn10300_opcode {
	144	const char *name;
	145	u_int32_t opcode;
	146	u_int32_t opmask;
	147	unsigned exclusion;
148
149	enum format_id format;
150
151	unsigned cpu_mask;
152	#define AM33 330
153
154	unsigned params[2];
155	#define MEM(ADDR) (0x80000000 \| (ADDR))
156	#define MEM2(ADDR1, ADDR2) (0x80000000 \| (ADDR1) << 8 \| (ADDR2))
157	#define MEMINC(ADDR) (0x81000000 \| (ADDR))
158	#define MEMINC2(ADDR, INC) (0x81000000 \| (ADDR) << 8 \| (INC))
159	};
160
161	/* LIBOPCODES EXCERPT
162	Assemble Matsushita MN10300 instructions.
163	Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
164
165	This program is free software; you can redistribute it and/or modify
166	it under the terms of the GNU General Public Licence as published by
167	the Free Software Foundation; either version 2 of the Licence, or
168	(at your option) any later version.
169
170	This program is distributed in the hope that it will be useful,
171	but WITHOUT ANY WARRANTY; without even the implied warranty of
172	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
173	GNU General Public Licence for more details.
174
175	You should have received a copy of the GNU General Public Licence
176	along with this program; if not, write to the Free Software
177	Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
178	*/
179	static const struct mn10300_opcode mn10300_opcodes[] = {
180	{ "mov", 0x60, 0xf0, 0, FMT_S0, 0, {DM1, MEM(AN0)}},
181	{ "mov", 0x70, 0xf0, 0, FMT_S0, 0, {MEM(AM0), DN1}},
182	{ "mov", 0xf000, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), AN1}},
183	{ "mov", 0xf010, 0xfff0, 0, FMT_D0, 0, {AM1, MEM(AN0)}},
184	{ "mov", 0xf300, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
185	{ "mov", 0xf340, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
186	{ "mov", 0xf380, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), AN2}},
187	{ "mov", 0xf3c0, 0xffc0, 0, FMT_D0, 0, {AM2, MEM2(DI, AN0)}},
188	{ "mov", 0xf80000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
189	{ "mov", 0xf81000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
190	{ "mov", 0xf82000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8,AM0), AN1}},
191	{ "mov", 0xf83000, 0xfff000, 0, FMT_D1, 0, {AM1, MEM2(SD8, AN0)}},
192	{ "mov", 0xf8f000, 0xfffc00, 0, FMT_D1, AM33, {MEM2(SD8, AM0), SP}},
193	{ "mov", 0xf8f400, 0xfffc00, 0, FMT_D1, AM33, {SP, MEM2(SD8, AN0)}},
194	{ "mov", 0xf90a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}},
195	{ "mov", 0xf91a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}},
196	{ "mov", 0xf96a00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}},
197	{ "mov", 0xf97a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}},
198	{ "mov", 0xfa000000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
199	{ "mov", 0xfa100000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
200	{ "mov", 0xfa200000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), AN1}},
201	{ "mov", 0xfa300000, 0xfff00000, 0, FMT_D2, 0, {AM1, MEM2(SD16, AN0)}},
202	{ "mov", 0xfb0a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
203	{ "mov", 0xfb1a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
204	{ "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}},
205	{ "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
206	{ "mov", 0xfb8e0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
207	{ "mov", 0xfb9e0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
208	{ "mov", 0xfc000000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
209	{ "mov", 0xfc100000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
210	{ "mov", 0xfc200000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), AN1}},
211	{ "mov", 0xfc300000, 0xfff00000, 0, FMT_D4, 0, {AM1, MEM2(IMM32,AN0)}},
212	{ "mov", 0xfd0a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
213	{ "mov", 0xfd1a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
214	{ "mov", 0xfd6a0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}},
215	{ "mov", 0xfd7a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
216	{ "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
217	{ "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
218	{ "mov", 0xfe6a0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}},
219	{ "mov", 0xfe7a0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
220
221	{ "movhu", 0xf060, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), DN1}},
222	{ "movhu", 0xf070, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}},
223	{ "movhu", 0xf480, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
224	{ "movhu", 0xf4c0, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
225	{ "movhu", 0xf86000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
226	{ "movhu", 0xf87000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
227	{ "movhu", 0xf94a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}},
228	{ "movhu", 0xf95a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}},
229	{ "movhu", 0xf9ea00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}},
230	{ "movhu", 0xf9fa00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}},
231	{ "movhu", 0xfa600000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
232	{ "movhu", 0xfa700000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
233	{ "movhu", 0xfb4a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
234	{ "movhu", 0xfb5a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
235	{ "movhu", 0xfbce0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
236	{ "movhu", 0xfbde0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
237	{ "movhu", 0xfbea0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}},
238	{ "movhu", 0xfbfa0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
239	{ "movhu", 0xfc600000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
240	{ "movhu", 0xfc700000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
241	{ "movhu", 0xfd4a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
242	{ "movhu", 0xfd5a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
243	{ "movhu", 0xfdea0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}},
244	{ "movhu", 0xfdfa0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
245	{ "movhu", 0xfe4a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
246	{ "movhu", 0xfe5a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
247	{ "movhu", 0xfeea0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}},
248	{ "movhu", 0xfefa0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
249	{ 0, 0, 0, 0, 0, 0, {0}},
250	};
251
252	/*
253	* fix up misalignment problems where possible
254	*/
255	asmlinkage void misalignment(struct pt_regs *regs, enum exception_code code)
256	{
257	const struct exception_table_entry *fixup;
258	const struct mn10300_opcode *pop;
259	unsigned long registers = (unsigned long ) regs;
260	unsigned long data, store, postinc;
261	mm_segment_t seg;
262	siginfo_t info;
263	uint32_t opcode, disp, noc, xo, xm;
264	uint8_t *pc, byte;
265	void *address;
266	unsigned tmp, npop;
267
31ea24bb	268	kdebug("==>misalignment({pc=%lx})", regs->pc);
b920de1b DH	269
	270	if (in_interrupt())
	271	die("Misalignment trap in interrupt context", regs, code);
	272
	273	if (regs->epsw & EPSW_IE)
	274	asm volatile("or %0,epsw" : : "i"(EPSW_IE));
	275
	276	seg = get_fs();
	277	set_fs(KERNEL_DS);
	278
	279	fixup = search_exception_tables(regs->pc);
	280
	281	/* first thing to do is to match the opcode */
	282	pc = (u_int8_t *) regs->pc;
	283
	284	if (__get_user(byte, pc) != 0)
	285	goto fetch_error;
	286	opcode = byte;
	287	noc = 8;
	288
	289	for (pop = mn10300_opcodes; pop->name; pop++) {
31ea24bb	290	npop = ilog2(pop->opcode \| pop->opmask);
b920de1b DH	291	if (npop <= 0 \|\| npop > 31)
	292	continue;
	293	npop = (npop + 8) & ~7;
	294
	295	got_more_bits:
	296	if (npop == noc) {
	297	if ((opcode & pop->opmask) == pop->opcode)
	298	goto found_opcode;
	299	} else if (npop > noc) {
	300	xo = pop->opcode >> (npop - noc);
	301	xm = pop->opmask >> (npop - noc);
	302
	303	if ((opcode & xm) != xo)
	304	continue;
	305
	306	/* we've got a partial match (an exact match on the
	307	* first N bytes), so we need to get some more data */
	308	pc++;
	309	if (__get_user(byte, pc) != 0)
	310	goto fetch_error;
	311	opcode = opcode << 8 \| byte;
	312	noc += 8;
	313	goto got_more_bits;
	314	} else {
	315	/* there's already been a partial match as long as the
	316	* complete match we're now considering, so this one
	317	* should't match */
	318	continue;
	319	}
	320	}
	321
	322	/* didn't manage to find a fixup */
	323	if (!user_mode(regs))
	324	printk(KERN_CRIT "MISALIGN: %lx: unsupported instruction %x\n",
	325	regs->pc, opcode);
	326
	327	failed:
	328	set_fs(seg);
	329	if (die_if_no_fixup("misalignment error", regs, code))
	330	return;
	331
	332	info.si_signo = SIGBUS;
	333	info.si_errno = 0;
	334	info.si_code = BUS_ADRALN;
	335	info.si_addr = (void *) regs->pc;
	336	force_sig_info(SIGBUS, &info, current);
	337	return;
	338
	339	/* error reading opcodes */
	340	fetch_error:
	341	if (!user_mode(regs))
	342	printk(KERN_CRIT
	343	"MISALIGN: %p: fault whilst reading instruction data\n",
	344	pc);
	345	goto failed;
	346
	347	bad_addr_mode:
	348	if (!user_mode(regs))
	349	printk(KERN_CRIT
	350	"MISALIGN: %lx: unsupported addressing mode %x\n",
	351	regs->pc, opcode);
	352	goto failed;
	353
	354	bad_reg_mode:
355	if (!user_mode(regs))
356	printk(KERN_CRIT
357	"MISALIGN: %lx: unsupported register mode %x\n",
358	regs->pc, opcode);
359	goto failed;
360
361	unsupported_instruction:
362	if (!user_mode(regs))
363	printk(KERN_CRIT
364	"MISALIGN: %lx: unsupported instruction %x (%s)\n",
365	regs->pc, opcode, pop->name);
366	goto failed;
367
368	transfer_failed:
369	set_fs(seg);
370	if (fixup) {
371	regs->pc = fixup->fixup;
372	return;
373	}
374	if (die_if_no_fixup("misalignment fixup", regs, code))
375	return;
376
377	info.si_signo = SIGSEGV;
378	info.si_errno = 0;
379	info.si_code = 0;
380	info.si_addr = (void *) regs->pc;
381	force_sig_info(SIGSEGV, &info, current);
382	return;
383
384	/* we matched the opcode */
385	found_opcode:
31ea24bb	386	kdebug("%lx: %x==%x { %x, %x }",
b920de1b DH	387	regs->pc, opcode, pop->opcode, pop->params[0], pop->params[1]);
	388
	389	tmp = format_tbl[pop->format].opsz;
	390	if (tmp > noc)
	391	BUG(); /* match was less complete than it ought to have been */
	392
	393	if (tmp < noc) {
	394	tmp = noc - tmp;
	395	opcode >>= tmp;
	396	pc -= tmp >> 3;
	397	}
	398
	399	/* grab the extra displacement (note it's LSB first) */
	400	disp = 0;
	401	tmp = format_tbl[pop->format].dispsz >> 3;
	402	while (tmp > 0) {
	403	tmp--;
	404	disp <<= 8;
	405
	406	pc++;
	407	if (__get_user(byte, pc) != 0)
	408	goto fetch_error;
	409	disp \|= byte;
	410	}
	411
	412	set_fs(KERNEL_XDS);
	413	if (fixup \|\| regs->epsw & EPSW_nSL)
	414	set_fs(seg);
	415
	416	tmp = (pop->params[0] ^ pop->params[1]) & 0x80000000;
	417	if (!tmp) {
	418	if (!user_mode(regs))
	419	printk(KERN_CRIT
	420	"MISALIGN: %lx:"
	421	" insn not move to/from memory %x\n",
	422	regs->pc, opcode);
	423	goto failed;
	424	}
	425
	426	if (pop->params[0] & 0x80000000) {
	427	/* move memory to register */
	428	if (!misalignment_addr(registers, pop->params[0], opcode, disp,
	429	&address, &postinc))
	430	goto bad_addr_mode;
	431
	432	if (!misalignment_reg(registers, pop->params[1], opcode, disp,
	433	&store))
	434	goto bad_reg_mode;
	435
	436	if (strcmp(pop->name, "mov") == 0) {
31ea24bb	437	kdebug("mov (%p),DARn", address);
b920de1b DH	438	if (copy_from_user(&data, (void *) address, 4) != 0)
	439	goto transfer_failed;
	440	if (pop->params[0] & 0x1000000)
	441	*postinc += 4;
	442	} else if (strcmp(pop->name, "movhu") == 0) {
31ea24bb	443	kdebug("movhu (%p),DARn", address);
b920de1b DH	444	data = 0;
	445	if (copy_from_user(&data, (void *) address, 2) != 0)
	446	goto transfer_failed;
	447	if (pop->params[0] & 0x1000000)
	448	*postinc += 2;
	449	} else {
	450	goto unsupported_instruction;
	451	}
	452
	453	*store = data;
	454	} else {
	455	/* move register to memory */
	456	if (!misalignment_reg(registers, pop->params[0], opcode, disp,
	457	&store))
	458	goto bad_reg_mode;
	459
	460	if (!misalignment_addr(registers, pop->params[1], opcode, disp,
	461	&address, &postinc))
	462	goto bad_addr_mode;
	463
	464	data = *store;
	465
	466	if (strcmp(pop->name, "mov") == 0) {
31ea24bb	467	kdebug("mov %lx,(%p)", data, address);
b920de1b DH	468	if (copy_to_user((void *) address, &data, 4) != 0)
	469	goto transfer_failed;
	470	if (pop->params[1] & 0x1000000)
	471	*postinc += 4;
	472	} else if (strcmp(pop->name, "movhu") == 0) {
31ea24bb	473	kdebug("movhu %hx,(%p)", (uint16_t) data, address);
b920de1b DH	474	if (copy_to_user((void *) address, &data, 2) != 0)
	475	goto transfer_failed;
	476	if (pop->params[1] & 0x1000000)
	477	*postinc += 2;
	478	} else {
	479	goto unsupported_instruction;
	480	}
	481	}
	482
	483	tmp = format_tbl[pop->format].opsz + format_tbl[pop->format].dispsz;
	484	regs->pc += tmp >> 3;
	485
	486	set_fs(seg);
	487	return;
	488	}
	489
	490	/*
	491	* determine the address that was being accessed
	492	*/
	493	static int misalignment_addr(unsigned long *registers, unsigned params,
	494	unsigned opcode, unsigned disp,
	495	void _address, unsigned long _postinc)
	496	{
	497	unsigned long *postinc = NULL, address = 0, tmp;
	498
	499	params &= 0x7fffffff;
	500
	501	do {
	502	switch (params & 0xff) {
	503	case DM0:
	504	postinc = &registers[Dreg_index[opcode & 0x03]];
	505	address += *postinc;
	506	break;
	507	case DM1:
	508	postinc = &registers[Dreg_index[opcode >> 2 & 0x0c]];
	509	address += *postinc;
	510	break;
	511	case DM2:
	512	postinc = &registers[Dreg_index[opcode >> 4 & 0x30]];
	513	address += *postinc;
	514	break;
	515	case AM0:
	516	postinc = &registers[Areg_index[opcode & 0x03]];
	517	address += *postinc;
	518	break;
	519	case AM1:
	520	postinc = &registers[Areg_index[opcode >> 2 & 0x0c]];
	521	address += *postinc;
	522	break;
	523	case AM2:
	524	postinc = &registers[Areg_index[opcode >> 4 & 0x30]];
	525	address += *postinc;
	526	break;
	527	case RM0:
	528	postinc = &registers[Rreg_index[opcode & 0x0f]];
	529	address += *postinc;
	530	break;
	531	case RM1:
	532	postinc = &registers[Rreg_index[opcode >> 2 & 0x0f]];
	533	address += *postinc;
	534	break;
	535	case RM2:
	536	postinc = &registers[Rreg_index[opcode >> 4 & 0x0f]];
	537	address += *postinc;
538	break;
539	case RM4:
540	postinc = &registers[Rreg_index[opcode >> 8 & 0x0f]];
541	address += *postinc;
542	break;
543	case RM6:
544	postinc = &registers[Rreg_index[opcode >> 12 & 0x0f]];
545	address += *postinc;
546	break;
547	case RD0:
548	postinc = &registers[Rreg_index[disp & 0x0f]];
549	address += *postinc;
550	break;
551	case RD2:
552	postinc = &registers[Rreg_index[disp >> 4 & 0x0f]];
553	address += *postinc;
554	break;
555
556	case SD8:
557	case SIMM8:
558	address += (int32_t) (int8_t) (disp & 0xff);
559	break;
560	case SD16:
561	address += (int32_t) (int16_t) (disp & 0xffff);
562	break;
563	case SD24:
564	tmp = disp << 8;
565	asm("asr 8,%0" : "=r"(tmp) : "0"(tmp));
566	address += tmp;
567	break;
568	case SIMM4_2:
569	tmp = opcode >> 4 & 0x0f;
570	tmp <<= 28;
571	asm("asr 28,%0" : "=r"(tmp) : "0"(tmp));
572	address += tmp;
573	break;
574	case IMM24:
575	address += disp & 0x00ffffff;
576	break;
577	case IMM32:
578	case IMM32_HIGH8:
579	address += disp;
580	break;
581	default:
582	return 0;
583	}
584	} while ((params >>= 8));
585
586	_address = (void ) address;
587	*_postinc = postinc;
588	return 1;
589	}
590
591	/*
592	* determine the register that is acting as source/dest
593	*/
594	static int misalignment_reg(unsigned long *registers, unsigned params,
595	unsigned opcode, unsigned disp,
596	unsigned long **_register)
597	{
598	params &= 0x7fffffff;
599
600	if (params & 0xffffff00)
601	return 0;
602
603	switch (params & 0xff) {
604	case DM0:
605	*_register = &registers[Dreg_index[opcode & 0x03]];
606	break;
607	case DM1:
608	*_register = &registers[Dreg_index[opcode >> 2 & 0x03]];
609	break;
610	case DM2:
611	*_register = &registers[Dreg_index[opcode >> 4 & 0x03]];
612	break;
613	case AM0:
614	*_register = &registers[Areg_index[opcode & 0x03]];
615	break;
616	case AM1:
617	*_register = &registers[Areg_index[opcode >> 2 & 0x03]];
618	break;
619	case AM2:
620	*_register = &registers[Areg_index[opcode >> 4 & 0x03]];
621	break;
622	case RM0:
623	*_register = &registers[Rreg_index[opcode & 0x0f]];
624	break;
625	case RM1:
626	*_register = &registers[Rreg_index[opcode >> 2 & 0x0f]];
627	break;
628	case RM2:
629	*_register = &registers[Rreg_index[opcode >> 4 & 0x0f]];
630	break;
631	case RM4:
632	*_register = &registers[Rreg_index[opcode >> 8 & 0x0f]];
633	break;
634	case RM6:
635	*_register = &registers[Rreg_index[opcode >> 12 & 0x0f]];
636	break;
637	case RD0:
638	*_register = &registers[Rreg_index[disp & 0x0f]];
639	break;
640	case RD2:
641	*_register = &registers[Rreg_index[disp >> 4 & 0x0f]];
642	break;
643	case SP:
644	*_register = &registers[REG_SP >> 2];
645	break;
646
647	default:
648	return 0;
649	}
650
651	return 1;
652	}