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368dd5ac AT |
1 | /* MN2WS0050 processor initialisation |
2 | * | |
3 | * Copyright (C) 2005 Red Hat, Inc. All Rights Reserved. | |
4 | * Written by David Howells (dhowells@redhat.com) | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | #include <linux/sched.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/interrupt.h> | |
16 | ||
17 | #include <asm/processor.h> | |
18 | #include <asm/system.h> | |
19 | #include <asm/uaccess.h> | |
20 | #include <asm/io.h> | |
60063497 | 21 | #include <linux/atomic.h> |
368dd5ac AT |
22 | #include <asm/smp.h> |
23 | #include <asm/pgalloc.h> | |
24 | #include <asm/busctl-regs.h> | |
25 | #include <unit/timex.h> | |
26 | #include <asm/fpu.h> | |
27 | #include <asm/rtc.h> | |
28 | ||
29 | #define MEMCONF __SYSREGC(0xdf800400, u32) | |
30 | ||
31 | /* | |
32 | * initialise the on-silicon processor peripherals | |
33 | */ | |
34 | asmlinkage void __init processor_init(void) | |
35 | { | |
36 | int loop; | |
37 | ||
38 | /* set up the exception table first */ | |
39 | for (loop = 0x000; loop < 0x400; loop += 8) | |
40 | __set_intr_stub(loop, __common_exception); | |
41 | ||
42 | __set_intr_stub(EXCEP_ITLBMISS, itlb_miss); | |
43 | __set_intr_stub(EXCEP_DTLBMISS, dtlb_miss); | |
44 | __set_intr_stub(EXCEP_IAERROR, itlb_aerror); | |
45 | __set_intr_stub(EXCEP_DAERROR, dtlb_aerror); | |
46 | __set_intr_stub(EXCEP_BUSERROR, raw_bus_error); | |
47 | __set_intr_stub(EXCEP_DOUBLE_FAULT, double_fault); | |
48 | __set_intr_stub(EXCEP_FPU_DISABLED, fpu_disabled); | |
49 | __set_intr_stub(EXCEP_SYSCALL0, system_call); | |
50 | ||
51 | __set_intr_stub(EXCEP_NMI, nmi_handler); | |
52 | __set_intr_stub(EXCEP_WDT, nmi_handler); | |
53 | __set_intr_stub(EXCEP_IRQ_LEVEL0, irq_handler); | |
54 | __set_intr_stub(EXCEP_IRQ_LEVEL1, irq_handler); | |
55 | __set_intr_stub(EXCEP_IRQ_LEVEL2, irq_handler); | |
56 | __set_intr_stub(EXCEP_IRQ_LEVEL3, irq_handler); | |
57 | __set_intr_stub(EXCEP_IRQ_LEVEL4, irq_handler); | |
58 | __set_intr_stub(EXCEP_IRQ_LEVEL5, irq_handler); | |
59 | __set_intr_stub(EXCEP_IRQ_LEVEL6, irq_handler); | |
60 | ||
61 | IVAR0 = EXCEP_IRQ_LEVEL0; | |
62 | IVAR1 = EXCEP_IRQ_LEVEL1; | |
63 | IVAR2 = EXCEP_IRQ_LEVEL2; | |
64 | IVAR3 = EXCEP_IRQ_LEVEL3; | |
65 | IVAR4 = EXCEP_IRQ_LEVEL4; | |
66 | IVAR5 = EXCEP_IRQ_LEVEL5; | |
67 | IVAR6 = EXCEP_IRQ_LEVEL6; | |
68 | ||
69 | #ifndef CONFIG_MN10300_HAS_CACHE_SNOOP | |
70 | mn10300_dcache_flush_inv(); | |
71 | mn10300_icache_inv(); | |
72 | #endif | |
73 | ||
74 | /* disable all interrupts and set to priority 6 (lowest) */ | |
75 | #ifdef CONFIG_SMP | |
76 | for (loop = 0; loop < GxICR_NUM_IRQS; loop++) | |
77 | GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT; | |
78 | #else /* !CONFIG_SMP */ | |
79 | for (loop = 0; loop < NR_IRQS; loop++) | |
80 | GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT; | |
81 | #endif /* !CONFIG_SMP */ | |
82 | ||
83 | /* clear the timers */ | |
84 | TM0MD = 0; | |
85 | TM1MD = 0; | |
86 | TM2MD = 0; | |
87 | TM3MD = 0; | |
88 | TM4MD = 0; | |
89 | TM5MD = 0; | |
90 | TM6MD = 0; | |
91 | TM6MDA = 0; | |
92 | TM6MDB = 0; | |
93 | TM7MD = 0; | |
94 | TM8MD = 0; | |
95 | TM9MD = 0; | |
96 | TM10MD = 0; | |
97 | TM11MD = 0; | |
98 | TM12MD = 0; | |
99 | TM13MD = 0; | |
100 | TM14MD = 0; | |
101 | TM15MD = 0; | |
102 | ||
103 | calibrate_clock(); | |
104 | } | |
105 | ||
106 | /* | |
107 | * determine the memory size and base from the memory controller regs | |
108 | */ | |
109 | void __init get_mem_info(unsigned long *mem_base, unsigned long *mem_size) | |
110 | { | |
111 | unsigned long memconf = MEMCONF; | |
112 | unsigned long size = 0; /* order: MByte */ | |
113 | ||
114 | *mem_base = 0x90000000; /* fixed address */ | |
115 | ||
116 | switch (memconf & 0x00000003) { | |
117 | case 0x01: | |
118 | size = 256 / 8; /* 256 Mbit per chip */ | |
119 | break; | |
120 | case 0x02: | |
121 | size = 512 / 8; /* 512 Mbit per chip */ | |
122 | break; | |
123 | case 0x03: | |
124 | size = 1024 / 8; /* 1 Gbit per chip */ | |
125 | break; | |
126 | default: | |
127 | panic("Invalid SDRAM size"); | |
128 | break; | |
129 | } | |
130 | ||
131 | printk(KERN_INFO "DDR2-SDRAM: %luMB x 2 @%08lx\n", size, *mem_base); | |
132 | ||
133 | *mem_size = (size * 2) << 20; | |
134 | } |